CURRENTLY AND ADVANCED PIXEL DESIGNS FOR HEP Patrick Pangaud
Centre de Physique des Particules de Marseille C.P.P.M 163, avenue
de Luminy Case 902 13288 Marseille cedex 09 France
[email protected] USTC, April 11, 2013Patrick Pangaud -
CPPM-IN2P3-CNRS1 Slide 2 HYBRID PIXELS SENSOR FOR HIGH ENERGY
PHYSICS IBM 130nm : FEI4 development TSMC 65nm : FEI5 develpment
TEZZARON 3D 130nm: FETC4 developments HVCMOS development USTC,
April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS2 Slide 3 Hybrid
Pixels Detector for LHC/HL-LHC at CERN USTC, April 11, 2013Patrick
Pangaud - CPPM-IN2P3-CNRS3 LHC : Luminosity of 10 34 cm -2.s -1
HL-LHC expected 10 times more luminosity, more pixels, more
ionizing particles, more !!! Whatever will be discovered in next
years at LHC, need much data to understand what has been
discovered. Higher luminosity allows extending discovery/studies to
higher masses processes of lower cross-section LHC has plans of
upgrade by increasing luminosity to collect ultimately ~ 3000 fb
-1. This will open new physics possibilities. Slide 4 Inner
Tracking ATLAS detector USTC, April 11, 2013Patrick Pangaud -
CPPM-IN2P3-CNRS4 Straw tubes Silicon strip Silicon pixel Slide 5
LHC and ATLAS upgrade USTC, April 11, 2013Patrick Pangaud -
CPPM-IN2P3-CNRS5 L dt Year phase-0 phase-1 phase-2 2013/142018~2022
7 TeV 14 TeV 10 27 2x10 33 cm -2 s -1 1x10 34 cm -2 s -1 1x10 34
~2x10 34 cm -2 s -1 Now ~10 fb -1 ~50 fb -1 ~300 fb -1 3000 fb -1
5x10 34 cm -2 s -1 luminosity leveling Possible upgrade timeline T.
Kawamoto, TIPP2011, Chicago, USA Slide 6 ATLAS upgrade USTC, April
11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS6 LHC improves, bulk of
luminosity with instantaneous luminosity beyond the nominal
luminosity for which the ATLAS detector was designed and built.
Technology improves, can build better performing detector now.
Detectors age, after the nominal integrated luminosity has been
collected, leading to deterioration of performance during the runs
at higher luminosity. It will take long time to study and build new
detector Installation has to be done during the limited number of
long shut downs Installation has to be planned to be prepared to
the new running condition T. Kawamoto, TIPP2011, Chicago, USA Slide
7 IBM 130nm FE-I4 DEVELOPMENT USTC, April 11, 2013Patrick Pangaud -
CPPM-IN2P3-CNRS7 HYBRID PIXELS SENSOR FOR HIGH ENERGY PHYSICS Slide
8 Hybrid Pixels Sensor for HEP The FE-I4 readout chip 50 m FE-I3
CMOS technology : 250 nm 400 m 250 m FE-I4 CMOS technology : 130 nm
Done : ATLAS/LHC (2008/2009) Under Production ATLAS/LHC upgrade
project (2013-2014) USTC, April 11, 2013Patrick Pangaud -
CPPM-IN2P3-CNRS8 Participating institutes: Bonn Bonn: D. Arutinov,
M. Barbero, T. Hemperek, A. Kruth, M. Karagounis. CPPM CPPM: D.
Fougeron, M. Menouni. Genova: R. Beccherle, G. Darbo. LBNL LBNL: S.
Dube, D. Elledge, M. Garcia-Sciveres, D. Gnani, A. Mekkaoui. Nikhef
Nikhef: V. Gromov, R. Kluit, J.D. Schipper 160 18 FE-I3 FE-I4 Slide
9 FE-I4 : Motivation for Redesign of FE USTC, April 11, 2013Patrick
Pangaud - CPPM-IN2P3-CNRS9 Need for a new FE? Smaller b-layer
radius + potential luminosity increase higher hit rate. FE-I3
column-drain architecture saturated. FE-I4 new digital
architecture: local regional memories, stop moving hits around
(unless RO). FE-I4 has smaller pixel (reduced cross-section). New
technology: Higher integration density for digital circuits,
rad-hard, availibility. 0.25 m 130 nm FE-I3 FE-I4 Hit prob. / DC
Inefficiency [%] LHC IBL sLHC FE-I3 at r=3.7 cm! The inefficiency
wall 100 80 60 40 20 0 012345 6 7 8 910 M. Backhaus, FEI4 course,
Desy, Germany Slide 10 Future FE-I4-Based Module and Consequences
for FE-I4 USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS10
Increased active area: from less than 75 % to ~90 %: Reduced
periphery; bigger IC; cost down for sLHC (main driver is flip-chip
costs per chip). No MCC: More digital functionality in the IC.
Power: Analog design for reduced currents; decrease of digital
activity (digital logic sharing for neighbor pixels); new powering
concepts. 8 metal layers [2 thick Alu.] power routing. FE-Chip
Sensor Flex 1 1 2 2 3 3 4 1) Big chip (periphery on one side of
module). 2) Reduce size of periphery (2.8 mm 2 mm). 3) Thin down FE
chips (190 m 90 m). 4) Thin down the sensor (250 m 200 m)? 5) Less
cables (powering scheme)? 5 challenging: power (routing, start-up),
clk. distrib., simulation / management, yield 4 M. Backhaus, FEI4
course, Desy, Germany Slide 11 Motivation for Redesign of FE USTC,
April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS11 Need for a new
FE? Accommodate higher hit rate (smaller b-layer radius +
luminosity increase) Architecture based on local memories (no
column-drain mechanism). Smaller pixel size: enhanced granularity
and reduced cross-section. Reduced periphery & bigger chip:
higher active area fraction ( 3D Test results : FE-TC4-AEDS chip
Shielding studies with Digital Simple Moreover, to determine the
best shielding strategy, different metal shielding have been
implemented on the DS chip : Sh i e l d M e t al 3 a n d M etal 5
Sh i e l d M e t al 5 No Sh i e l d Sh i e l d Me t a l 3 No S hi e
l d Shielding configuration depending on column numbers : Col 0 and
1 => shield in Metal 3 and Metal 5 Col 2, 3, 4, 5 => shield
in Metal 5 Col 6, 7, 8 => no shield Col 9 and 10 => shield in
Metal 3 Col 11, 12, 13 => no shielded USTC, April 11,
2013Patrick Pangaud - CPPM-IN2P3-CNRS41 Slide 42 3D Test results :
FE-TC4-AEDS chip Shielding studies with Digital Simple First try
Comparison No Drums / All Drums S curves measurements noise = 116
e- 150 e- 250 e- 350 e- 800 e- A shielding is necessary. Shielding
with only M3 is not enough efficient. Metal 5 appears to be the
best solution. USTC, April 11, 2013Patrick Pangaud -
CPPM-IN2P3-CNRS42 Slide 43 3D Test results : FE-TC4-AEDS chip
Shielding studies with Digital Simple Studying the intra-pixel
sensitivity Each drum is separately activated. The noise is
measured on column 7 (without any shield) (noise of 116e- with all
drum OFF). The most sensitive parts are those directly connected to
the input (bump area, injection capacitor) : Not a big surprise but
it confirms that the others parts are not sensitive to the digital
tier. 119 e- 400 e- 200 e- 119 e- 500 e- 350 e- 120 e- 121 e- 124
e- 119 e- 120 e- USTC, April 11, 2013Patrick Pangaud -
CPPM-IN2P3-CNRS43 Slide 44 3D Test results : FE-TC4-AEDC chip
Digital Complex chip offers a complex read-out "A la FE-I4 (with 4
pixel regions). The FE-TC4-AEDC is fully tested by Bonn University
: Threshold~2400e- Noise~94e- The tuned threshold can reach a
dispersion of 50e-. The AE tier and DC tier communicates wells. The
analogue performances are as expected. The readout with TOT
information has been tested and works as expected. USTC, April 11,
2013Patrick Pangaud - CPPM-IN2P3-CNRS44 Slide 45 3D Test results :
FE-TC4-AEDC chip Study of crosstalk between pixel Test procedure:
Inject charge to two pixels and read out only the pixel in between.
Cover the matrix with a 16 Step mask. Configuration : Tuned
threshold around ~ 2800 electrons (for the pixel in the middle) The
injection is increased until reach the crosstalk threshold for
which the middle pixel is affected. Crosstalk threshold = Normal
Threshold / Threshold Measured with crosstalk mask 16 Step Mask
First step Inject Read USTC, April 11, 2013Patrick Pangaud -
CPPM-IN2P3-CNRS45 Slide 46 3D Test results : FE-TC4-AEDC chip Study
of crosstalk between pixel Threshold ~31680 e- Threshold ~31810 e-
Crosstalk threshold ~ 4,42% Crosstalk threshold ~ 4,40% Read analog
tier Read digital tier The crosstalk threshold is the same if the
readout is done via the analog shift register or the digital shift
register : The main crosstalk path is on the analog tier only. No
addition of crosstalk through the digital tier is observed. USTC,
April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS46 Slide 47 3D
Project : test structures From the first 3D prototype made for the
ATLAS Project, some test were done to measure TSV and
Bond-Interface performance. The TSV (Through Silicon Via) consists
of a vertical conductor, often referred to as nail or plug,
entirely crossing the Si substrate of the stacked dies. Measure the
TSV daisy chain(51520 tsv), to understand its electrical
properties. USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS47
Slide 48 FE-TC4-P1 TSV and BI test We measured 19 chips, which show
good tsv daisy chain interconnection. Yielding ~84%. Single tsv
resistance is. Agree with reference value FEC4-P3 test results
under radiation Third 2D chip in Chartered 130nm ( submitted in
2011) : Smaller pixel size (50m x 166m => 50m x 125m) Design of
new sub-parts : analogue buffer, analogue multiplexor . Radiation
Hardness improvement (optimized latches, substrate separation,
guard-ring) Tests under radiation at CERN/PS : The test was made up
to 650 MRads. The chip resists well : up to 300 MRads for the
Analog Part and up to the end of the campaign for the Digital Part.
The chip is not broken after irradiation, and works. The Analog
Part shows a good annealing recovering after 6 months (after
irradiation: 78% of dead pixels, after 6 months of annealing: 18%
of dead pixels). The new small analog pixel is now completely ready
for a next 3D integration. USTC, April 11, 2013Patrick Pangaud -
CPPM-IN2P3-CNRS50 Slide 51 FEC4-P3 : Analog behavior before protons
beam USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS51 At 0
Mrad Sigma Threshold = 674 e- Mean Noise = 339 e- The nominal noise
is 100e-, but we ever detected some excess noise by using the
USBPix card (200e-) Slide 52 FEC4-P3 : Analog behavior under
protons beam USTC, April 11, 2013Patrick Pangaud -
CPPM-IN2P3-CNRS52 At 594Mrads Sigma Threshold = ????? Mean Noise =
????? 3/05/2012 10/05/2012 17/05/2012 24/05/2012 Beam Fluence Slide
53 FEC4-P3 : Analog behavior after 203 days annealing USTC, April
11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS53 Slide 54 The FE-TC4
ATLAS full-scale chip USTC, April 11, 2013Patrick Pangaud -
CPPM-IN2P3-CNRS54 FE-TC4, run 3-D Very large matrix size : 336 x
160 pixels Chip size of 18.8 x 20.1 mm. 1.95 mm End Of Column
width. Small pixel size : 125m x 50m Bump bond pads compatible with
250 m sensor pitch (FE-I4 project) The FE-TC4 re-uses main blocks
of FE- I4 to be compatible for sensors, bump bonding, module/stave
integration, testing tools, software, mechanics 160 18 FE-I3 FE- TC
4 160 Slide 55 Conclusions and prospects The Global Foundry 130nm
is a good candidat with good electrical performance under protons
radiation Despite the (very) poor yield the Tezzaron-Chartered
technology is finally working and gives very good results.
Substantial efforts have to be made by vendors to improve yield and
delivery schedule. Next step : Hybridization of a sensor in such a
3D wafer If the sensor hybridization on a 10m thinned tier works,
this 3D process will be a success. In parallel, we work with
HV-CMOS technology which can allow to perform 3D stacking without
the sensor hybridization step (reduce of cost, time and
complexity). We are working firstly with the Chartered HV
technology (BCDlite) in view of a Chartered-Tezzaron 3D processing
(2D MPW run in May 2012). But if this technology would appear to be
not suitable, we could try to use Tezzaron process with another HV
technology (as allowed in 3D process). Sensor layout : Anna
Macchiolo, Max- Planck-Institut fr Physik, Munich USTC, April 11,
2013Patrick Pangaud - CPPM-IN2P3-CNRS55 Slide 56 HVCMOS DEVELOPMENT
USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS56 HYBRID
PIXELS SENSOR FOR HIGH ENERGY PHYSICS Slide 57 SMART Diode in CMOS
technology 57 The CMOS signal processing electronics are placed
inside the deep-n-well. PMOS are placed directly inside n-well,
NMOS transistors are situated in their p-wells that are embedded in
the n-well as well. Ivan Peric, FEE2011, Bergamo, Italy USTC, April
11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS Slide 58 USTC, April 11,
2013Patrick Pangaud - CPPM-IN2P3-CNRS58 Slide 59 USTC, April 11,
2013Patrick Pangaud - CPPM-IN2P3-CNRS59 Slide 60 A new 3D approach
for HEP community M6 TSV Bond Interface Tier 2 Smart Sensor Tier 1
(thinned wafer) Back Side Metal M5 M4 M3 M2 M1 M2 M3 M4 M5 M4 M3 M2
M1 M2 M3 M4 M5 particle Global Foundries BCDLite technology 0,13m
Electrical field TSV technologies (Via last or middle or first)
GlobalFoundries 0,13m BCDLite technology The BCDLite include the
Low power option plus the High Voltage option. Bond Interface :
regular Redistribution Layer made with last thick Cu Top Metal (1m)
6 metal levels Large reticle (26 x 30 mm) Upper tier thinned down
The HV-CMOS technology allows to perform 3D stacking without the
sensor hybridization step (reduce of cost, time and complexity).
Because the Tezzaron-Chartered technology is a good rad- hard
candidate, we will use the enhanced GlobalFoudry BCDLite technology
to design a new chip in spring 2013 Can we mix the smart diode and
the 3D Integrated technology? USTC, April 11, 2013Patrick Pangaud -
CPPM-IN2P3-CNRS60 Slide 61 IBM 130nm: Possible well-substrate
configuration 61 Nwell Pwell Deep Nwell P- (1-2 Ohm-cm) NwellPwell
T3 Burried n P- (1-2 Ohm-cm) P- Nwell Pwell P- (1-2 Ohm-cm)
Conventional T3: True isolation. NMOS and PMOS on top of sensor.
Substrate can be biased. Proposed prototype to study such a sensor!
Deep Nwell: more flexible - sub can be biased VSUB 0 to -10V USTC,
April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS Slide 62 Conclusion
Time to R&D, between LHC phases Several approach for the same
goal : Compactness information on less mass material. Using the 3-D
electronic integration approach Using very deep submicronic
technology (65nm technology) Using the HVCMOS . Or all in one We
need to create, design and test to qualify these new approaches New
technologies (deeper submicronic, 3D ways, Smart pixels) New
industrial, academic partners, new alliances Novel architecture
(analog detection and digital post-processing) Radiation hardness (
protons beam, Gamma ray, etc) Robustness by test We would like to
thank the fruitful collaboration with Wei Wei, Lei Zhao, Luo
Jianping, Wang Zheng Na Wang, Jiang Xiaoshan, Fu Wei, Jian Lu USTC,
April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS62
