CURRENT STEERING D/A CONVERTERW-2W DAC & Programming Resistive Memory

Shantanu Gupta

ECE 614 Advanced Analog IC Design

Overview

Current Steering DAC

W-2W Topology

Design and Layout Considerations

Glitch ( parasitic capacitances and input delay)

Improving the output impedance of current source

Mismatch consideration in current source

Simulations

INL / DNL

Programming Resistive Memory

Conclusion

Current Steering DACs

unit element- generic current-steering DAC

MOS switch

Binary weighted current-steering DACBinary weighted current-mirror

W-2W Topology

Binary weighted current steering DACrequires N element for N-bit DACrather 2N – 1 element

Biggest problem with binary weighted

current mirror – MISMATCH

W-2W solves the problem

for MISMATCH

4-Bit W-2W NMOS Binary Weighted

DAC w/ Differential output

current not tapped in the

last NMOS device

Diode connected NMOS- dummy

switch better matching

Analyzing W-2W Topology

same size MOSFETs in parallel with G – D – S connected

equivalent to twice the width ( W/L // W/L ≡ 2W/L )

same size MOSFETs in series with G-D-S connected

equivalent to twice the length ( W/L // W/L ≡ W/2L )

Design Considerations

Analog ≡ Custom Design

glitch

glitch-

parasitic capacitance associated with MOS switch and current source cell

variation at node Vn

minimize switch size, use of cascoded current source, RC filtering output

bibi

Cparasitic

Vn

Design Considerations cntd..

switch sizes reduced to 30/2 from 100/2 improved glitch - fig.1

RC filtering at output helps in minimizing it further- fig.2

also S/H circuit can be used to minimize glitch at output (depends of type of application; not shown here)

Fig 1. minimizing glitch through sizing MOS switches Fig2. minimizing glitches further through RC filtering

bibi30

2

Design Considerations cntd..

cascoded current source

increases output impedance of current source

reduces the effect of parasitic capacitance between current source and switches

improve glitch at the output – fig.3

at the cost of increased layout area

Fig3. minimizing glitches and increasing output impedance through cascoded current source

W/L ratio for current source and cascode MOS same but actual size or WxL different

Design Considerations cntd..

Mismatch in the current source

due to threshold voltage ( threshold voltage)

due to size (Wand L)

current source variation important concern for INL and DNL

( )2

2D GS THNI V Vβ= −

where'

n ox

WC

Lβ µ= ×

D DD THN

THN

I II V

Vβ

β∂ ∂∆ = ∆ + ∆∂ ∂

THND D D

D D THN D

VI I I

I I V I

ββ

∆∆ ∂ ∂∆= +∂ ∂

Design Considerations cntd..

( )( )

( )( )

2

2 2

121 1

2 2

GS THN GS THN THND

D GS THN GS THN

V V V V VI

I V V V V

β ββ β

− ∆ − − ∆∆ = +− −

( )2 TH ND

D G S T H N

VI

I V V

ββ

∆∆ ∆= −−

( )

22 2

22 2

4THND VI

D GS THNI V V

β σσ σβ

∆ = +−

THN

THN

VV

A

W Lσ =

× and A

W Lβ

βσ =×

thus for good matching of current source relatively large area MOSFETs should be used for current cell

** Equations adapted from [3] and [4]

Layout

1 m

m

12 Bit DAC Layout

6 Bit DAC Layout

W-2W compact layout area

INL / DNL

INL and DNL specification

assuming MSB max positive mismatch and rest of bits max negative

sum of mismatch equals = 0

1( )

2ith REFN iI bi I−= where bi = 0 or 1 1LSB = IREF/ 2N

|INL| max = Actual MSB – Ideal MSB ; if ∆Ik current mismatch

= (IREF+ ∆Ik ) / 2 – ( IREF / 2 )

INL / DNL

|INL| max = ∆Ik / 2 ; If INL ≤ 0.5 LSB then ; 1

2 2 2k REF

N

I I∆ = ×

max, 2REF

k NINL

II I∆ = ∆ =

worst case DNL in binary weighted – mid code ; code changes 01111----1 to 1000---0 ; intuitively at mid code Input changes by more than 1 LSB

( ) ( )2

max ( 1)0

1 1

2 2 2

NREF

REF k REF kN N N i Ni

IDNL I I I I

−

− − −=

= +∆ × − +∆ −∑

max

11

2k NDNL I = ∆ −

If DNL ≤ 0.5 LSB then 1 1

12 2 2

REFk N N

II ∆ − = ×

1max, 2 2REF

k NDNL

II I +∆ = ∆ =

−

DNL specification more stringent then INL for high resolution

Programming Resistive Memory

** figure 4 taken from [5]

Fig 4 scheme depicting programming of resistive memory through current steering DAC [4]

Programming - Joule effect

Digitally controlled current pulses

stepping up current digitally, eases

Implementation of multilevel programming

Conclusion

DACs architecture based on application

w/ high conversion rates used in high frequency application

programming of resistive memory circuit

w/ W-2W implementation achieve compact

layout

high power consumption

Limited DNL (not very high resolution achievable)

DNL specification can be eased, higher resolution through segmentation

Fig 5 various flavors of DAC based on application [6]

References:-

[1] CMOS Circuit Design Layout and Simulation (revised second edition) , R. Jacob Baker, IEEE Press

[2] CMOS Mixed Signal Circuit Design, R. Jacob Baker, IEEE Press

[3] http://www.ee.iitm.ac.in/~nagendra/videolectures/doku.php?id=ee658_2008:start

[4] Transistor matching in analog CMOS application; Marcel J. M. Pelgrom et. al.

[5] A Multi- Level – Cell Bipolar Selected Phase Change Memory, Ferdinando Bedeschiet. al. , 2008 IEEE International Solid State Circuits Conference

[6] www.ti.com

Questions and Discussion

Crystal Oscillators in CMOS

ECE614 Project 2

Bob Hay

1

Topics Covered

• The crystal model

• Creating an oscillator from a resonator

• The concept of loaded Q

• Parallel resonance operation

• Topologies

• CMOS implementation

• Other design considerations

2

The Quartz Crystal

3

Motional Elements

Resonator Equations

• For a Series Resonant Circuit,

• For Parallel Resonant Circuit,

4

S

S

S C

L

RQ

1=

PS

PSEQ

CC

CCC

+•

=

SS

SCL

1=ω

EQ

S

S C

L

RQ

1=

EQS

PCL

1=ω

•

•

•

•

•

•

Parameters of a High Quality Crystal

• Example:

• Bliley SC-Cut Model BG61SCH-3S

5

aFQR

CSS

S 049.2041

==ω H

CL

SS

S 24143.112

==ω

Ω= 65SR pFCO 3≈

6102.1 ∗=QMHzf 000.100 =

Derived from data at http://www.bliley.com/index_088.htm

The Crystal Equivalent Circuit

6

Turning a Resonator into an Oscillator

The Open Loop Response

7

Crystal Resonator

θ

Output

Fine

Tune

AC

Vout

Vin

Vin

VoutG = VinVout ∠−∠=φ Barkhausen Criteria for oscillation

G>1; πφ N2=

Turning a Resonator into an Oscillator

Closing the Loop

8

If there is a frequency f0 at which the Barkhausen Criteria are

met, then the system will oscillate at that frequency. This is a

case where positive feedback is a good thing. If there is more

than one frequency at which the criteria are met, beware!

Simulating Series Resonance with Ideal

Behavioral Gain Stages (not practical)

9

Loaded Q with Ideal Circuit

10

DelayGroup

d

dQL

∗=

=

2

2

0

0

0

ω

ωφω

67 102.1038.10 ∗≈∗∗= πLQ

Group Delay = 38 ms

Ref [4]

Create a Crystal Component

11

Loaded Q with Ideal and Real Loads

12

Implementation of Series Resonant

Oscillator – The Butler Oscillator

13

The Butler Oscillator can be useful at

high frequencies but requires an

inductor to achieve the feedback gain.

This works well with overtone

oscillators where a tank circuit is

needed.

High Q→low RE or low RS → high device bias current.

==

Dm

SIg

Rβ2

11

=

C

EI

mVR

25

Operation in Series Resonance –

Some Observations

14

Barkhausen

Criteria

High QL

Implies low input/output R

and noninverting gain.

Often difficult to achieve at high frequencies,

since small bipolar and MOS devices tend to

invert and have high input/output R. L/C

matching transformer may be required.

Consider a topology

better matched to

real devices.

Another operating mode –

Parallel Resonance

15

The crystal is

inductive; the added C

creates a parallel

resonance so at fR

( ) ( ) ( )1VILICI >>≈

Here we have the same circuit.

Notice that I1 will be 180° out of

phase with I2 in the direction

shown.

CrystalCrystal

Parallel Resonance Topology

16

Crystal Parallel Resonant Circuit

Loaded Q with Ideal Components

17

The 38ms group delay is

maintained and thus so is

the QL=1.2*106. Note that

the phase shift is now

180° at resonance. Also

note that achieving this

QL

requires infinite

resistance input and

output components.

Generic Bipolar Anti-resonant

Crystal Oscillator

18

Most parallel resonant (anti-resonant) mode oscillators with

a single stage active circuit are a variation of this design.

Since the gain stage provides phase inversion, the crystal

must be operating in the parallel resonant mode.

Ref [3]

Three Configurations

19

Output signals may be derived as

shown or frequently from a node

based on a divider of the existing

capacitor to ground.

How nice it must have been to be able to

simply take an existing oscillator design,

move the ground, and attach your name to

the design!

Most CMOS oscillators are

Pierce oscillators due to the

grounded source configuration

CMOS Implementation

20

Build a gain block – 3 stages for high gain and

to minimize crossover current. Stage width

multiplier = 3X

CMOS/Crystal Oscillator-Open Loop

21

This is for most applications a poor design. The Q is high but

the resonator power will be very low → Low SNR in inverter.

Oscillator Transient Analysis

22

Rate of signal increase is constrained by

bandwidth(and Q)

Gain compression in amplifier provides

nonlinear gain control

• Average loop gain = 1 at equilibrium.

• Harmonic distortion in resonator will

increase with larger loop gain.

Other Performance Metrics

23

VDD current over a cycle 255µA @ 1V = 255µW

Crystal power over a cycle 12.4nW average power

Too low for most applications.

Other Design Considerations

• Temperature characteristics and

compensation

• Phase noise and jitter

• Overtones and spurious oscillations

• Long-term stability (drift)

24

Concept of Cut and General

Temperature Characteristics

25

http://www.icmfg.com/glossary.html

AT Cut Crystal

Temperature Characteristics of AT Cut

Crystal

26

http://www.citizen.co.jp/english/crystal/aspect/index.html

SC Cut characteristics for Ovenized

Crystals

27http://www.bliley.com/index_080.htm

Temperature Compensation

• Compensator typically uses Varactor diode as capacitor in fine tuning phase shifter or as part of the shunt capacitor network.

• Varactor bias can be supplied by network of thermistors or derived with digital logic/DAC from a single temperature sensor.

• Varactor diodes are typically poor (low Q) capacitors so increasing compensation range results in higher oscillator noise.

• The best quality oscillators use ovens to minimize required compensation range (SC cut crystals).

28

Phase Noise and Jitter

29Ref [2]

Leeson’s Oscillator Noise ModelPhase noise vs. offset

1 E -1 2

1 E -1 1

1 E -1 0

1 E -0 9

1 E -0 8

1 E -0 7

1 E -0 6

1 E -0 5

0 .0 0 0 1

0 .0 0 1

0 .0 1

0 .1

1

1 1 0 1 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0

Log(Offset from carrier)

dB relative to carrier

( )ωφS

3

2

0

2

−

m

Qαω

ω

2

2

0 2

2

−

m

SP

FkT

Qω

ωSP

FkT2

Q2

0ω

Zone 1

Zone 2

Zone 3

Q plays a dominant role in determining noise, both close in (drift)

and far out (jitter). Ref. [7]

( )mω

Effect of phase noise on a QAM

Constellation

-1.5 -1 -0.5 0 0.5 1 1.5-1.5

-1

-0.5

0

0.5

1

1.5Initial Constellation EVM = 2.2327e-016

Real

Imagin

ary

-1.5 -1 -0.5 0 0.5 1 1.5-1.5

-1

-0.5

0

0.5

1

1.5Received Constellation EVM = 0.023092

Real

Imagin

ary

Constellation prior to frequency conversionConstellation after frequency conversion with minor phase

noise.

Overtones and Spurious Responses

32

http://www.ecliptek.com/tech/spurmodes.html

Overtone Model

33

Causes of Frequency Drift

• High crystal power

– Vibration slowly relieves stresses in quartz

• Low QL

– Low dφ/dω →high dω/dφ

• Contamination accumulation on quartz

– Metal package outgasses contaminants

– Use hermetic glass /vacuum package

34

Metal Case Crystal

35

http://www.bliley.com/index_098.htm

Glass Vacuum Packaged Crystal

36http://www.bliley.com/index_088.htm

Typical RS vs. Frequency

37

Typical

maximum

crystal

resistance RS

as a function of

frequency.

Ref [1]

A Few Items to Consider• Frequency accuracy

– Use oven (best) or temperature compensation

• Long term stability – drift– Maximize Q, reduce crystal power, avoid oven

• Short term stability – jitter and noise– Maximize Q, increase crystal power, use oven

• Power consumption– Avoid oven, reduce crystal drive, match Rs (reduces

Q)

• Overtone and frequency selection– Avoid spurious oscillations (adds cost)

• Nothing to it – it’s just a crystal oscillator38

How easy is this stuff?

39

Current Openings:

ENGINEERING JOBS & TECHNICAL OPENINGS

Senior OCXO / TCXO Design Engineer

Bliley Technologies is seeking a talented, creative individual with

extensive design experience with high performance OCXO and TCXO

oscillators. The successful candidate will work closely with our design

and production teams to develop new products and efficient designs for

our customers in the telecommunications, satellite and defense

industries. The ideal individual should have a degree in Electrical

Engineering with ten years of proven experience in the field. An

extensive knowledge of quartz crystals is a must. The desire to

explore and apply leading-edge techniques and the ability to work

in a fast-paced environment are trademarks of this versatile

engineer. If you have what it takes, we want to hear from you. For

directions to our facility, please view our contact us page.

http://www.bliley.com/engineering_jobs.htm

References

1. Philips Semiconductors Application Note AN1983, “Crystal oscillators and frequency

multipliers using the NE602 and NE5212”, 1991

2. “Predicting PLL Phase Noise & Jitter with HSPICE RF, “ webcast hosted by EDN and

Synoposys, !/23/2007, no longer available.

3. Frerking, Marvin, “Crystal Oscillator Design and Temperature Compensation,” Van Nostrand

Reinhold, 1978, ISBN: 0-442-22459-1

4. Grebennikov, Andrei, “RF and Microwave Transistor Oscillator Design, “ John Wiley & Sons,

2007

5. Baker, R. Jacob, “CMOS Circuit Design, Layout, and Simulation,” IEEE Press/John Wiley &

Sons, Revised Second Edition, 2008, ISBN 978-0-470-22941-5

6. Haque, M. and Cox, E, “Use of the CMOS Unbuffered Inverter in Oscillator Circuits,” Texas

Instruments Application Report SZZA043 January 2004

7. D. B. Leeson, “A Simple Model of Feedback Oscillator Noise Spectrum,” Proceedings of the

IEEE, February 1966, pp. 329 – 330.

40

Questions

41