Upload
sm-ferdous
View
225
Download
0
Embed Size (px)
Citation preview
8/10/2019 Current Sources BJT
1/15
EEEB273/EEEB314 Electronics II - Analog IC Biasing and Active Loads (Part 1)
Analog Integrated Circuit (IC) biasing and active
loads (Part 1) BJT Current Sources
Preamble Biasing BJT Circuits to Achieve Forard!active
"ode
Single Base #esistor Biasing
$oltage %ivider Biasing and Bias Stabilit&
Advantages Simple
Disadvantages No bias stabilisation,
i.e. -point varies
with
Requires large
resistors (Ms, i.e.
uses large area,
whi!h is an
important issue in "#
design.
Advantages Simple
Disadvantages No bias stabilisation,
i.e. -point varies
with
Requires large
resistors (Ms, i.e.
uses large area,
whi!h is an
important issue in "#
design.
Advantages Simple
Disadvantages No bias stabilisation,
i.e. -point varies
with
Requires large
resistors (Ms, i.e.
uses large area,
whi!h is an
important issue in "#
design
Figure 1' Common!emitter circuit
ith a single bias resistor in the base
8/10/2019 Current Sources BJT
2/15
8/10/2019 Current Sources BJT
3/15
EEEB273/EEEB314 Electronics II - Analog IC Biasing and Active Loads (Part 1)
*+at t,e o. circ#its can e designed to estalis+ ias c#rrent I0
To!Transistor Current Source a0a Current "irror
+asi! building blo!$ in "# !urrent
sour!e design
Q1is diode!connected
Q1and Q2are matched, i.e.
identi!al,
)he re.erence currentis given b0*
Current relationshi,*
o At !olle!tor node o& 1, i.e. at point 3* 22 2 BC)E2 III +=
o )here&ore, output !urrent is
(.2
6BE14 6BE2 6BEIB14IB2IC14IC2
3
)
666I BE)E2
+ =
Figure 3' To!transistor current
source ith re.erence resistorR1
+
==
2(
2
)E2
C0
III
(.
#onne!ted as a
diode7 whensupplies are
!onne!ted, +%-
8un!tion is&orward biased.
8/10/2019 Current Sources BJT
4/15
EEEB273/EEEB314 Electronics II - Analog IC Biasing and Active Loads (Part 1)
o 9en!e, assuming 6CE1(4 6BE :: 6A,
o A more general equation to !al!ulate dI0*
where0is the output resistan!e o& the !urrent sour!e and is
di&&erent &or di&&erent t0pes o& !urrent sour!es.
Eercise 1'2$ E 1'2
"ismatched Transistors
"n most "# &abri!ation o& !urrent sour!es, 1and 2will be dire!tl0 ad8a!ent
to ea!h other. 9en!e, the0 !an be ver0 well mat!hed.
9owever, i. Q1and Q2are mismatchedand ;;, base !urrents !an benegle!ted to give*
22
oA
0
CE
0
r6
I
d6
dI=
(.60CE
0
)d6
dI
2=
8/10/2019 Current Sources BJT
5/15
Figure 5' Basic three!transistor
current source
EEEB273/EEEB314 Electronics II - Analog IC Biasing and Active Loads (Part 1)
Im,roved Current Source Circuits
=ets loo$ at !urrent sour!e !ir!uits that have improved load !urrent stabilit0against*
!hanges in
!hanges in output transistor !olle!tor voltage
i Basic Three!Transistor Current
Source
Assume all transistors identical
(.>
Note* #urrent in 3substantiall0smaller
than in either 1and 2, i.e. 3
: .
)he re.erence currentis given b0*
6BE14 6BE2 6BEIB14IB2IC14IC214 24
3
2 666+
( ) 2666
2( BBE III =+=
1suall0 assume 6BE34
6BE. 9en!e, the term
8/10/2019 Current Sources BJT
6/15
EEEB273/EEEB314 Electronics II - Analog IC Biasing and Active Loads (Part 1)
ut,ut resistance2 ro*
o =oo$ing into the !olle!tor o& the output transistor 2in the three-
transistor !urrent sour!e,rois the same as in the to!transistor
current source*
(.C
"& there eists an0 mismat!h between 1and 2, the bias !urrent deviation&rom the ideal is as given in eq. (..
Ea5le 1'3$ E 1'3
1 Cascode Current Source
Designed su!h thatROis greater than that o. the to!transistor
circuit.
Assum,tion' all the transistors are matched 9en!e,IO IREF.
0
A
CE
0
oI
6
d6
dIr
=
2
E
=
E
=
8/10/2019 Current Sources BJT
7/15
EEEB273/EEEB314 Electronics II - Analog IC Biasing and Active Loads (Part 1)
Figure 9' Small!signal e-uivalent circuit o. the cascode current mirror rearranged
rom igure C, summing !urrents at the output node 0ields*
++=
o
/e4
/e54r
666gI
and sin!e ( ).2. rrI6 o4/e = , the out,ut resistanceis given b0*
(.F
9en!e, the out,ut resistance has increased b& a .actor o. !ompared to
the two-transistor !urrent sour!e.
( ) oo
4
40 rrr
I
6) ++==
8/10/2019 Current Sources BJT
8/15
Figure ;' Basic three!transistor
current source
EEEB273/EEEB314 Electronics II - Analog IC Biasing and Active Loads (Part 1)
#urrent levels in all three transistors are nearl0 the same, there&ore
142434
At point 3*
(.H
Nodal equation at emitter o& 3, i.e. point G*
(.
1sing the !urrent relationships o& a transistor, eq. (. be!omes*
(.2
)here&ore, b0 substituting (.2 into (.H, the out,ut currentis*
(.6
626 BCBC)E2 IIIII +=+=
+=+=
22 2226 CBCE IIII
( ) 66
22
2 C
E
C II
I
++
=+
=
( )
+
+==
2
2
6 )E2C0 III
)his !urrent relationship is essentiall0 the same as o& the previous three-transistor
!urrent sour!e (given b0 eq. .@. The di..erence is in the higher out,ut
8/10/2019 Current Sources BJT
9/15
EEEB273/EEEB314 Electronics II - Analog IC Biasing and Active Loads (Part 1)
or the two-transistor !urrent sour!e (igure >, i& a load !urrent o&I04
HA is required, &or 694 >/ and 6-4 >/, the resistan!e value needed is*
( )$IF6H
H
>@.H> =
=
+
)E2
BE
I
666)
Resistors in the order o& Mrequire large area and are di&&i!ult to &abri!ate
a!!uratel0 &or "# appli!ation. 9en!e, the resistor values are limited to the
lo 0ilohm range.
)he 5idlar !urrent sour!e, shown below, meets the above requirement.
/oltage di&&eren!e a!rossEenables
6BE2: 6BE1
9en!e,I0:IE.
Q1and Q2are identicaland:;;
&or both transistors.
9en!e, &BE 668C)E2 eIII I
8/10/2019 Current Sources BJT
10/15
EEEB273/EEEB314 Electronics II - Analog IC Biasing and Active Loads (Part 1)
(.@
Design Ea5le 1'4$ E 1'4
Design Ea5le 1';$ E 1';
)he output resistan!e loo$ing into the !olle!tor o& 2is given b0*
whi!h !an be determined b0 using the small-signal equivalent !ir!uit in
igure (a.
)he output resistan!e loo$ing into the base o& 1is given b0
2((
(
((
(
r)r
gr) o
5
0
8/10/2019 Current Sources BJT
11/15
EEEB273/EEEB314 Electronics II - Analog IC Biasing and Active Loads (Part 1)
Figure 11' (a) Small!signal e-uivalent circuit .or determining out,ut resistance o.
:idlar current source2 (b) sim,li.ied e-uivalent circuit .or determining out,ut
resistance2 and (c) e-uivalent circuit a.ter a *orton trans.ormation
)here&ore, output resistan!e at the !olle!tor o& 2!an be determined &rom
igure (b or (! to give*
(.C
Normall0, ( ) 22 5o gr
8/10/2019 Current Sources BJT
12/15
EEEB273/EEEB314 Electronics II - Analog IC Biasing and Active Loads (Part 1)
)he relationship between ea!h load !urrent and the re&eren!e !urrent,
assuming all transistors are mat!hed and 6A4 K, is*
(.2H
)he !olle!tor o& multiple output transistors !an be !onne!ted together,
!hanging the load !urrent versus !urrent relationship. An eample o& su!h a!ir!uit is shown in igure 6.
Figure 1+' "ultiout,ut
transistor current source
(assuming all transistors are
matched andis ver& large such
that the base currents can be
neglected2I1=I2=I3=IREF)
>enerali4ed Current "irror
4 6IE
( )
%
IIII )E2%00 ++
====(
(
2(
%quivalent !ir!uit s0mbol
o& three transistors in
parallel
8/10/2019 Current Sources BJT
13/15
EEEB273/EEEB314 Electronics II - Analog IC Biasing and Active Loads (Part 1)
%&&e!t o& &inite -I0to be less thanIEsin!eIEsupplies all base
!urrents. "t be!omes more severe as more transistors are added.
Design Ea5le 1'7$ E 1'7ut,ut $oltage Sing
The minimum out,ut voltage2 VO(min)2 o. the current mirror in.luences
the ma6imum s&mmetrical out,ut voltage2 VOUT2 sing o. the load
circuit being biased
60
60!&
8/10/2019 Current Sources BJT
14/15
8/10/2019 Current Sources BJT
15/15
EEEB273/EEEB314 Electronics II - Analog IC Biasing and Active Loads (Part 1)
Summar& o. current source circuits
To!
transistor(igure >
Three!
transistor(igure ?
Cascode(igure @a
:ilson(igure F
:idlar(igure H
"ulti,le
transistor(igure 2
?oad current2
IO
+
2(
)E2I
( )
+
+6
(
2(
)E2I
+
.(
)E2I
( )
+
+ 2
2(
)E2I
0
)E2
&
E I
I6
)ln
( )
%
I)E2+
+
ut,ut
resistance2ROro2 ro2 .or
2
6or ( )
222( r)gr E5o + ro
Finiteerror@
22
2
.2
2 -
%
inite:error 4 dis!repan!0 betweenI0andIEsin!e the re&eren!e !urrent supplies all base !urrents.
Oroblem-Solving )e!hnique* +P) #urrent Sour!e #ir!uits
o Sum !urrents at the various nodes in the !ir!uit to &ind the relation between the re&eren!e !urrent and the bias
!urrent.
o )o &ind the output resistan!e, pla!e a test voltage at the output node and anal0se the small-signal equivalent
!ir!uit. Eeep in mind that the re&eren!e !urrent is !onstant, whi!h ma0 ma$e some o& the base voltage
!onstant or at signal ground.
Dr !ng"# Anisa$ !%I&E%$ 2''7 >