CSE398: Network Systems Design - Lehigh University

CSE398:Network Systems Design

Instructor: Dr. Liang ChengDepartment of Computer Science and Engineering

P.C. Rossin College of Engineering & Applied ScienceLehigh University

March 28, 2005

Instructor: Dr. Liang Cheng CSE398: Network Systems Design 03/28/05

Outline

RecapNetwork processor architectures

Issues in scaling a network processorSummary and homework


RecapNetwork processor architecture is characterized by

Processor hierarchyMemory hierarchyInternal busesExternal interfacesSpecial-purpose functional unitsSupport for concurrent or parallel executionProgramming modelDispatch mechanisms


Design QuestionsCan we make network processors

Faster?More powerful?Cheaper?More general?Easier to use?All of the above?

Scalable design is fundamental


Scaling the Processor Hierarchy

General purpose CPUHighest level functionalityAdministrative interfaceSystem controlOverall management functionsRouting protocols

Embedded processorIntermediate functionalityHigher-layer protocolsControl of I/O processorsException and error handlingHigh-level ingress (e.g., reassembly)High-level egress (e.g., traffic shaping)

I/O processorBasic packet processingClassificationForwardingLow-level ingress operationsLow-level egress operations


Packet Flow through HierarchyTo maximize performance, packet processing tasks should be assigned to the lowest level processor capable of performing the task.


The Pyramid of Processor Scale

Lower levels need the most increase


Scaling the Processor Hierarchy

Make processors fasterUse more concurrent threadsIncrease numbers of processorsIncrease processor types


Scaling the Memory Hierarchy

SizeSpeedThroughputCost


Memory SpeedAccess latency

Raw read/write access speedSRAM 2 - 10 ns: flip-flop, 4-6 transistorsDRAM 50 - 70 ns: capacitor under 1 transistorExternal memory takes order of magnitude longer than onboard

Memory cycle timeMeasure of successive read/write operationsImportant for networking because packets are largeRead Cycle time (tRC) is time for successive fetch operationsWrite Cycle time (tWC) is time for successive store operations


The Pyramid of Memory ScaleLargest memory is least expensive


Memory Bandwidth

General measure of throughputMore parallelism in access path yields more throughputCannot scale arbitrarily

Pinout limitsProcessor must have addresses as wide as bus


Types of Memory


Memory Cache

General-purpose technique better thanExternal memory

Memory controllerMagnitude longer to access than on-chip memory

May not work well in network systemsLow temporal localityLarge cache size (either more entries or larger granularity of access)


Content Addressable Memory (CAM)

Combination of mechanismsRandom access storageExact-match pattern search

Rapid search enabled with parallel hardware


Arrangement of CAMOrganized as array of slots


Lookup in Conventional CAMGiven

Pattern for which to searchKnown as key

CAM returnsFirst slot that matches key, orAll slots that match key

Algorithmfor each slot do {

if ( key == slot ) {declare key matches slot;

} else {declare key does not match slot;

}}


Ternary CAM (T-CAM)Allows masking of entriesGood for network processorOne, zero, don’t care


T-CAM LookupEach slot has bit maskHardware uses mask to decide which bits to testAlgorithmfor each slot do {

if ( ( key & mask ) == ( slot & mask ) ) {declare key matches slot;

} else {declare key does not match slot;

}}


Partial Matching with a T-CAMKey matches slot #1


Using a T-CAM for Classification

Extract values from fields in headersForm values in contiguous stringUse a key for T-CAM lookupStore classification in slot


Classification using a T-CAM


Outline

RecapNetwork processor architecturesSummary and homework


SummaryScalability key issuePrimary subsystems affecting scale

Processor hierarchyMemory hierarchy

Many memory types availableSRAMSDRAMCAM

T-CAM useful for classification


Homework (due on 04/05)10.1. (a) Problem 8 of Chapter 13 (Page 200); (b) Problem 1 of Chapter 14 (Page 218).10.2 Find out what are SDRM, QDR-SRAM, ZBT-SRAM, FCRAM, DDR-DRAM, RLDRAM.

Documents

CSE398: Network Systems Design - Lehigh University