CPF_tutorial_2007_12_06

8/19/2019 CPF_tutorial_2007_12_06

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Innovation Through Collaboration

Common Power FormatTutorial

December 6, 2007

Qi WangCadence Design Systems, Inc.

LPC Architect, LPC, Si2

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– 2 –Innovation Through Collaboration

– 2 –Innovation Through Collaboration – Low Power Coalition

Outline

●Where Was It Started?

●CPF Basics

●Digest CPF Using A Simple Example

●CPF Based Low Power Design Flow

●Where Is CPF Headed?

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– 3 –Innovation Through Collaboration

– 3 –Innovation Through Collaboration – Low Power Coalition

Low Power Design Without A Power Format

Verification

Formal Analysis

Acceleration& Emulation

Simulation

V e r i f i c a t i o n C o v e r a g e

T e

s t b e n c h A u t o m a t i o n

Design Creation

Synthesis

ConstraintGeneration

Design for Test

SVP

E q ui v al en c e C h e c k

i n g

C on s t r ai n t V al i d a t i on

SpecificationFunction, timing, power

RTL

Coding

IterateIterate

Physical Implementation

Chip IntegrationPrototyping

Physical Synthesis

Routing

DF T

A n al y s i s

Sign-off

A T P G


E q ui v al en c e

c h e c k i n g

L V S / DR

C / E x t

GDSII

Constraints Netlist

How do you verifypower functionality

without changing RTL??

MSVSRPGPSO

DVFS

Command file•Domains

•Level shifters•Isolation•SRPG

Command file•Domains•Level shifters•Isolation•SRPG


Command file•Domains

Command file•Domains•Modes for ATPG


Command file•Domains•Level shifters•Isolation

•SRPG

Which one ofthese is “golden”?

Does the power

shutoff really going towork?

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– 4 –Innovation Through Collaboration – 4 –Innovation Through Collaboration – Low Power Coalition

LibrariesIP

What Was the Problem?

LogicInformation(Verilog)

Synthesis

Test

SVP

Formal Analysis

Simulation

Parser Parser

Parser

Logic is “ Connected”

P+R

Parser

P a r s e r

P ar s e

r

Can be Automated

Hardware

Parser

EquivalenceChecking

Parser

Management

Parser

Power Information(CPF)

Power is Not “ Connected”

Very Difficult to Automate

Power Information(no consistency)

LibrariesIP

Synthesis

Test

SVP

Formal Analysis

Simulation

Parser Parser

Parser

P+R

Parser

P a r s e r

P ar s er

Hardware

Parser

EquivalenceChecking

Parser

Management

Parser

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Common Power Format (CPF)Single file format to automate low power holistically

Power is “ Connected”

Is Automated

LibrariesIP

Synthesis

Test

SVP

Formal Analysis

Simulation

Parser Parser

Parser

P+R

Parser

P a r s e r

P ar s er

Hardware

Parser

EquivalenceChecking

Parser

Management

Parser

Power Information(CPF)

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Rallying Industry Support

CPF

D e s i g

n

V e r i f i

c a t i o

n

Implementation

Libs

Semi

System

MfgEquip

EDA

IP

A new method ofcapturing design

and constraintinformation

Enables automation and

what-if exploration

Facilitates holisticmethodology acrossdesign, verification,and implementation

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300300ManMan

YearsYears

Common Power Format Progress

2005

CPFCPFV 0.0V 0.0

Q22006

CPFCPFV 0.5V 0.5

~ 100 Inputs~ 100 Inputs

Q32006

CPFCPFV 0.8V 0.8

> 400 Inputs> 400 Inputs

Q42006

CPFCPFV 1.0V 1.0

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● Dec 4, 2006

Cadence contributed CPF v1.0 to Si2

● January 12, 2007

LPC members unanimously voted andapproved CPF v1.0 as Si2 Specif ication forlow power standard

● January 17, 2007

Cadence contributed CPF v1.0 parser sourcecode to Si2

● March 5, 2007

CPF 1.0 available to everyone at no cost as a

Si2 standard

Si2 CPF Standardization

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Outline


●CPF Basics




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Common Power File ASCII file to capture

● Design intent and constraints

Power domain

Logical: instances as domain members

Physical: power/ground nets and connectivity Analysis view: timing library sets for power domains

Power Logic

Level Shifter Logic

Isolation Logic

State-Retention logic

Switch Logic & Control Signals

Power mode

Mode definitions

Mode transition definitions

● Technology information

Level Shifter Cells, Isolation Cells, State-Retention Cells, Switch Cells, Always On Cells

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CPF Language

● CPF is TCL-based.

● CPF Language = TCL commands + CPF objects + Design objects

Power domain

Analysis view Delay corner

Library set

Operating condition

● Design objects: objects that already exist in the RTL/gate netlist Module, Instance, Net, Pin, Port

● Commands – 42 commands

set_* commands [version, scope, and general commands]

define_*_cell commands [library cell description]

create_*_rule commands [design intent]

update_*_rules commands [implementation directives]

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Minimal Command Set For Different Design Stages

create_power_domain

create_nominal_condition

create_power_mode

create_state_retention_rulecreate_isolation_rule

create_level_shifter_rule

define_library_set

update_nominal_condition

update_power_mode

create_ground_nets

create_power_netsupdate_power_domain

create_power_switch_rule

create_analysis_view

create_operating_corner

Specify power intentsverification and simulationdesign explorationearly power estimation

More implementation detailssynthesis

formal verificationDFT, ATPG,gate level power estimation

Complete physical implementationdetailssilicon virtual prototypingpower planningphysical synthesisstructural verificationsign-off power analysis

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Outline


●CPF Basics




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Nano CPU

● 32 bit RISC processor

5 power domains with 4 independent switchable domains

2 supply voltages: simple DVFS

ALU

Arithmetic Unit

Logical Unit

Registerfile

Program Counter

Data-out register

I/Ocontroller Power

ControlUnit

State

Sequencer

Address register

Instruction register

Data-in register

Data Bus

PowerControl Bus

CPU Control Bus

Address BusAlways ON power

domain

Switched power domains

Data OUT

Data IN

Address

Clock

Control

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Set Up Power Domains

create_power_domain -name PDcore -default

create_power_domain -name PDau -instances alu_inst/aui \

-shutoff_condition pcu_inst/pau[2]

create_power_domain -name PDlu -instances alu_inst/lui \

-shutoff_condition pcu_inst/plu[2]create_power_domain -name PDalu -instances alu_inst \

-shutoff_condition pcu_inst/palu[2]

create_power_domain -name PDrf -instances rf_inst \

-shutoff_condition pcu_inst/prf[2]

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Complete create_power_domain Command

create_power_domain

-name power_domain

{ -default [-instances instance_list] [-boundary_ports pin_list]

| -instances instance_list [-boundary_ports pin_list]

| -boundary_ports pin_list }

[ -shutoff_condition expression ]

[ -default_restore_edge expression ] [ -default_save_edge expression ][ -power_up_states {high|low|random} ]

● Power domain definition

● Pure abstract model of a power domain at RTL● Power domain inheritance and precedence

● Default power domain concept

● Wildcard characters are allowed for design objects

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Specify Power Logic: Retention Strategy

create_state_retention_rule –name sr_rule –domain PDrf \

-restore_edge { !pcu_inst/prf[1] }

Single control for state retention

pcr_inst/prf[1] going high starts the retention mode pcr_inst/prf[1] going low ends the retention mode with

saved data restored to the flop output

All registers and only registers in power domain PDrf aremodeled as retention registers

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Specify Power Logic: Isolation Strategy

create_isolation_rule -name iso_rule1 -from PDau \

-isolation_condition {!pcu_inst/pau[0]} -isolation_output lowcreate_isolation_rule -name iso_rule2 -from PDlu \

-isolation_condition {!pcu_inst/plu[0]} -isolation_output high

create_isolation_rule -name iso_rule3 -from PDalu \

-isolation_condition {!pcu_inst/palu[0]} -isolation_output low

create_isolation_rule -name iso_rule4 -from PDrf \

-isolation_condition {!pcu_inst/prf[0]} -isolation_output low

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Complete create_isolation_rule Command

create_isolation_rule -name string -isolation_condition expression

{-pins pin_list | -from power_domain_list | -to power_domain_list}...

[-isolation_target {from|to}] [-isolation_output {high|low|hold}]

[-exclude pin_list]

● It specifies a list of signals require isolation when the driving or receiving power domains ofthese signals are switched off

●

-pins/-from/-to/-exclude are filters for selecting the signals● -isolation_condition specifies under what condition the isolation rule is activated

For RTL verification tool, this is the condition when the behavior specified by –isolation_outputshould be imposed to the normal functional behavior

For implementation tool, isolation condition should be synthesized to drive the enable pin of the

special isolation cell● In most cases, isolation is needed when the driver of a signal is switched off but the

receivers of the signal are still on. In some cases, isolation may be required when thedriver signal is on but the receivers of the signal are off.

-isolation_target specifies which power domain is switched off when this rule is activated

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Power Modes

PDcore PDau PDlu PDalu PDrf

PM1 1.2v

0.8v

PM3 0.8v off off off 1.2

PM4 0.8v 1.2v 1.2v 1.2v off

1.2v 1.2v 1.2v

PM2

1.2v

1.2v 1.2v 1.2voff

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Specify Power Modes

create_nominal_condition -name high -voltage 1.20

create_nominal_condition -name low -voltage 0.8create_power_mode -name PM1 –default \

-domain_conditions {PDcore@high PDau@high PDlu@high PDalu@high PDrf@high}

create_power_mode -name PM2 \

-domain_conditions {PDcore@low PDlu@high PDalu@high PDrf@high}


-domain_conditions {PDcore@low PDrf@high}


-domain_conditions {PDcore@low PDau@high PDlu@high PDalu@high }


PM1 1.2v

0.8v

PM3 0.8v off off off 1.2PM4 0.8v 1.2v 1.2v 1.2v off

1.2v 1.2v 1.2v

PM2

1.2v

1.2v 1.2v 1.2voff

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Complete create_power_mode Command

create_nominal_condition –name string –voltage float

create_power_mode -name string [-default]

-domain_conditions domain_condition_list

● The create_power_mode commands specify a list of valid operating modes for a design

● Each mode include the operating conditions for each power domain

off or on

if on at what voltage

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Specify Power Mode Transitions

create_mode_transition -name PM1toPM2 –from_mode PM1 –to_mode PM2 \

-start_condition { pcu_inst/ctrl[0] & pcu_inst/ctrl[1] }

-clock_pin { pcu_inst/clk } –cycles 100create_mode_transition -name PM2toPM3 –from_mode PM2 –to_mode PM3 \

-start_condition { pcu_inst/ctrl[0] & !pcu_inst/ctrl[1] }

-clock_pin { pcu_inst/clk } –cycles 1000


-start_condition { !pcu_inst/ctrl[0] & pcu_inst/ctrl[1] }



-start_condition { !pcu_inst/ctrl[0] & !pcu_inst/ctrl[1] }



PM1 1.2v

0.8v


PM4 0.8v 1.2v 1.2v 1.2v off

1.2v 1.2v 1.2v

PM2

1.2v

1.2v 1.2v 1.2voff

PM1

PM2

PM3

PM4

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Complete create_mode_transition Command

create_mode_transition -name string

-from_mode power_mode -to_mode power_mode

-start_condition expression [-end_condition expression]

[-clock_pin clock_pin [-cycles number | -latency float]]

● Specify a single mode transition

● Each mode transition involves a series of power domain changes

● The start condition and end condition can be used by verification tools to trace the modetransition and record coverage on modes and mode transitions

● The transition time can be used to simulate the latency of each mode transition

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Put Everything Together For Design Specification

set_design nano_cpu


create_power_domain -name PDau -instances alu_inst /aui -shutof f_condi tion pcu_inst/pau[2]

create_power_domain -name PDlu -instances alu_inst/lui -shutoff_condition pcu_inst/plu[2]

create_power_domain -name PDalu -instances alu_inst -shutoff_condition pcu_inst /palu[2]create_power_domain -name PDrf -instances rf_inst -shutoff_condition pcu_inst/prf[2]

create_state_retention_rule –name sr_rule –domain PDrf -restore_edge { ! pcu_inst/prf[1] }

create_isolation_rule -name iso_rule1 -from PDau -isolation_condition {!pcu_inst /pau[0]} -isolation_output low

create_isolation_rule -name iso_rule2 -from PDlu -isolation_condition {!pcu_inst/plu[0]} -isolation_output low

create_isolation_rule -name iso_rule3 -from PDalu -isolation_condition {!pcu_inst/palu[0]} -isolation_output low

create_isolation_rule -name iso_rule4 -from PDrf -isolation_condit ion {!pcu_inst/prf[0]} -isolation_output low

create_nominal_condi tion -name high -voltage 1.20

create_nominal_condition -name low -vol tage 0.8


–defaul t -domain_condi tions {PDcore@high PDau@high PDlu@high PDalu@high PDrf@high}

create_power_mode -name PM2 -domain_conditions {PDcore@low PDlu@high PDalu@high PDrf@high}

create_power_mode -name PM3 -domain_condit ions {PDcore@low PDrf@high}

create_power_mode -name PM4 -domain_conditions {PDcore@low PDau@high PDlu@high PDalu@high }

end_design

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Low Power Design Verification Using CPF

● No need to specify power or ground nets at RTL stage

● No need to specify implementation related constraints at this stage suchas library, timing constraints etc

● Minimal set of CPF commands for front-end designers to use Simulation tools

to simulation power domain on and off

to simulate power mode transitions for DVFS

Coverage tools to check power mode coverage

to check power mode transition coverage

Assertion tools

to generate power domain and mode aware assertions

Verification tools

to check for the correctness and completeness of CPF

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What About Implementation?

● For synthesis

Need to specify the libraries

Need to link the libraries to each power domain in each power mode

Need to associate timing constraints for each power mode to perform DVFS synthesis

● For physical implementation and verification

Need to specify power and ground net work

Need to specify how power switch network should be implemented● Additional CPF commands are needed


update_power_domain

update_power_mode

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Specify Technology Libraries And Special Low Power Cells

#Libraries for implementation, file name tech.cpf

set libdir ../../../libs

set 08v_list "$libdir/130e_sp_tt_0p8v_25c.lib … "

set 120v_list "$libdir/13sp_tt_0p8v_1p2v_25c.lib …"

define_library_set -name 08v -libraries $08v_list

define_library_set -name 120v -libraries $120v_list

define_level_shi fter_cell -cells LVLHLEHX* -input_voltage_range 1.2 \

-output_voltage_range 0.8 -direction down –valid_location to

define_level_shifter_cell -cells LVLHLX* -input_voltage_range 1.2 \

-output_voltage_range 0.8 -direction down –valid_location to

define_level_shifter_cell -cells LVLLHEHX* -input_voltage_range 0.8 \

-output_voltage_range 1.2 -direction up –valid_location to

define_level_shifter_cell -cells LVLLHX* -input_voltage_range 0.8 \

-output_voltage_range 1.2 -direction up –valid_location to

define_isolation_cell -cells ISOLN* -enable EN -valid_location from

define_isolation_cell -cells "LVLHLEHX* LVLLHEHX* LVLHLELX*" -enable ENdefine_always_on_cell -cells "BUFGX2M BUFGX8M INVGX2M INVGX8M"

define_state_retention_cell -cells *DRFF* -restore_function RETN

define_power_swi tch_cell -cells "HEAD8DM HEAD16DM HEAD32DM HEAD64DM“ –ground VSS \

-power_switchable VDD -power VDDG –stage_1_enable SLEEP –stage_1_out SLEEPOUT –type header

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Link Technology Libraries And Timing Constraints

#fi le name syn.cpf

update_nominal_condit ion -name high -library_set 120v

update_nominal_condit ion -name low -library_set 08v

update_power_mode –name PM1 –sdc_files ../../../sdc/PM1.sdc

update_power_mode –name PM4 –sdc_files ../../../sdc/PM4.sdc

● The synthesis l ibraries are automatically linked to each power domain foreach power domain

● Associate timing constraints to each power mode for DVFS synthesis


PM1 1.2v

0.8v


PM4 0.8v 1.2v 1.2v 1.2v off

1.2v 1.2v 1.2v

PM2

1.2v

1.2v 1.2v 1.2voff

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Complete Command Syntax

update_nominal_condition -name nominal_condition -library_set library_set

update_power_mode -name mode

{ -activity_file file -activity_file_weight weight

| -sdc_files sdc_file_list

| -peak_ir_drop_limit domain_voltage_list

| -average_ir_drop_limit domain_voltage_list

| -leakage_power_limit float

| -dynamic_power_limit float}...

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Put Everything Together For Logic Implementation

include tech.cpf

set_design nano_cpu




create_power_domain -name PDalu -instances alu_inst -shutoff_condition pcu_inst /palu[2]

create_power_domain -name PDrf -instances rf_inst -shutoff_condition pcu_inst/prf[2]




create_isolation_rule -name iso_rule3 -from PDalu -isolation_condition {!pcu_inst/palu[0]} -isolation_output lowcreate_isolation_rule -name iso_rule4 -from PDrf -isolation_condit ion {!pcu_inst/prf[0]} -isolation_output low

create_nominal_condi tion -name high -voltage 1.20



–defaul t -domain_condi tions {PDcore@high PDau@high PDlu@high PDalu@high PDrf@high}

create_power_mode -name PM2 -domain_conditions {PDcore@low PDlu@high PDalu@high PDrf@high}

create_power_mode -name PM3 -domain_conditions {PDcore@low PDrf@high}

create_power_mode -name PM4 -domain_conditions {PDcore@low PDau@high PDlu@high PDalu@high }

source syn.cpf

end_design

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Low Power Logic Implementation and Verif ication Using CPF

● Still , no need to specify power or ground nets at this design stage

● Minimal set of CPF commands for designers to use

Logic synthesis tools

to synthesize isolation, level shifter and state retention logic

to perform power domain aware logic synthesis

to perform power mode aware (DVFS) synthesis

Test synthesis tools

to perform power domain and power mode aware DFT synthesis

to generate power domain aware test control logic Formal Verification tools

to check the correctness of low power structural implemented by synthesis tools

to perform low power equivalency checking (RTL+CPF vs Netlist)

Simulation tools

to perform power aware gate level simulation

to generate additional assertions for gate level simulation

Analysis tools

to perform power domain aware and power mode aware power analysis

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Specify Power/Ground Nets for Physical Implementation

#file name phy_pg.cpf #power/ground net specification

create_power_nets –nets VDD1 –vol tage 1.2

create_power_nets –nets VDD2 –voltage 0.8

create_power_nets –nets { VDD_core VDD1_au_sw VDD1_lu_sw VDD1_alu_sw VDD1_rf_sw} –internal

create_ground_nets –nets VSS

update_power_domain –name PDcore –internal_power_net VDD_core –internal_ground_net VSS

update_power_domain –name PDau –internal_power_net VDD1_au_sw –internal_ground_net VSS

update_power_domain –name PDlu –internal_power_net VDD1_lu_sw –internal_ground_net VSS

update_power_domain –name PDalu –internal_power_net VDD1_alu_sw –internal_ground_net VSS

update_power_domain –name PDrf –internal_power_net VDD1_rf_sw –internal_ground_net VSS

#power switch specification for power shutoff

create_power_switch_rule –name PDau_sw –domain PDau –external_power_net VDD1

create_power_switch_rule –name PDlu_sw –domain PDlu –external_power_net VDD1

create_power_switch_rule –name PDalu_sw –domain PDalu –external_power_net VDD1

create_power_switch_rule –name PDrf_sw –domain PDrf –external_power_net VDD1

#power switch specification for DVFS control

create_power_switch_rule –name PDcore_1 –domain PDcore –external_power_net VDD1

update_power_switch_rule –name PDcore_1 –enable_condition_1 {pcu_inst/pcore[2]}

create_power_switch_rule –name PDcore_2 –domain PDcore –external_power_net VDD2

update_power_switch_rule –name PDcore_2 –enable_condition_1 {!pcu_inst /pcore[2]}

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Complete Command Syntax for Power/Ground Nets Specification

create_power_nets -nets net_list [-voltage string]

[-external_shutoff_condition expression | -internal] [-user_attributes string_list]

[-peak_ir_drop_limit float] [-average_ir_drop_limit float]

create_ground_nets -nets net_list [-voltage string]

[-internal] [-user_attributes string_list]

[-peak_ir_drop_limit float] [-average_ir_drop_limit float]

update_power_domain -name domain

{ -internal_power_net net | -internal_ground_net net

| -min_power_up_time float | -max_power_up_time float| -pmos_bias_net net | -nmos_bias_net net | -user_attributes string_list

| -rail_mapping rail_mapping_list -library_set library_set} ...

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Complete Command Syntax for Power Switch Specification

create_power_switch_rule -name string

-domain power_domain {-external_power_net net | -external_ground_net net}

update_power_switch_rule -name string

{ -enable_condition_1 expression [-enable_condition_2 expression]

| -acknowledge_receiver pin

| -cells cell_list -library_set library_set

| -prefix string

| -peak_ir_drop_limit float

| -average_ir_drop_limit float }...

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Specify MMMC Constraints for Physical Timing Closure & Analysis

#file name phy_mmmc.cpf to setup Multi-Mode-Multi-Corner (MMMC) timing closure constraints

create_operating_corner –name 120v_fast –voltage 1.3 –library_set 120v

create_operating_corner –name 120v_slow –voltage –library_set 120v

create_operating_corner –name 08v_fast –voltage 0.9 –library_set 08v

create_operating_corner –name 08v_slow –voltage 0.7 –library_set 07v

create_analysis_view –name view1 –mode PM1 –domain_corners \

{ PDcore@120v_fast PDau@120v_fast PDlu@120v_fast PDalu@120v_fast PDrf@120v_fast}


{ PDcore@120v_slow PDau@120v_slow PDlu@120v_slow PDalu@120v_slow PDrf@120v_slow}


{ PDcore@08v_fast PDau@120v_fast PDlu@120v_fast PDalu@120v_fast }


{ PDcore@080v_slow PDau@120v_slow PDlu@120v_slow PDalu@120v_slow }


PM1 1.2v 1.2v 1.2v 1.2v

0.8v


PM4 0.8v 1.2v 1.2v 1.2v off

PM2

1.2v

1.2v 1.2v 1.2vof f

Need to analysis 2 corners forthis mode, fast and slow

Need to analysis 2 corners for

this mode, fast and slow

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Command Syntax for MMMC Setup

create_operating_corner -name string -voltage float

[-process float] [-temperature float] -library_set library_set

create_analysis_view -name string -mode mode

-domain_corners domain_corner_list

O i f CPF S t f DVFS & MMMC

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-name <nominal_condition>-library_set <name>

update_power_mode

-name <mode_name>[ -activity_file file -activity_file_weight weight ][ -sdc_files sdc_file_list ]

create_analysis_view-name <string>-mode <mode_name>-domain_corners

{ list_of_operating_corners_by_domain }

create_power_mode

-name <string>-domain_conditions

{ list_of_nominal_condition_by_domains }

create_operating_corner

-name <string>-voltage <float>

[-process <float>][-temperature <float>]-library_set <name>

define_library_set

-name <library_set>

-timing <library_list>

create_nominal_condition

-name <string>-voltage <float>

create_power_domain

-name <string>{-default [-instances instance_list ][-boundary_ports pin_list ]| -instances instance_list

[-boundary_ports pin_lust ][-boundary_ports pin_list }

[-shoutoff_condition expression]

DVFS

MMMC

Overview of CPF Support for DVFS & MMMC

P t E thi T th F Ph i l I l t ti

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Put Everything Together For Physical Implementation

include tech.cpf

set_design nano_cpu




create_power_domain -name PDalu -instances alu_inst -shutoff_condition pcu_inst/palu[2]

create_power_domain -name PDrf -instances rf_inst -shutoff_condi tion pcu_inst/prf[2]




create_isolation_rule -name iso_rule3 -from PDalu -isolation_condi tion {!pcu_inst/palu[0]} -isolation_output lowcreate_isolation_rule -name iso_rule4 -from PDrf -isolation_condit ion {!pcu_inst/prf[0]} -isolation_output low

create_nominal_condition -name high -voltage 1.20



–default -domain_conditions {PDcore@high PDau@high PDlu@high PDalu@high PDr f@high}

create_power_mode -name PM2 -domain_condi tions {PDcore@low PDlu@high PDalu@high PDrf@high}

create_power_mode -name PM3 -domain_conditions {PDcore@low PDrf@high}

create_power_mode -name PM4 -domain_condi tions {PDcore@low PDau@high PDlu@high PDalu@high }

source syn.cpf

source phy_pg.cpf

source phy_mmmc.cpf

end_design

Lo Po er Ph sical Implementation and Verif ication Using CPF

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Low Power Physical Implementation and Verif ication Using CPF

● At this stage

The power and ground nets for each power domain are fully specified

The power switch logic is specified for each domain

● Complete set of CPF commands for back-end designers to use Physical implementation tools

to perform power domain aware placement and routing

to insert and optimize power switch network

to connect the power and ground nets to insert additional low power logic due to netlist change if needed

to perform Multi-Mode-Multi-Corner timing and power optimization and analysis

Verification tools

to check the correctness of low power physical structural

Analysis tools

to perform dynamic analysis power switch network

to perform sign-off power and timing analysis

Other Implementation related commands

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Other Implementation related commands

Optional implementation constraints to provide designers more flexibility in logicaland physical implementation

update_isolation_rules -names rule_list { -location {from | to}| -cells cell_list -library_set library_set

| -prefix string | -combine_level_shifting

| -open_source_pins_only}...

update_level_shifter_rules -names rule_list

{ -location {from | to} | -cells cell_list -library_set library_set

| -prefix string }...

update_state_retention_rules -names rule_list

{-cell_type string | -cell libcell -library_set library_set} …

Other Commands

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Other Commands

● Hierarchical Flow

set_instance [hier_instance [-merge_default_domains]

[-port_mapping port_mapping_list]]

set_hierarchy_separator string

● RTL to Netl ist Name Mapping

set_register_naming_style

set_array_naming_style

● General Commands

set_cpf_version

set_power_target

set_power_unit

set_switching_activity

set_time_unit

Outline

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Outline


●CPF Basics



●

Where Is CPF Headed?

CPF Enabled Low Power Design Flow

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?

CPF Enabled Low Power Design Flow

Design Creationb

Synthesis

ConstraintGeneration

Design for Test

SVP

E

q ui v al en c e C h e c k i n

g


SpecificationFunction, timing, power

RTLCoding

RTL + CPFCoding

Iterate

Quick architectural explorationRe-use pre-verified IPInstantiate single

RTL with differentpower profiles

Hand off to drive physicalimplementation

Physical Implementation

Chip Integration

Prototyping

Physical Synthesis

Routing

DF T

A n al y s i s

Sign-off

A T P G

C on s t r ai n t V al i d a t i o

n

E q

ui v al en c e

c

h e c k i n g

L V S / DR C / E x t

GDSII

Constraints CPF Netlist

Goldenspecification

eliminatesassumptions and

miscommunications

Automatic partitioning ofpower domains

Automatic scheduling oftest modes

Single powerspecification used from

specification to GDSII

V e r i f i c a t i o n C o v e r a

g e

T e s t b e n c h A u t o m a t i o n

Verification

Structural &Funct. Checks

Formal Analysis

Simulation

Accelerat ion

& Emulation

Functionally verifyadvanced powerimplementation

techniquesIterate

Continued Industry Wide Adoption of CPF

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Continued Industry Wide Adoption of CPF

1Q2007 2H2007

• CPF becomesSi2 standard

• Cadence LowPower Solutionproductionreleased V 1.0

ReferenceFlow 8.0

PRIDE Flow

CommonPlatformFlow

Joins PFI

PowerPro CG

DDR PHY

EnergyProTechnology

Joins PFI

Joins PFI

Joins PFI

2Q2007

• > 100 customer adopting

CPF-based advanced lowpower solut ion

• ~ 50 tapeoutsFreescale, Fujitsu, NEC, NXP..

Ecosystem Support for CPF Based Low Power Solution

http://www.starc.jp/index-e.html






















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y pp

ASIC /Design

Service

IP Vendor

EDA

Foundry

Early Adopters

www.powerforward.org

TSMC 8 0 Low Power Reference Flow

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– 48 –Innovation Through Collaboration – 48 –Innovation Through Collaboration – Low Power Coalition48

TSMC 8.0 Low Power Reference Flow

C

P F

C

P F

CPF Quality CheckConformal Low Power

CPF Quali ty CheckConformal Low Power

CPF-Enabled Funct ional simulationIncisive Design Team Simulator

Incisive Design Team Manager

CPF-Enabled Funct ional simulationIncisive Design Team Simulator

Incisive Design Team Manager

CPF-Enabled Logic Synthesis & DFT

Encounter RTL Compiler

CPF-Enabled Logic Synthesis & DFT

Encounter RTL Compiler CPF-Enabled LEC + Power Checks

Conformal Low Power

CPF-Enabled LEC + Power ChecksConformal Low Power



CPF-Enabled Timing & SI signoff Encounter Timing System

CPF-Enabled Timing & SI signoff Encounter Timing System

CPF-Enabled Physical implementationSoC Encounter

CPF-Enabled Physical implementationSoC Encounter

CPF-Enabled Logic simulationIncisive Design Team Simulator

CPF-Enabled Logic simulationIncisive Design Team Simulator

CPF-Enabled ATPGEncounter Test

CPF-Enabled ATPGEncounter Test

CPF-Enabled IR drop & Power signoff VoltageStorm-DG

CPF-Enabled IR drop & Power signoff

VoltageStorm-DG

CPF-Enabled Leakage & Thermal AnalysisEncounter Timing System

CPF-Enabled Leakage & Thermal AnalysisEncounter Timing System

www.tsmc.com

ARC Proof Point Project Using CPF Based Low Power Solution

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j g

● Simulation with CPF identifiesproblems that you will nototherwise identify

●

CPF aids communication of powerintent across team boundaries,ensuring accurate implementationat all f low stages

● Signif icant power savings resultsusing these techniques

Always On

SCQSCQSCQ

SCQ SCM SDMSIMD

SCM SDM

I$ D$ SCQARC700

I$ D$

Clock Gating Domains

Power DomainsFunctional Blocks

ARC700 with SIMD Co-Processor

• For high bit-rate data streams, boththe ARC and the SIMD run flat out

• For lower bit-rate data stream, thesubsystem can be run at a lowerfrequency

• For generic processing, the SIMDcan be inactive

Power Forward

low-power implementation &verification project results

Fujitsu Proof Point Project Using CPF Based Low Power Solution

http://www.arc.com/index.html

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j j g

CPU1 CPU2peripherals

Power Switch

90nm940K instances11 Power Domains

19 Power Modes

PowerDomains

●

Verified with test design PSO functional verification with simulation

Low power structural and physical check(Shifters/Isolators/Power switches)

Domain aware place and route

● Conclusion

Functional verification is necessary forcomplex PSO design for design bugs

Structural check with CPF could verify LPdesign

Fujitsu will support CPF-based ASIC flow fortheir customers

Silicon Proven September ‘07Silicon Proven September ‘07

DVFS

NEC Proof Point Project Using CPF Based Low Power Solution

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Power DomainPowerMode

PD0 PD1 PD2 PD3 PD4 PD5

PM1 1.2V 1.2V 1.2V 0.74V 0.74V 0.74V

PM2 1.2V PSO 1.2V 0.74V 0.74V 0.74V

PM3 1.2V 1.2V PSO 0.74V 0.74V 0.74V

PM4 1.2V 1.2V 1.2V PSO 0.74V 0.74V

PM5 1.2V PSO PSO PSO 0.74V PSO

Driver

PD4:0.74V

PD0: 1.2V(Default,

Always On)

PD5:0.74V

PD3:0.74V

PD2:1.2V

PD1:1.2V

PSOcntl

PSGcntl

ISOcntl

Validated CPF and CPF-based flowfor major low power methodologiesin NEC Electronics

386 checkpoints evaluated successfully

CPF describe-abil ity

Multi-Supply-Voltage (MSV)

Power Shut Off (PSO)

State Retention Logic (SRL)

Variable Voltage Library (VVL)

Clock Tree Gating (CTG)

CPF based flow wil l be in use from Q3/2007

NEC ElectronicsNEC ElectronicsCorporationCorporation

65nm6 Power Domains5 Power Modes2 Supply Voltage

NXP Proof Point Project Using CPF Based Low Power Solution

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Power Forward low-powerplatform SoC results

● CPF-based functionalverification (using simulation)catches system level powerissues early in the flow

● Use of CPF ensured whatimplementation built was whatwas verified

• SoC consists of 11 islands

• 3 major power consumers -RISCCPU, VLIW DSP & L2 System

Cache are controlled using DVFS• High bandwidth expansion ports

enable extension, with graphicsor cellular modem subsystems

Outline

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●CPF Basics




Si2 LPC Progress

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● Three Working Groups

Data API

Common Glossary

Design Flow Low Power Design Flow Document

Format Requirement

● Format Requirement Working Group

Clarification on CPF 1.0 semantics

Collect new requirements for formatimprovements

Custom macro modeling

More flexibili ty on IP reuse

Complete hierarchical flow

…

g

CPF Related Information

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● CPF 1.0 Documents & Parser http://www.si2.org/openeda.si2.org/projects/si2cpf/

● Si2 LPC http://www.si2.org

● Power Forward Init iative http://www.powerforward.org● Power Format Comparison http://www.si2.org/?page=866