CPE 201 Digital Design Lecture 20: Sequential Logic (5)

CPE 201Digital Design

Lecture 20:

Sequential Logic (5)

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Lecture Outline

• Excitation Tables

• Controller Design Examples

• State Reduction

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Understanding the Controller’s Behavior

s0s1

b x

n1

n0

x=1 x=1 x=1b

01 10 11On2On1

Off

On3

00

0 0

0

00

0

b’

0

0

0

00

x=0

000

clk

clk

Inputs:

Outputs:

1

0

10

b

1

0

10

0

s0s1

b x

n1

n0

x=1 x=1 x=1

b’

01 10 11On2On1

Off

On3

clk

b

x

00

0 0

x=0

000

state=00 state=00

s0s1

b x

n1

n0

x=1 x=1 x=1

x=0

b

b’

01

00

10 11On2On1

Off

On3

1

0

1

1

0

00

110

clk0 1

01

state=01

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Controller Example: Button Press Synchronizer

• Want simple sequential circuit that converts button press to single cycle duration, regardless of length of time that button actually pressed– We assumed such an ideal button press signal in

earlier example, like the button in the laser timer controller

cycle1 cycle2 cycle3 cycle4clk

Inputs:

Outputs:

bi

bo

Button press synchronizer

controller

bi bo

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Controller Example: Button Press Synchronizer (cont.)

A

B

C

s100001111

s000110011

bi01010101

Inputs

n100010100

n001000000

bo00110000

OutputsCombinational logic

unused

Step 4: State table

Step 1: FSM

A B C

bo=1bo=0 bo=0bi

bibi’

bi’

bi’bi

FSM inputs: bi; FSM outputs: bo

Step 3: Encode states

00 01 10

bo=1bo=0 bo=0bi

bibi’

bi’

bi’bi

FSM inputs: bi; FSM outputs: bo

Step 5: Create combinational circuit

clkState register

bo

bi

s1 s0

n1

n0

Combinational logic

n1 = s1’s0bi + s1s0’bin0 = s1’s0’bibo = s1’s0bi’ + s1’s0bi = s1’s0

Step 2: Create architectureCombinational

logic

n0s1 s0

n1

bobi

clkState register

FSM

inputs

FSM

outp

uts

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• Design a circuit to detect three or more consecutive 1’s in a string of bits coming through an input line

Present State Input Next State Output

A B x A B y

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 0

0 1 1 1 0 0

1 0 0 0 0 0

1 0 1 1 1 0

1 1 0 0 0 1

1 1 1 1 1 1

A(t+1)= Σ(3,5,7)

B(t+1)= Σ(1,5,7)

Y(A,B,x)= Σ(6,7)

Sequence Decoder Example

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A(t+1)=DA(A,B,x)= Σ(3,5,7)

B(t+1)=DB(A,B,x)= Σ(1,5,7)

Y(A,B,x)= Σ(6,7)

DA = Ax + Bx DB = Ax + B’x y = AB

Synthesis Using D Flip-Flops

• Need 2 D flip-flops to represent the four states

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DA = Ax + BxDB= Ax + B’xy=AB

Sequence Detector Logic Diagram

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Excitation Tables

• Using flip-flops other than D can be complicated

• Why?

– Input equations for the circuit

must be derived indirectly from

the state table

• Excitation tables can help

– They give us the flip-flop input that would cause a

state transition

Combinationallogic

State register

s1 s0

n1

n0

xb

clk

FSM

inp

uts

FSM

ou

tpu

ts

DA DB

JA JBKA KB

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Excitation Tables – JK Flip-Flop

• During design we know the transition Q(t) Q(t+1) and want to know inputs JK that lead to the transition

Q(t) Q(t+1) J K Input situation

0 0

0 1

1 0

1 1

Reset, No change

Set, Complement

Reset, Complement

Set, No change

Q(t+1) = JQ’(t) + K’Q(t)

0

1

X

X

X

X

1

0

Excitation table

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Excitation Tables – T Flip-Flop

Q(t) Q(t+1) T Input situation

0 0

0 1

1 0

1 1

No change

Complement

0

1

1

0

Complement

No change

Q(t+1) = TQ’(t) + T’Q(t) = T XOR Q

Excitation table

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Synthesis Using JK Flip-Flops

Present State Input Next State Flip-Flop Inputs

A B x A B JA KA JB KB

0 0 0 0 0 0 x 0 x

0 0 1 0 1 0 x 1 x

0 1 0 1 0 1 x x 1

0 1 1 0 1 0 x x 0

1 0 0 1 0 x 0 0 x

1 0 1 1 1 x 0 1 x

1 1 0 1 1 x 0 x 0

1 1 1 0 0 x 1 x 1

• We have to include J, K input conditions, derived from the excitation table

Available from the FSM diagram

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Synthesis Using T Flip-Flops

• E.g.: 3-bit Binary Counter– The counter counts with the clock

State diagram

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Present State Next State Flip-Flop InputsA2 A1 A0 A2 A1 A0 TA2 TA1 TA00 0 0 0 0 1 0 0 10 0 1 0 1 0 0 1 10 1 0 0 1 1 0 0 10 1 1 1 0 0 1 1 11 0 0 1 0 1 0 0 1 1 0 1 1 1 0 0 1 11 1 0 1 1 1 0 0 11 1 1 0 0 0 1 1 1

State diagram

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Controller Example: Sequence Generator

• Want to generate sequence 0001, 0011, 1100, 1000, (repeat)– Each value for one clock cycle

00

01 10

11A

B

D

wxyz=0001 wxyz=1000

wxyz=0011 wxyz=1100

C

Inputs: none; Outputs: w,x,y,z

Step 3: Encode states

Step 4: Create state table

clk State register

w

x

y

z

n0s0s1

n1

Step 5: Create combinational circuit

w = s1x = s1s0’y = s1’s0z = s1’n1 = s1 xor s0n0 = s0’

Step 1: Create FSM

A

B

D

wxyz=0001 wxyz=1000

wxyz=0011 wxyz=1100

C

Inputs: none; Outputs: w,x,y,z

Step 2: Create architecture

Combinationallogic

n0s1 s0

n1

clk State register

wxyz

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Controller Example: Secure Car Key

• (from earlier example)

K1 K2 K3 K4

r=1 r=1 r=0 r=1

Waitr=0

Inputs: a; Outputs: r

a’a

Ste

p 1

Combinationallogic

s2 s1 s0

n2

ra

n1n0

clk State register

Ste

p 2

a’a

r=0

r=1 r=1 r=0 r=1

000

001 010 011 100

Inputs: a;Outputs: r

Ste

p 3

Step 4We’ll omit Step 5

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FSM Example: Code Detector

• Unlock door (u=1) only when buttons pressed in sequence: – start, then red, blue, green, red

• Input from each button: s, r, g, b– Also, input a indicates that some

colored button pressed• FSM

– Wait for start (s=1) in “Wait”– Once started (“Start”)– If see red, go to “Red1”– Then, if see blue, go to “Blue”– Then, if see green, go to “Green”– Then, if see red, go to “Red2”

• In that state, open the door (u=1)– Wrong button at any step, return to

“Wait”, without opening door

Start

RedGreen

Blue

s

rg

ba

Doorlock

u

Codedetector

Q: Can you trick this FSM to open the door, without knowing the code?

A: Yes, hold all buttons simultaneously

Wait

Start

Red1 Red2GreenBlue

s’

a’

ar’ ab’ ag’ ar’

a’

ab ag ar

a’ a’u=0

u=0ar

u=0 s

u=0 u=0 u=1

Inputs: s,r,g,b,a;Outputs: u

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Improve FSM for Code Detector

• New transition conditions detect if wrong button pressed, returns to “Wait”

Wait

Start

Red1 Red2GreenBlue

s’

a’

a’

ab ag ar

a’ a’u=0

u=0 ar

u=0 s

u=0 u=0 u=1

ar’ ab’ ag’ ar’

Inputs: s,r,g,b,a;Outputs: u

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Common Pitfalls Regarding Transition Properties

• At most one condition must be true– For all transitions

leaving a state

• At least one condition must be true– For all transitions

leaving a state

a

bIf ab=11

next state=?

a

a’b

a

What ifab=00?

a’b

a

a’b

a’b’

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Verifying Correct Transition Properties

• Can verify using Boolean algebra• At most one condition true

– AND of each condition pair (for transitions leaving a state) should equal 0 proves pair can never simultaneously be true

• At least one condition true – OR of all conditions of transitions leaving a

state should equal 1 proves at least one condition must be true

– Examplea

a’b

a + a’b= a*(1+b) + a’b= a + ab + a’b= a + (a+a’)b= a + bFails! Might not be 1 (i.e., a=0, b=0)

Q: For shown transitions, prove whether: * At most one condition true (AND of each pair is always 0) * At least one condition true (OR of all transitions is always 1)

a * a’b= (a * a’) * b= 0 * b= 0OK!

Answer:

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Evidence that Pitfall is Common

• Recall code detector FSM– We “fixed” a problem with the

transition conditions– Do the transitions obey the

two required transition properties?

• Consider transitions of state Start, and the “at most one true” property

Wait

Start

Red1 Red2GreenBlue

s’

a’

a’

ab ag ar

a’ a’u=0

u=0ar

u=0s

u=0 u=0 u=1ar * a’ a’ * a(r’+b+g) ar * a(r’+b+g) = (a*a’)r = 0*(r’+b+g) = (a*a)*r*(r’+b+g) = a*r*(r’+b+g) = 0 = 0 = arr’+arb+arg

= 0 + arb+arg = arb + arg = ar(b+g)

Fails! Means that two of Start’s transitions could be true

Intuitively: press red and blue buttons at same time: conditions ar, and a(r’+b+g) will both be true. Which one should be taken?

Q: How to solve? a

A: ar should be arb’g’(likewise for ab, ag, ar)

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Simplifying Notations

• FSMs– Assume that unassigned

output is implicitly 0

• Sequential circuits– Assume that unconnected

clock inputs are implicitly connected to same external clock

a=0b=1c=0

a=0b=0c=1

b=1 c=1clk a

a

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State Reduction and Assignment

• Goal: Reduce the number of states while keeping the external input-output requirements

• 2m states need m flip-flops, so reducing the states may reduce flip-flops

• If two states are equivalent, one can be removed

• What are equivalent states?

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010101110100 applied and start from state a

State a a b c d e f f g f g ainput 0 1 0 1 0 1 1 0 1 0 0 output 0 0 0 0 0 1 1 0 1 0 0

State Reduction Example

• For state reduction only input-output sequences are important– States are only used to provide the

output sequence

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Present State Next State Output x=0 x=1 x=0 x=1

a a b 0 0 b c d 0 0 c a d 0 0 d e f 0 1 e a f 0 1 f g f 0 1 g a f 0 1

States e and g are equal since for each member of the set of inputs, they give the same output and send the circuit either to the same state or an equivalent state

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a a b 0 0 b c d 0 0 c a d 0 0 d e f 0 1 e a f 0 1 f e f 0 1

Table and state diagram after the first reduction: g is removed and replaced by state e.

NEW equal states: d and f

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a a b 0 0 b c d 0 0 c a d 0 0 d e d 0 1 e a d 0 1

Table and state diagram after the second reduction: f is removed and replaced by state d.

If we apply the same input sequence:

State a a b c d e d d e d e ainput 0 1 0 1 0 1 1 0 1 0 0 output 0 0 0 0 0 1 1 0 1 0 0

Reduced state diagram

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Design Procedure

1. From word description, derive state diagram

2. Reduce the number of states

3. Assign binary values to states

4. Obtain the binary coded state table

5. Choose the type of flip-flop used

6. Derive the simplified flip-flop input and output equations

7. Draw the logic diagram

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Chapter Summary

• Sequential circuits– Have state

• Created robust bit-storage device: D flip-flop– Put several together to build register, which we used to hold state

• Defined FSM formal model to describe sequential behavior– Using mathematical models – Boolean equations for combinational

circuit, and FSMs for sequential circuits

• Defined step process to convert FSM to sequential circuit– Controller

• So now we know how to build sequential circuits (known as controllers)

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Readings

• Chapter 5– Sections 5.8

Documents

CPE 201 Digital Design Lecture 20: Sequential Logic (5)