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CPE 201Digital Design
Lecture 21:
Registers and Counters (1)
2
Lecture Outline
• Registers
3
Registers – Introduction
• So far we introduced increasingly complex digital building blocks– Gates, multiplexers, decoders, basic registers, and
controllers• Controllers are good for systems with control
inputs/outputs– Control input: Single bit (or just a few),
representing environment event• e.g., 1 bit representing button pressed
– Data input: Multiple bits collectively representing single entity• e.g., 7 bits representing temperature in binary
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Registers – Introduction
• Need building blocks for data– Datapath components, aka register-transfer-level
(RTL) components, store/transform data• Put datapath components together to form a datapath
• We will introduce several datapath components, and simple datapaths– Register: A group of flip-flops each storing one bit of
information– Registers include flip-flops and gates: flip-flops hold
the information, gates control how the information is transferred to the register
– Counter is a register that goes through a predetermined sequence of states
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Registers
• Can store data, very common in datapaths
• Basic register: loaded every cycle– Useful for implementing FSM,
stores encoded state– For other uses, may want to
load only on certain cycles
Combinationallogic
State register
s1 s0
n1
n0
xb
clk
I3 I2 I1 I0
Q3Q2Q1Q0
reg(4)
Basic register loads on every clock cycle
load
How to extend to only load on certain cycles?
DQ
DQ
DQ
DQ
I2I3
Q2Q3 Q1 Q0
I1 I0
clk
4-bit register
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Register with Parallel Load
To fully synchronize the system, clock signals should arrive at the same time at all flip-flops.
Therefore we should not control the clock by gates.
Load = 1, we load data
Load =0, register content does not change
1
I0
I3
I2
I1
1
1
1
1
1
7
Register with Parallel Load
Load =0, register content does not change
0
A0
A3
A2
A1
0
0
0
0
0
1
1
1
1
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Register with Parallel Load
• Add 2x1 mux to front of each flip-flop• Register’s load input selects mux input to pass
– Either existing flip-flop value, or new value to load
1 0
D
Q
Q3
I3
1 0
D
Q
Q2
I2
1 0
Q
Q1
I1
1 0
D
Q
Q0
I0
load
= 0
1 02×1
D
Q
Q3
I3
loadload
1 0
D
Q
Q2
I2
1 0
D
Q
Q1
I1
1 0
D
Q
Q3
I3
1 0
D
Q
Q2
I2
1 0
D
Q
Q1
I1
1 0
D
Q
Q0
I0
load
= 1
(b)
(c)(a)
1 0
D
Q
Q0
I0
I3 I2 I1 I0
Q3 Q2 Q1 Q0
D
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Basic Example Using Registers
• Parallel transfer• This example will show
how registers load simultaneously on clock cycles– Notice that all load
inputs set to 1 in this example - just for demonstration purposes
Q3 Q2 Q1 Q0
a3 a2 a1 a0
I3 I2 I1 I0
Q3 Q2 Q1 Q0
I3ld1 I2 I1 I0
ld1 ld1
Q3 Q2 Q1 Q0
I3 I2 I1 I0
R1
R0
R2
clk
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Basic Example Using Registers
Q3Q2Q1Q0
a3 a2 a1 a0
I3 I2 I1 I0
Q3Q2Q1Q0
I3ld1 I2 I1 I0
ld1 ld1
Q3Q2Q1Q0
I3 I2 I1 I0
R1
R0
R2
clk
????
????
R1????R2
–>1111
R0
clk
a3..a0
R0
R1
R2
give
n
????
1111
R1????R2
1111–>0001
R0
1111
0001
R10000R2
0001–>1010
R0
0001
1010
R11110R2
1010
R0
1010
1010
R10101R2
1010
R0
1010
1010
R10101R2
1010
R0
(a)
(b)
1111
????
????
????
????
????
0001
1111
1111
0000
0001
0001
1110
1010
1010
0101
1010
1010
0101
1010
1010
1 2 3 4 5
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Register Example using the Load Input: Weight Sampler
• Scale has two displays– Present weight– Saved weight– Useful to compare present
item with previous item
• Use register to store weight– Pressing button causes
present weight to be stored in register
– Register contents always displayed as “Saved weight,” even when new present weight appears
Scale
Saved weight
Weight Sampler
Present weight clk
bSave
I3 I2 I1 I0
Q3 Q2 Q1 Q0
load3 pounds
0 0 1 1
0 0 1 1
3 pounds
0 0 1 0
2 pounds1
• Earlier example: Four simultaneous values from car’s computer
• To reduce wires: – computer writes only 1
value at a time, loads into one of four registers
• Was: 8+8+8+8 = 32 wires• Now: 8 +2+1 = 11 wires
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Register Example: Above-Mirror Display
C
d0
d1
d2
d3e
i0
i0
i1
i2
i3
a0
a1
load
i1
2×4 8
8
8
8
8Dd
8x y
s1s0
8-bit4×1
load
load
load
load
reg0
reg1
reg2
reg3
T
A
I
M
1
0
0001010
1
1
0001010
Loaded on clock edge
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Shorthand notation
32 wires
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Shift Register
• Shift right– Move each bit one position right– Shift in 0 to leftmost bit
1 1 0 1 Register contentsbefore shift right
0 1 1 0
0
Register contentsafter shift right
E.g.: Do four right shifts on 1001, showing value after each shift
A: 1001 (original)
0100
0010
0001
0000
shr_in
• Implementation: Connect flip-flop output to next flip-flop’s input
14
Shift Register
• To allow register to either shift or maintain value– Control input shr: 0 means maintain value, 1 shift– Input shr_in: value to shift in
• May be 0, or 1
– Use 2x1 muxes• Note: Can easily design shift register that shifts left instead
1 02×1
D
Q
Q3
1 0
D
Q
Q2
1 0
D
Q
Q1
1 0
D
Q
Q0
shr=
11 02×1
D
Q
Q3
shr
shr_in
shrshr_in
1 0
D
Q
Q2
1 0
D
Q
Q1 (b)
(c)
(a)
1 0
D
Q
Q0
Q3 Q2 Q1 Q0
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Rotate Register
• Rotate right: Like shift right, but leftmost bit comes from rightmost bit
1 1 0 1
1 1 1 0
Register contentsbefore rotate right
Register contentsafter rotate right
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Shift Register Example: Above-Mirror Display
• Earlier example: 8 +2+1 = 11 wires from car’s computer to above-mirror display’s four registers– Better than 32 wires,
but 11 still a lot – want fewer for smaller wire bundles
• Use shift registers– Wires: 1+2+1=4– Computer sends one
value at a time, one bit per clock cycle
C
d0
d1
d2
d3e
i0
i0
i1
i2
i3
a0
a1
load
i1
2×4
From
the c
ar's
cent
ralcom
puter
8
8
8
8
8Dd
8
x y
s1 s0
8-bit4×1
To th
e a
bove
mirro
r disp
lay
load
load
load
load
reg0
reg1
reg2
reg3
T
A
I
M
11 w
ires
c
d0
d1
d2
d3e
i0
i0s1 s0
x y
i1
i2
i3
a0
a1
shift
i1
2×48
8
8
8Dd
8
4×1
shrshr_in
shrshr_in
shrshr_in
shrshr_in
reg0
reg1
reg2
reg3
T
A
I
M
Note: this line is 1 bit, rather than 8 bits like before
17
Multifunction (Universal) Registers
shr_inshl_in
3 2 1
I3
0
D
Q
Q3
Q2 Q1 Q0Q3
I2 I1 I0I3
Q2
3 2 1
I2
0
D
Q
Q1
3 2 1
I1
0
D
Q
Q0
3 2 1
I0
0
D
Q
shl_inshr_ins1s0
(a) (b)
Operation
Maintain present value
Parallel load
Shift right
Shift left
s0
0
1
0
1
s1
0
0
1
1
• Many registers have multiple functions– Load, shift, clear (load all 0s)– And retain present value, of course
• Easily designed using muxes– Just connect each mux input to achieve
desired function
18
Maintain valueShift leftShift rightShift rightParallel loadParallel loadParallel loadParallel load
NoteOperations0s1
01110000
01001111
OutputsInputs
01010101
00110011
00001111
ld shr shl
Truth table for combinational circuit
Multifunction Registers with Separate Control Inputs
Maintain present valueShift leftShift right
Shift right – shr has priority over shlParallel load
Parallel load – ld has priorityParallel load – ld has priorityParallel load – ld has priority
Operationshlshrld
00001111
00110011
01010101
Q2 Q1 Q0Q3
Q2 Q1 Q0Q3
I2 I1 I0I3
I2 I1 I0I3
s1shr_in
shr_in
shr
shl
ld
s0shl_in
shl_in
?combi-nationalcircuit
s1 = ld’*shr’*shl + ld’*shr*shl’ + ld’*shr*shl
s0 = ld’*shr’*shl + ld
19
Register Operation Table
• Register operations typically shown using compact version of table– X means same operation whether value is 0 or 1
• One X expands to two rows• Two Xs expand to four rows
– Put highest priority control input on left to make reduced table simple
Maintain valueShift left
NoteOperations0s1
01
01
OutputsInputs
01
00
00
Shift rightShift right
11
00
01
11
00
Parallel loadParallel loadParallel loadParallel load
0000
1111
0101
0011
1111
ld shr shl
MaintainvalueShift left
Operationld shr shl
01
00
00
Parallel loadXX1Shift rightX10
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Register Design Process
• Can design register with desired operations using simple four-step process
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Register Design Example
• Desired register operations– Synchronous clear, synchronous
set, load, shift left
Step 1: Determine mux size
5 operations: above, plus maintain present value (don’t forget this one!) Use 8x1 mux
Step 2: Create mux operation table
Step 3: Connect mux inputs
Step 4: Map control lines
OperationMaintain present valueParallel loadShift leftSynchronous clearSynchronous setMaintain present valueMaintain present valueMaintain present value
s001010101
s100110011
s200001111
D
Q
Qn
7 6 3 2 1
Id
05 4
1 0
s2s1s0
fromQn-1
Operation
Maintain present valueShift leftParallel load
Set to all 1sClear to all 0s
s0
001
01
s1
010
01
s2
000
10
shl
01X
XX
ld
001
XX
clr
000
01
Inputs Outputs
set
000
1X
s2 = clr’*sets1 = clr’*set’*ld’*shl + clrs0 = clr’*set’*ld + clr
22
Register Design Example
Step 4: Map control linesOperation
Maintain present valueShift leftParallel load
Set to all 1sClear to all 0s
s0
001
01
s1
010
01
s2
000
10
shl
01X
XX
ld
001
XX
clr
000
01
Inputs Outputs
set
000
1X
s2 = clr’*sets1 = clr’*set’*ld’*shl + clrs0 = clr’*set’*ld + clr
Q2 Q1 Q0Q3
Q2 Q1 Q0Q3
I2 I1 I0I3
I2 I1 I0I3
s1ld
shl
s0shl_in
shl_incombi-nationalcircuitset
clr
s2
23
Serial Transfer
• A digital system is in the serial mode when information is processed one bit at a time
• Serial transfer of information from A to B
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Remember 4-bit Parallel Adder Circuit?
• For small digital circuits, serial addition requires less equipment
4-bit parallel adder
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Serial Addition
• Slower compared to parallel addition, but uses less equipment
• Use shift registers– A, B hold data– Use a full adder– Carry out stored in
a D flip-flop
• PA uses more FAs compared to SA
• PA is a combinational circuit, SA is sequential
Which register holds the sum?
26
Serial Adder using Design Procedure
Present State Inputs Next State Output Flip-Flop inputs
Q (carry) x y Q (carry) S J0 K0
0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1
• J0=xy • K0=x’y’= (x+y)’ • S=x y Q
0 x0 x0 x1 xx 1x 0x 0x 0
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Serial 4-bit Parallel Adder Circuit
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Readings
• Chapter 6– Sections 6.1 – 6.2
