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COUNTERS

CountersTransition TablesMoore OutputsCounter Timing

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General Sequential Systems

D QD Q

CurrentStateState

MemoryInputForming

Logic

NextState

CLK

NextState 01 10 11 00 01

CurrentState 00 01 10 11 00

The current stateloads the nextstate values inresponse to the clock edge.

IFL reacts after some gate delaysto produce a newnext state.

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Transition Table for 2-Bit Counter

CurrentState

NextState

00 0101 1010 1111 00

It is the truth table for the input forming logic…

It describes what the next state values are as a functionof the current state(clock is assumed)

Q1 Q0 N1 N0

0 0 0 10 1 1 01 0 1 11 1 0 0

CurrentState

NextState

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Q1

Q0 0 1

0 1 11 0 0

Implementation of 2-Bit Counter

Q0

Q1D Q

D Q

CLK

CLK

N1

N0

N0 =Q0’

Q1

Q0 0 1

0 0 11 1 0

N1 =Q1⊕Q0

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Example 2 – A Gray Code Counter

Q1 Q0 N1 N0

0 0 0 10 1 1 11 1 1 01 0 0 0

Ordering of TT rowschosen to make it easierto see the count pattern.

It doesn’t change result.

N1= Q0

N0 = Q1’

Q1D Q

D Q Q0

CLK

CLK

N1

N0

Q1

Q0 0 1

0 0 01 1 1

Q1

Q0 0 1

0 1 01 1 0

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Example 3 – Not All Count Values Used

Desired count sequence = 00 – 01 – 11 - 00 …

Q1 Q0 N1 N0

0 0 0 10 1 1 11 1 0 01 0 ? ?

What should next state for 10 be?

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Example 3 – Not All Count Values UsedQ1 Q0 N1 N0

0 0 0 10 1 1 01 0 0 01 1 X X

Do the normal KMap w/don’t cares minimization…

Q1

Q0 0 1

0 0 01 1 X

N1 = Q0

Q1

Q0 0 1

0 1 01 0 X

N0 = Q0’•Q1’

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Example 4 – A Ring CounterDesired count sequence = 001 – 010 – 100 - 001 …

Q2 Q1 Q0 N2 N1 N0

0 0 0 X X X0 0 1 0 1 00 1 0 1 0 00 1 1 X X X1 0 0 0 0 11 0 1 X X x1 1 0 X X X1 1 1 X X X

Doing KMaps leads to: N2 = Q1 N1 = Q0 N0 = Q2

No big surprise here!!!!!

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Example 4 – A Ring Counter

D Q

D Q

D Q

Q0

Q2

Q1

CLK

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General Counter Design Procedure

• Write transition table for counter– Use X’s as appropriate

• Reduce each Nx variable to an equation• Implement input forming logic (IFL) using

gates• Draw schematic using FF’s + IFL

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Counters With Alternative FF’s

CurrentState

InputForming

Logic

NextState

StateMemory

T QT QT Q

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Excitation Table for T Flip Flop

Q Q+ T

0 0 00 1 11 0 11 1 0

T Q Q+

0 0 00 1 11 0 11 1 0

Rearranging rows and/or columns…

Tells how inputs affect output Tells what input to applyto achieve desiredoutput transition

In the end, they are the same table, just rearranged…

Transition Table Excitation Table

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TFF Counter Design Using Augmented Transition Table

Q2 Q1 Q0 N2 N1 N0 T2 T1 T0

0 0 0 0 0 1 0 0 10 0 1 0 1 0 0 1 10 1 0 0 1 1 0 0 10 1 1 1 0 0 1 1 11 0 0 1 0 1 0 0 11 0 1 1 1 0 0 1 11 1 0 1 1 1 0 0 11 1 1 0 0 0 1 1 1

TFFInputs

CurrentState State

Next

Next state values Inputs to apply to achieve desired next state

T2 = Q1•Q0T1 = Q0T0 = ‘1’

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TFF Counter Design

‘1’

CLK

Q1

CLK

T Q

T Q

T Q

CLK

Q2

Q0

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Excitation Table for JK Flip Flop

Rearranging rows and/or columns…

Tells how inputs affect output

Tells what inputs to applyto achieve desiredoutput transition

Do you see why the X’s?

J K Q Q+

0 0 0 00 0 1 10 1 0 00 1 1 01 0 0 11 0 1 11 1 0 11 1 1 0

Q Q+ J K

0 0 0 X0 1 1 X1 0 X 11 1 X 0

In the end, they are the same table, just rearranged…

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JKFF Gray Code Counter Design

Next state values Inputs to apply to achieve desired next state

J2 = Q1Q0’K2 = Q1’Q0’

J1 = Q2’Q0K1 = Q2Q0

J0 = Q2Q1 + Q2’Q1’ = K0’K0 = Q2’Q1 + Q2Q1’ = Q2 © Q1

Q2 Q1 Q0 N2 N1 N0 J2 K2 J1 K1 J0 K0

0 0 0 0 0 1 0 X 0 X 1 X0 0 1 0 1 1 0 X 1 X X 00 1 0 1 1 0 1 X X 0 0 X0 1 1 0 1 0 0 X X 0 X 11 0 0 0 0 0 X 1 0 X 0 X1 0 1 1 0 0 X 0 0 X X 11 1 0 1 1 1 X 0 X 0 1 X1 1 1 1 0 1 X 0 X 1 X 0

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General Counter Design Procedure

• Write transition table for counter– Use X’s as appropriate– If not DFF’s, augment table

• Reduce each FF input variable to equation• Implement IFL with gates• Draw schematic using FF’s + gates

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Counters With Outputs

Outputs

D QD Q

CurrentState

InputForming

Logic

NextState

StateMemory

OutputForming

Logic

Outputs = f(CurrentState)

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Counters With Outputs

Q2 Q1 Q0 Z

0 0 0 10 0 1 00 1 0 00 1 1 11 0 0 01 0 1 01 1 0 11 1 1 0

Z=1 when count={0,3,6}

Z is called a Moore or static output. It is a function only of the current state

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Combined Transition TableQ2 Q1 Q0 N2 N1 N0 Z

0 0 0 0 0 1 10 0 1 0 1 0 00 1 0 0 1 1 00 1 1 1 0 0 11 0 0 1 0 1 01 0 1 1 1 0 01 1 0 1 1 1 11 1 1 0 0 0 0

Current state Next state Output

Z = Q2’Q1’Q0’ + Q2’Q1Q0 + Q2Q1Q0’

(implement OFL with gates)

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Counter Delay Characteristics

Q0

Q1D Q

D Q

CLK

CLK

N1

N0

TClockPeriod >= tCLK-Q + tIFL + tsetup

CLK

Next State(N’s) 01 10

CurrentState (Q’s) 00 01 10

tCLK-Q

tIFL

tsetup

TClockPeriod

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Counter Delay Example

• tCLK-Q = 1ns

• tIFL = 7ns

• tsetup = 2ns

• TClockPeriod >= 10ns ( 10 x 10-9 sec)• ClockRate <= 100MHz (100 x 106 Hz)

– Rate = 1/Period

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Next State and Output Timings

CLK

Z

CurrentState 010 011 100

tCLK-Q

tOFL

tCLK-Q

tOFL

More outputs appear tCLK-Q + tOFL

after the clock edge.

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Counters and Timing

• The count sequence affects the size of IFL• The size of the IFL affects tIFL

• tIFL affects TClockPeriod

• Choosing binary counts is not always fastest or smallest

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Example Problem

• Design a 3-bit binary counter• The Z output is TRUE iff count value is

even• The Y output is TRUE iff count value is

multiple of 3