Counters and Shift Rgisters

8/10/2019 Counters and Shift Rgisters

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Counters & Shift Registers


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2

Lecture 13: Sequential LogicCounters and Registers

Counters

Introduction: Counters

Asynchronous (Ripple) Counters

Asynchronous Counters with MOD number < 2n

Asynchronous Down Counters

Cascading Asynchronous Counters


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3

Lecture 13: Sequential LogicCounters and Registers

Synchronous (Parallel) Counters

Up/Down Synchronous Counters

Designing Synchronous Counters

Decoding A Counter

Counters with Parallel Load


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Introduction: Counters 6

Introduction: Counters

Countersare circuits that cycle through a specifiednumber of states.

Two types of counters:

synchronous (parallel) counters

asynchronous (ripple) counters

Ripple counters allow some flip-flop outputs to be

used as a source of clock for other flip-flops.

Synchronous counters apply the same clock to all

flip-flops.


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Asynchronous (Ripple) Counters 7


Asynchronous counters: the flip-flops do not changestates at exactly the same time as they do not have acommon clock pulse.

Also known as ripple counters, as the input clockpulse ripples through the counter cumulative

delay is a drawback.

nflip-flopsa MOD (modulus) 2ncounter. (Note: A

MOD-xcounter cycles throughxstates.)

Output of the last flip-flop (MSB) divides the input

clock frequency by the MOD number of the counter,hence a counter is also a frequency divider.


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Example: 2-bit ripple binary counter. Output of one flip-flop is connected to the clock input

of the next more-significant flip-flop.

K

J

K

J

HIGH

Q0 Q1

Q0

FF1FF0

CLK CC

Timing diagram

0001101100 ...

4321CLK

Q0

Q0

Q1

1 1

1 1

0

0 0

0 0

0


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Example: 3-bit ripple binary counter.

K

J

K

JQ0 Q1

Q0

FF1FF0

CC

K

J

Q1C

FF2

Q2

CLK

HIGH

4321CLK

Q0

Q1

1 1

1 1

0

0 0

0 0

0

8765

1 10 0

1 10 0

Q2 0 00 0 1 1 11 0

Recycles back to 0


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Propagation delays in an asynchronous (ripple-clocked) binary counter.

If the accumulated delay is greater than the clockpulse, some counter states may be misrepresented!

4321CLK

Q0

Q1

Q2

tPLH

(CLK to Q0)

tPHL

(CLK to Q0)

tPLH

(Q0 toQ1)

tPHL

(CLK to Q0)

tPHL

(Q0 toQ1)

tPLH

(Q1 toQ2)


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Asynchronous Counters withMOD number < 2^n

12

Asyn. Counters with MOD no. < 2n

States may be skipped resulting in a truncatedsequence.

Technique: force counter to recycle before going

through all of the statesin the binary sequence.

Example: Given the following circuit, determine thecounting sequence (and hence the modulus no.)

K

JQ

QCLK

CLRK

JQ

QCLK

CLRK

JQ

QCLK

CLR

C B A

B

C

All J, Kinputs

are 1

(HIGH).


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13


Example (contd):

K

JQ

Q

CLK

CLRK

JQ

Q

CLK

CLRK

JQ

Q

CLK

CLR

C B A

BC

All J, K

inputs

are 1

(HIGH).

A

B

1 2

C

NAND

Output10

3 4 5 6 7 8 9 10 11 12Clock MOD-6 counter

produced by

clearing (a MOD-8binary counter)

when count of six

(110) occurs.


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14


Example (contd): Counting sequence of circuit (inCBA order).

A

B

CNAND

Output10

1 2 3 4 5 6 7 8 9 10 11 12

Clock

111 000001

110

101

100

010

011

Temporary

state

Counter is a MOD-6counter.

0

0

0

1

0

0

0

1

0

1

1

0

0

0

1

1

0

1

0

0

0

1

0

0


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15


Exercise:How to construct an asynchronous MOD-5counter? MOD-7 counter? MOD-12 counter?

Question:The following is a MOD-? counter?

K

JQ

Q

CLR

C B A

C

DEF

All J= K = 1.

K

JQ

Q

CLR

K

JQ

Q

CLR

K

JQ

Q

CLR

K

JQ

Q

CLR

K

JQ

Q

CLR

DEF


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16


Decade counters(or BCD counters) are counterswith 10 states (modulus-10) in their sequence.They are commonly used in daily life (e.g.: utilitymeters, odometers, etc.).

Design an asynchronous decade counter.

D

CLK

HIGH

K

J

C

CLR

Q

K

J

C

CLR

QC

K

J

C

CLR

QB

K

J

C

CLR

QA

(A.C)'


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Asynchronous Down Counters 19

Asynchronous Down Counters

Example: A 3-bit binary (MOD-8) down counter.

4321CLK

Q0

Q1

1 1

1 0

0

0 1

0 0

0

8765

1 10 0

1 01 0

Q2 1 10 1 1 0 00 0

001

000111

010

011

100

110

101

1

K

J

K

JQ1Q0

CC

K

J

C

Q2

CLK

Q

Q'

Q

Q'

Q

Q'

Q

Q'


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Cascading AsynchronousCounters

20


Larger asynchronous (ripple) counter can beconstructed by cascading smaller ripple counters.

Connect last-stage output of one counter to theclock input of next counter so as to achieve higher-modulus operation.

Example: A modulus-32 ripple counter constructedfrom a modulus-4 counter and a modulus-8 counter.

K

J

K

J

Q1Q0

CCCLK

Q

Q'

Q

Q'

Q

Q'K

J

K

J

Q3Q2

CC

K

J

C

Q4

Q

Q'

Q

Q'

Q

Q'

Q

Q'

Modulus-4 counter Modulus-8 counter


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21


Example: A 6-bit binary counter (counts from 0 to63) constructed from two 3-bit counters.

3-bitbinary counter 3-bitbinary counterCountpulse

A0 A1 A2 A3 A4 A5

A5 A4 A3 A2 A1 A0

0 0 0 0 0 0

0 0 0 0 0 1

0 0 0 : : :

0 0 0 1 1 1

0 0 1 0 0 00 0 1 0 0 1

: : : : : :


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22


If counter is a not a binary counter, requiresadditional output.

Example: A modulus-100 counter using two decade

counters.

CLK

Decade

counter

Q3Q2Q1Q0C

CTEN

TC

1 Decade

counter

Q3Q2Q1Q0C

CTEN

TC

freq

freq/10freq/100

TC = 1 when counter recycles to 0000


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Synchronous (Parallel) Counters 23


Synchronous (parallel) counters: the flip-flops areclocked at the same time by a common clock pulse.

We can design these counters using the sequential

logic design process (covered in Lecture #12).

Example: 2-bit synchronous binary counter (using Tflip-flops, or JK flip-flops with identical J,K inputs).

Present Next Flip-flop

state state inputs

A 1 A 0 A 1+

A 0+

TA 1 TA 0

0 0 0 1 0 10 1 1 0 1 1

1 0 1 1 0 11 1 0 0 1 1

0100

1011


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Example: 2-bit synchronous binary counter (using Tflip-flops, or JK flip-flops with identical J,K inputs).

Present Next Flip-flop

state state inputs

A 1 A 0 A 1+

A 0+

TA 1 TA 0

0 0 0 1 0 1

0 1 1 0 1 1

1 0 1 1 0 11 1 0 0 1 1

TA1=A0

TA0= 1

1

K

J

K

JA 1A 0

CC

CLK

Q

Q'

Q

Q'

Q

Q'


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Example: 3-bit synchronous binary counter (using Tflip-flops, or JK flip-flops with identical J, K inputs).

Present Next Flip-flopstate state inputs

A 2 A 1 A 0 A 2+

A 1+

A 0+

TA 2 TA 1 TA 0

0 0 0 0 0 1 0 0 1

0 0 1 0 1 0 0 1 10 1 0 0 1 1 0 0 10 1 1 1 0 0 1 1 11 0 0 1 0 1 0 0 11 0 1 1 1 0 0 1 11 1 0 1 1 1 0 0 11 1 1 0 0 0 1 1 1

TA2= A 1.A 0

A2

A1

A0

1

1

TA 1= A 0 TA 0= 1

A2

A1

A0

1

1 1

1

A2

A1

A0

1 1 1

11 1 1

1


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Example: 3-bit synchronous binary counter (contd).TA2= A1.A0 TA1= A0 TA0= 1

1

A 2

CP

A 1 A 0

K

Q

J K

Q

J K

Q

J


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Note that in a binary counter, the n

th

bit (shownunderlined) is always complemented whenever

0111110000

or 1111100000

Hence, Xnis complemented wheneverXn-1Xn-2... X1X0= 1111.

As a result, if T flip-flops are used, then

TXn= Xn-1 . Xn-2 .... .X1 .X0


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Example: 4-bit synchronous binary counter.

TA3=A2.A1.A0

TA2=A1.A0

TA1=A0

TA0= 1

1

K

J

K

JA 1A 0

CC

CLK

Q

Q'

Q

Q'

Q

Q'K

JA 2

C

Q

Q'K

JA 3

C

Q

Q'

A 1.A 0 A2.A 1.A 0


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Example: Synchronous decade/BCD counter.

Clock pulse Q3 Q2 Q1 Q0

Initially 0 0 0 01 0 0 0 12 0 0 1 03 0 0 1 1

4 0 1 0 05 0 1 0 16 0 1 1 07 0 1 1 18 1 0 0 09 1 0 0 1

10 (recycle) 0 0 0 0

T0= 1

T1= Q3'.Q0

T2= Q1.Q0

T3= Q2.Q1.Q0+ Q3.Q0


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Example: Synchronous decade/BCD counter(contd).

T0= 1

T1= Q3'.Q0

T2= Q1.Q0T3= Q2.Q1.Q0+ Q3.Q0

1 Q1

Q0

CLK

T

CQ

Q'

Q

Q'

Q2 Q3T

CQ

Q'

Q

Q'

T

CQ

Q'

Q

Q'

T

CQ

Q'

Q

Q'


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Up/Down Synchronous Counters 31


Up/down synchronous counter: a bidirectionalcounter that is capable of counting either up or

down.

An input (control) line Up/Down(or simply Up)

specifies the direction of counting. Up/Down= 1Count upward

Up/Down= 0Count downward


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Example: A 3-bit up/down synchronous binarycounter.

Clock pulse Up Q2 Q1 Q0 Down

0 0 0 01 0 0 12 0 1 0

3 0 1 14 1 0 05 1 0 16 1 1 07 1 1 1

TQ0= 1

TQ1= (Q0.Up) + (Q0'.Up' )

TQ2= ( Q0.Q1.Up )+ (Q0'. Q1'. Up' )

Up counter

TQ0= 1

TQ1= Q0

TQ2= Q0.Q1

Down counter

TQ0= 1

TQ1= Q0

TQ2= Q0.Q1


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Example: A 3-bit up/down synchronous binarycounter (contd).

TQ0= 1

TQ1= (Q0.Up) + (Q0'.Up' )

TQ2= ( Q0.Q1.Up )+ (Q0'. Q1'. Up' )

1

Q1Q0

CLK

T

C

Q

Q'

Q

Q'

T

C

Q

Q'

Q

Q'

T

C

Q

Q'

Q

Q'

Up

Q2


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Designing Synchronous Counters 34


Covered in Lecture #12.

Example: A 3-bit Gray code

counter (using JK flip-flops).

100 000 001

101

111

110

011

010

Present Next Flip-flopstate state inputs

Q2Q1 Q0 Q2+

Q1+

Q0+

JQ2 KQ2 JQ1 KQ1 JQ0 KQ0

0 0 0 0 0 1 0 X 0 X 1 X0 0 1 0 1 1 0 X 1 X X 0

0 1 0 1 1 0 1 X X 0 0 X0 1 1 0 1 0 0 X X 0 X 11 0 0 0 0 0 X 1 0 X 0 X1 0 1 1 0 0 X 0 0 X X 11 1 0 1 1 1 X 0 X 0 1 X1 1 1 1 0 1 X 0 X 1 X 0


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Designing Synchronous Counters 35


3-bit Gray code counter: flip-flop inputs.

0

1

00 01 11 10Q2Q1Q0

X X X X

1

JQ2= Q1.Q0'

0

1

00 01 11 10Q2Q1Q0

X X X X1

KQ2= Q1'.Q0'

0

1

00 01 11 10Q2Q1Q0

X X

X X1

JQ1= Q2'.Q0

0

1

00 01 11 10Q2Q1Q0

X XX X

1

KQ1= Q2.Q0

0

1

00 01 11 10Q2Q1Q0

XX

XX1

JQ0= Q2.Q1+ Q2'.Q1'

= (Q2 Q1)'

1

0

1

00 01 11 10Q2Q1Q0

XXXX 1

1

KQ0= Q2.Q1'+ Q2'.Q1

= Q2 Q1


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Decoding A Counter 37

Decoding A Counter

Decoding a counterinvolves determining which statein the sequence the counter is in.

Differentiate between active-HIGHand active-LOWdecoding.

Active-HIGH decoding: output HIGH if the counter isin the state concerned.

Active-LOW decoding: output LOW if the counter isin the state concerned.


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Decoding A Counter 39

Decoding A Counter

Example: To detect that a MOD-8 counter is in state0 (000) or state 1 (001).

A '

B '

1 2 3 4 5 6 7 8 9Clock

HIGH only on

count of ABC= 000

or ABC= 001

100

Example: To detect that a MOD-8 counter is in the

odd states (states 1, 3, 5 or 7), simply use C.

C

1 2 3 4 5 6 7 8 9Clock

HIGH only on count

of odd states

100

A'B 'C'

A 'B 'C


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Counters with Parallel Load 40


Counters could be augmented with parallel loadcapability for the following purposes:

To start at a different state

To count a different sequence

As more sophisticated register with increment/decrement

functionality.


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Counters with Parallel Load 41


Different ways of getting a MOD-6 counter:

Count = 1

Load = 0

CPI4 I3 I2 I1

Count = 1

Clear = 1

CP

A 4 A 3 A 2 A 1

Inputs = 0

Load

(a) Binary states 0,1,2,3,4,5.

I4 I3 I2 I1

A 4 A 3 A 2 A 1

Inputs have no effect

Clear

(b) Binary states 0,1,2,3,4,5.

I4 I3 I2 I1

Count = 1Clear = 1

CP

A 4 A 3 A 2 A 1

0 0 1 1

Load

(d) Binary states 3,4,5,6,7,8.

I4 I3 I2 I1

Count = 1Clear = 1

CP

A 4 A 3 A 2 A 1

1 0 1 0

Load

Carry-out

(c) Binary states 10,11,12,13,14,15.


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Introduction: Registers 43

Introduction: Registers

An n-bit registerhas a group of nflip-flops and somelogic gates and is capable of storing nbits of

information.

The flip-flops store the information while the gates

control when and how new information is transferredinto the register.

Some functions of register:

retrieve data from register

store/load new data into register (serial or parallel) shift the data within register (left or right)


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Simple Registers 44

Simple Registers

No external gates.

Example: A 4-bit register. A new 4-bit data is loadedevery clock cycle.

A 3

CP

A 1 A 0

D

Q

D

Q Q

D

A 2

D

Q

I3 I1 I0I2


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Registers With Parallel Load 45

Registers With Parallel Load

Instead of loading the register at every clock pulse,we may want to control when to load.

Loadinga register: transfer new information into the

register. Requires a loadcontrol input.

Parallel loading: all bits are loaded simultaneously.


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Shift Registers 50

Shift Registers

Another function of a register, besides storage, is toprovide for data movements.

Each stage(flip-flop) in a shift register represents

one bit of storage, and the shifting capability of a

register permits the movement of data from stage tostage within the register, or into or out of the register

upon application of clock pulses.


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Shift Registers 51

Shift Registers

Basic data movement in shift registers (four bits areused for illustration).

Data in Data out

(a) Serial in/shift right/serial out

Data inData out

(b) Serial in/shift left/serial out

Data in

Data out

(c) Parallel in/serial out

Data out

Data in

(d) Serial in/parallel outData out

Data in

(e) Parallel in /

parallel out

(f) Rotate right (g) Rotate left


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Serial In/Serial Out Shift Registers 52

Serial In/Serial Out Shift Registers

Accepts data seriallyone bit at a timeand alsoproduces output serially.

Q0

CLK

D

C

QQ1 Q2 Q3Serial data

input

Serial data

outputD

C

Q D

C

Q D

C

Q


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Serial In/Parallel Out Shift

Registers

55

Serial In/Parallel Out Shift Registers

Accepts data serially.

Outputs of all stages are available simultaneously.

Q0

CLK

D

C

Q

Q1

D

C

Q

Q2

D

C

Q

Q3

D

C

QData input

D

CCLK

Data input

Q0Q1Q2Q3

SRG 4

Logic symbol


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Parallel In/Serial Out Shift

Registers

56

Parallel In/Serial Out Shift Registers

Bits are entered simultaneously, but output is serial.

D0

CLK

D

C

Q

D1

D

C

Q

D2

D

C

Q

D3

D

C

Q

Data input

Q0 Q1 Q2 Q3

Serial

data

out

SHIFT/LOAD

SHIFT.Q0+ SHIFT'.D1


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Parallel In/Serial Out Shift

Registers

57

Parallel In/Serial Out Shift Registers

Bits are entered simultaneously, but output is serial.

Logic symbol

CCLK

SHIFT/LOAD

D0D1D2D3

SRG 4Serial data out

Data in


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Bidirectional Shift Registers 59

Bidirectional Shift Registers

Data can be shifted either left or right, using a controlline RIGHT/LEFT(or simply RIGHT) to indicate thedirection.

CLK

D

C

Q D

C

Q D

C

Q D

C

Q

Q0

Q1 Q2Q

3

RIGHT/LEFT

Serial

data in

RIGHT.Q0+

RIGHT'.Q2

1 2 3 4 65 7 8


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Bidirectional Shift Registers 61

Bidirectional Shift Registers

4-bit bidirectional shift register with parallel load.

Mode Control

s1 s0 Register Operation

0 0 No change

0 1 Shift right1 0 Shift left1 1 Parallel load


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Shift Register Counters 64

Shift Register Counters

Shift register counter: a shift register with the serial

output connected back to the serial input.

They are classified as counters because they give a

specified sequence of states.

Two common types: the Johnson counterand theRing counter.


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Ring Counters 65

Ring Counters

One flip-flop (stage) for each state in the sequence.

The output of the last stage is connected to the D

input of the first stage.

An n-bit ring counter cycles through nstates.

No decoding gates are required, as there is an output

that corresponds to every state the counter is in.

i C


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Ring Counters 66

Ring Counters

Example: A 6-bit (MOD-6) ring counter.

CLK

Q0D Q D Q D Q D Q D Q D Q

Q1 Q2 Q3 Q4 Q5

CLR

PRE

Clock Q0 Q1 Q2 Q3 Q4 Q5

0 1 0 0 0 0 01 0 1 0 0 0 0

2 0 0 1 0 0 03 0 0 0 1 0 04 0 0 0 0 1 05 0 0 0 0 0 1

100000

010000

001000

000100

000010

000001

J h C


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Johnson Counters 67

Johnson Counters

The complement of the output of the last stage is

connected back to the D input of the first stage.

Also called the twisted-ring counter.

Require fewer flip-flops than ring counters but more

flip-flops than binary counters.

An n-bit Johnson counter cycles through 2nstates.

Require more decoding circuitry than ring counter

but less than binary counters.

J h C


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J h C t 68

Johnson Counters

Example: A 4-bit (MOD-8) Johnson counter.

Clock Q0 Q1 Q2 Q3

0 0 0 0 01 1 0 0 02 1 1 0 0

3 1 1 1 04 1 1 1 15 0 1 1 16 0 0 1 17 0 0 0 1

CLK

Q0D Q D Q D Q D Q

Q1 Q2

Q3'

CLR

Q'

0000

0001

0011

0111

1111

1110

1100

1000

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Counters and Shift Rgisters