as a buffer storage, are included to provide an adequateinput-charge transfer during the clock period [5, 6]

(b) two additional feedback capacitors y\ = yt areplaced (for the even and the odd phase, respectively) todeliver the transferred charge after a proper half-perioddelay

(c) the parasitic insensitive toggle switching scheme [6]is chosen for the feedback capacitors y\, y2i, yi a n d ^31 ina way to provide the correct sign of the transferred charges

(d) two cascaded capacitors, one unit each, are putaround the OA to ensure a continuous feedback duringthe dead zones of the nonoverlapping clocks, according tothe recommendations in Reference 6;

(e) a set of clock signals (Fig. 8) is required to drive theswitches.

Following the numerical example in this paper and thedesign technique in Reference 4, all the capacitors ' / areevaluated. So the filter is implemented with one multi-plexed OA, 54 switches and 20 capacitors. The capacitorratio CmaJCmin is 25.32 and the total silicon area isYJ C{ — 33.54 units. The comparison made between thisimplementation and the same filter, based on a proposedsingle-OA biquad (Fig. 5) indicates the impracticability ofthe multiplexed OA technique used along with the state-space design method [4], if any suitable adaptions of themethod itself are not proposed.

CorrespondenceCORRELATION ALGORITHMS,CIRCUITS AND MEASUREMENTAPPLICATIONS

With reference to Paper 4299G \IEE Proc. G, 1986, 133,(1), pp. 58-74] I would like to make the followingcomments:

The equation for C2(a) on page 59 is incorrect andshould be written as

(•772

C2(a) = a(t) *b(-t)= a(t)b(t - a) dtJ-772

Eqn. 5 on the same page reads:

Tryx(a) = y(t)x(t + a) dt = y(t) * x(-t)J

The fact that the right-hand side is not y( — t) * x(t) may beconfusing. This is because the author has omitted to saythat a positive value for the correlation function argumentsignifies a time delay. This also explains why otherderivations (e.g. eqns. 13, 14, 17 etc.) may at first seem tobe in error.

12th August 1986 D.C. McLERNON

Department of Electrical and Electronic EngineeringPolytechnic of the South BankBorough RoadLondon SE1 OAAUnited Kingdom

4902G

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1EE PROCEEDINGS, Vol. 133, Pt. G, No. 5, OCTOBER 1986 255