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Copyright 1995-1999 SCRA
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VHDL Testbenches And Basic WAVES Topics
RASSP Education & FacilitationModule 61
Version 3.00 Copyright 1998 University of Virginia
This module was created under Air Force Contract #95-C-0220.
Copyright 1995-1999 SCRA
All rights reserved. This information is copyrighted by the SCRA, through its Advanced Technology Institute, and may only be used for non-commercial educational purposes. Any other use of this information without the express written permission of the ATI is prohibited. Certain parts of this work belong to other copyright holders and are used with their permission. All information contained herein may be duplicated for non-commercial educational use provided this copyright notice is included. No warranty of any kind is provided or implied, nor is any liability accepted regardless of use.
The United States Government holds “Unlimited Rights” in all data contained herein under Contract F33615-94-C-1457. Such data may be liberally reproduced and disseminated by the Government, in whole or in part, without restriction except as follows: Certain parts of this work belong to other copyright holders and are used with their permission;This information contained herein may be duplicated only for non-commercial educational use. Any vehicle, in which part or all of this data is incorporated into, shall carry this legend.
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Module Goals
Introduce VHDL Testbenches Used To Verify And Test VHDL Designs
Introduce WAVES Basic Concepts WAVES Library And Functions WAVES Test Set Basic WAVES Examples
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Module Outline
Introduction Testbench Development Design Verification Challenges WAVES Concepts WAVES Constructor Library and Built-Ins WAVES External File WAVES Test Set Decoder Example Algorithmic Waveform Generator Example
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Introduction
Top Down Electronic Design Automation (EDA)
TestVectorSystem
HardwareTester
VHDL
ConceptModeling
SimulatableSpecification
SimulatedDesigns
SynthesizedImplementation
Test Vectors
Results
Test Vectors
Results
Test Vectors
Results
Test Signals
Results
Tools
Tools
Tools
Tools
GraphicalUserInterface(GUI)
USER
Support Environment (file exchange, libraries, etc.)
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Introduction (cont.)
The Role Of WAVES In Top Down EDA
WAVESTestbench
HardwareTester
VHDL
ConceptModeling
SimulatableSpecification
SimulatedDesigns
SynthesizedImplementation
Results
Test Vectors
Results
Test Vectors
Results
Test Signals
Results
Tools
Tools
Tools
Tools
GUIUSER
Support Environment (file exchange, libraries, etc.)
changeswith levelof design
Test Vectors
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Introduction (cont.)
WAVES History Original Standard IEEE 1029.1 - 1991
Waveform And Vector Exchange SpecificationFocus On Exchange Between Multiple EnvironmentsFocus On Automatic Test Equipment (ATE) SupportFocus On Documentation/Archive
Subset Of VHDL LanguagePoor Interface For VHDL Modeling & SimulationPrototype Package Implementation Inefficient, Overly
Complex
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Introduction (cont.)
WAVES ‘97 Scope Re-ballot Standard IEEE 1029.1 - 1996
Standard For VHDL Waveform And Vector Exchange (WAVES) to Support Design And Test Verification
Focus On Improved Interface Between WAVES And VHDL (1164 Support Libraries)
Focus On Supporting Design Verification For All Levels Of Modeling Abstraction
Focus On Improved Storage & Simulation EfficiencyFocus On Alignment With VHDL ‘93
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Module Outline
Introduction
Testbench Development Design Verification Challenges WAVES Concepts WAVES Constructor Library and Built-Ins WAVES External File WAVES Test Set Decoder Example Algorithmic Waveform Generator Example
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Testbench Development
Quality Testbench Is Essential For Adequate Design Verification
Testbench Methodologies Are Ad Hoc
100 Designers => 100 Approaches Complex And Difficult To Develop
Typically On The Order Of The Model To Be Tested Correct Model Behavior Verified “By-Observation”
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Testbench Development (cont.)
WAVES Testbench Consistent, Structured, Standard Testbench
Methodology Development Of Testbench Is Automated Correct Model Behavior Verified Automatically By
Simulator Well Documented Test Set Well Documented Testing Methodology
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Testbench Development (cont.)
Details Of A WAVES Testbench A VHDL Entity With No Ports A VHDL Architecture That Uses Structural And
Behavioral VHDL Descriptions Architecture of Testbench Contains Instantiation Of
Component Under Test, Test Vector File, Waveform Generator, Monitor Processes
Expected Output Signals Are Declared Expected Outputs Compared To Actual Output Signals Testbench Provides Environment Similar To Real
Hardware Testers (Input Stimulus, Comparison Of Output Values)
Different Test Vector Sets Can Be Used Without Modifying Testbench
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Testbench Development (cont.)
WAVES Testbench Diagram
VHDLModel
Instantiation
MonitorProcesses
WAVESWaveformGenerator
Input Stimulus
ErrorMessagesActual Response
ExpectedResponse WAVES
Test Vector Set
Testbench
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Module Outline
Introduction Testbench Development
Design Verification Challenges WAVES Concepts WAVES Constructor Library and Built-Ins WAVES External File WAVES Test Set Decoder Example Algorithmic Waveform Generator Example
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Testing Uninitialized Devices Device Powers up in an unknown state, has no reset
(example: Counter)
WAVES Match Mode Test
Design VerificationChallenges
Clock the device untilits outputs respondwith all zeros, thenapply the test vectorsto verify correctfunctionality
Model To Test Test method
Clock
COUNT
Counter withno reset orclear
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Testing Asynchronous Devices Synchronize With External Signal Before Applying Each
Test Vector
WAVES Handshake Mode Test
Design VerificationChallenges (cont.)
Test method
DMA Controller
Apply each test vector on the risingedge of the externalacknowledge to verify correct functionality
Model To Test
ACK
BUS
REQ
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Testing Devices With Multiple Asynchronous Functionality
Multiple WAVES Processes
Design VerificationChallenges (cont.)
Model Under Test Serial Data
Serial communicationinterface Every 200 ns pulse OE
for 20 ns and on the rising edge of data ready verify the state of the parallel output bus
Parallel DataData Ready
BUS
OE
Drive the clock at 50 MHz and supplytwo channels of serialdata into the model
Clock
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Design VerificationChallenges (cont.)
Testing Devices With Boundary Scan And/Or BIT/BIST
TDI
TMS
TCK
TRST
TD0Reset*ClockDRShiftDRUpdateDR Reset*
ClockIRShiftIRUpdateIR
SelectTCK
Shift (enable)
MUX
MUX FF
TAPController
Instruction Register
Instruction Decode
Shift Register
RTG Sig Anal
BoundaryRegister
Internal Scan
Bypass Register
Internal Logic
Device ID Register
Test Data Register
Device Inputs Device Outputs
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Module Outline
Introduction Testbench Development Design Verification Challenges
WAVES Concepts WAVES Constructor Library and Built-Ins WAVES External File WAVES Test Set Decoder Example Algorithmic Waveform Generator Example
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What Is WAVES ‘97?
Essentially Sequential VHDL, PLUS Built-in Data Types, Functions, Procedures External Pattern File Format Standard Library Of Constructors To Support 1164
Model Verification
Standard, Self-contained, Unambiguous Simulatable Specification Of The Intended Behavior Of A VHDL Model/Physical Hardware
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WAVES Concepts (cont.)
WAVES Libraries Based On 1164 Logic Levels
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WAVES Concepts
Only A Handful Of Basic Concepts Must Be Learned
Waveform Slice Events/Logic Values Frame Frame Sets/Pin Codes Frame Set Array
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WAVES Concepts (cont.)
Waveform The Set Of All Events Across All Signals For The Entire
Simulation Like Timing Diagram In A Data Book
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WAVES Concepts (cont.)
Slice A Time Partition Of The Waveform
Like A Tester Cycle Or Period
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WAVES Concepts (cont.)
Events/Logic Values The Scheduling Of A Logic Value On A Signal Of The
Waveform
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WAVES Concepts (cont.)
Frames Grouping Of Events Into Common Reusable Waveform
Shapes The Sequence Of Events On A Given Signal For A Given
Slice Like A Tester Format
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WAVES Concepts (cont.)
Frame Sets/Pin Codes A Set Of Frames, One For Each Legal Pin Code
Defines The Events That Are Scheduled When The Given Pin Code Is Applied To A Given Signal
Pin Codes Appear In The External Pattern File Pinsets Are Used To Group Pin Codes Together
Pinsets Declared In Waveform Generator File Used To Form A Bus of Signals Having The Same
Waveform Shape
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WAVES Concepts (cont.)
Frame Sets/Pin Codes (cont.)
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-- Declare the character codes that are legal in the external file. -- constant PIN_CODES : String := "X01ZWLH-";
-- -- This is the maximum number of events that may comprise a frame. -- A frame is a sequence of events for a given signal for a given -- slice of the waveform. Set this constant appropriately for -- your application. -- constant MAX_FRAME_EVENTS : positive := 3;
-- -- Declare the logic values system that will be used to place -- events on the waveform. -- subtype LOGIC_VALUE is Std_Ulogic;
-- -- Declare a vector of logic values that will be used to as the -- signal of vectors for the WAVES port list. -- subtype WAVES_LOGIC_VECTOR is Std_Ulogic_vector;
WAVES 1164 Declarations
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WAVES Concepts (cont.)
Frame Set Array Associates Frame Sets With Each Signal On The
Waveform Specifies The Actual Timing For Event Scheduling Like A Tester Timing Set
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Composition Of A WAVES Waveform
Waveform
Pins Signals
1
2
3
signal #1
signal #2
signal #3
Slices
External File
Pin & Pin Code Combinations
Slice Duration Times
Frame Set Array
Pin & Pin Code Combinations
Event Time Values
Frame Set(s)
Frame(s)
Event Time DesignatorsLogic Levels
Framet1 t21
0 70ns 140ns
200ns
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List of Pin Codes: a Pattern a Vector one line in an External File (File Slice)
WAVES Waveform As A Set Of Pin Code Lists
UUTPins
Slice
Sequence of Slices
Set of Lists of Pin Codes = A Waveform
Pin Code
(Each pin code refers to a frame selected from aparticularframe set)
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Module Outline
Introduction Testbench Development Design Verification Challenges WAVES Concepts
WAVES Constructor Library and Built-Ins WAVES External File WAVES Test Set Decoder Example Algorithmic Waveform Generator Example
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WAVES Waveform Generator
VHDLModel
Instantiation
MonitorProcesses
WAVESWaveformGenerator
Input Stimulus
ErrorMessagesActual Response
ExpectedResponse WAVES
Test Vector Set
Testbench
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WAVES ‘97 ConstructorLibrary
Provides Common Frame Shapes Drive Format (Input Signals)
Non Return Return High/Low Surround By Complement Pulse Low/High
Expected Format (Output Signals) Window (Compare)
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WAVES ‘97 Constructor Library
Non Return (user specifies t1 only)
logichigh
logiclow
t1 t2 t1 t2t0 t0 t0
data = 0 data = 1
Function format: Non_Return (t1)
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WAVES ‘97 Constructor Library
Non Return example
logichigh
logiclow
20ns 70ns0ns 50ns 100ns
data = 0 data = 1
Function format: Non_Return (20 ns)
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WAVES ‘97 Constructor Library
Return High (user specifies t1 and t2)
logichigh
logiclow
t1 t2 t1 t2t0 t0 t0
data = 0 data = 1
Function format: Return_High (t1, t2)
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WAVES ‘97 Constructor Library
Return High example
logichigh
logiclow
15ns 35ns 65ns 85ns0ns 50ns 100ns
data = 0 data = 1
Function format: Return_High (15 ns, 35 ns)
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WAVES ‘97 Constructor Library
Return Low (user specifies t1 and t2)
Function format: Return_Low (t1, t2)
logichigh
logiclow
t1 t2 t1 t2t0 t0 t0
data = 0 data = 1
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WAVES ‘97 Constructor Library
Return Low example
logichigh
logiclow
15ns 35ns 65ns 85ns0ns 50ns 100ns
data = 0 data = 1
Function format: Return_Low (15 ns, 35 ns)
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WAVES ‘97 Constructor Library
Surround By Complement (user specifies t1 & t2)
logichigh
logiclow
t1 t2 t1 t2t0 t0 t0
data = 0 data = 1
Function format: Surround_Complement (t1, t2)
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WAVES ‘97 Constructor Library
Surround By Complement example
logichigh
logiclow
10ns 30ns 60ns 80ns0ns 50ns 100ns
data = 0 data = 1
Function format: Surround_Complement (10 ns, 30 ns)
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WAVES ‘97 Constructor Library
Pulse Low (user specifies t1 and t2)
logichigh
logiclow
t1 t2 t1 t2t0 t0 t0
data = 0 data = L
Function format: Pulse_Low (t1, t2)
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WAVES ‘97 Constructor Library
Pulse Low example
logichigh
logiclow
5ns 15ns 25ns 35ns0ns 20ns 40ns
data = 0 data = L
Function format: Pulse_Low (5 ns, 15 ns)
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WAVES ‘97 Constructor Library
Pulse High (user specifies t1 and t2)
logichigh
logiclow
t1 t2 t1 t2t0 t0 t0
data = H data = 1
Function format: Pulse_High (t1, t2)
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WAVES ‘97 Constructor Library
Pulse High example
logichigh
logiclow
5ns 15ns
25ns 35ns0ns 20ns 40ns
data = H data = 1
Function format: Pulse_High (5 ns, 15 ns)
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WAVES ‘97 Constructor Library
Window (user specifies t1 and t2)
logichigh
logiclow
t1 t2 t1 t2t0 t0 t0
data = 0 data = 1
Function format: Window (t1, t2)
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WAVES ‘97 Constructor Library
Window example
logichigh
logiclow
5ns 15ns 25ns 35ns0ns 20ns 40ns
data = 0 data = 1
Function format: Window (5 ns, 15 ns)
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function Non_Return( T1 : EVENT_TIME ) return Frame_set;
function Return_Low( T1, T2 : EVENT_TIME ) return Frame_set;
function Return_High( T1, T2 : EVENT_TIME ) return Frame_set;
function Surround_Complement( T1, T2 : EVENT_TIME ) return Frame_set;
function Pulse_Low( T1, T2 : EVENT_TIME ) return Frame_set;
function Pulse_Low_Skew( T0, T1, T2 : EVENT_TIME ) return Frame_set;
function Pulse_High( T1, T2 : EVENT_TIME ) return Frame_set;
function Pulse_High_Skew( T0, T1, T2 : EVENT_TIME ) return Frame_set;
function Window( T1, T2 : EVENT_TIME ) return Frame_Set;
function Window_Skew( T0, T1, T2 : EVENT_TIME ) return Frame_Set;
WAVES 1164 Frame Definitions
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WAVES ‘97 Built-ins
Only A Handful of Built-in Functions Apply Delay Match Handshake Read_File_Slice
Used In Waveform Generator File
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WAVES ‘97 Built-ins
The Apply Procedure Schedules Events For the Current Slice On The
Waveform Equivalent To VHDL Signal Assignment
The Delay Procedure Suspends The Execution Of the WAVES Process For
The Given Time Duration Equivalent To VHDL “wait for”
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WAVES ‘97 Built-ins
The Match Procedure Initiates A Match Request To The Testbench
Provides Coarse (Value Level) Synchronization
The Handshake Procedure Initiates A Handshake Request To The Testbench
Provides Event Level Synchronization Suspends Execution Of The WAVES Process Until
The Handshake Request Is Satisfied
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WAVES ‘97 Built-ins
The Read_File_Slice Procedure Reads A Vector (Slice) From A WAVES External Pattern
File Predefined File Format
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Module Outline
Introduction Testbench Development Design Verification Challenges WAVES Concepts WAVES Constructor Library and Built-Ins
WAVES External File WAVES Test Set Decoder Example Algorithmic Waveform Generator Example
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WAVES External Test Vector File
VHDLModel
Instantiation
MonitorProcesses
WAVESWaveformGenerator
Input Stimulus
ErrorMessagesActual Response
ExpectedResponse WAVES
Test Vector Set
Testbench
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WAVES ‘97 External File
Separates Test Pattern Data From Functional WAVES Code
Organized Into File Slices One “Pin Code” Character Per Device Pin
Patterns May Be Specified As Binary Bit Level Patterns Or In Hexadecimal
May Freely Mix Binary And Hexadecimal Fields
Could Algorithmically Generate Test Vectors Within Waveform Generator File (an external pattern file would not be required in this case)
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WAVES External File (cont.)
File Slices Contain Two “Token” Types Data Tokens Specify Pattern Data
Binary Pin Code Tokens Hexadecimal Tokens
Control Tokens Specify Processing Timing Specifier Skip Command Repeat Command Hexadecimal Template
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WAVES External File (cont.)
File Slice Structure Any Mixture Of Data And Control Tokens Spaces And Tabs Are Permitted Data Tokens Must Be Terminated By Space Or Tab Slice May Span Several Lines Of The File Semicolon ‘;’ Is The Slice Terminator
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WAVES External File (cont.)
Special Characters ‘%’ Introduces A Comment
Comments Span To The End Of The Line ‘=‘ Introduces A Skip Command
Applies The Next Data Token Beginning At Column n (example: =32 1010)
‘+’ Introduces A Repeat Command Repeat Vector n Times (example: +200)
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WAVES External File Example
% In this example, the data tokens are in binary format only.
% The control tokens are timing specifiers which indicate the slice
% duration.
00010010 : 20 ns;
% data tokens => 00010010 control token => : 20ns
01110111 : 15 ns;
01111100 : 10 ns;
% In this example, the skip and repeat commands are shown below.
% The first test vector is in binary format and has a 20ns duration:
00010010 : 20 ns;
% The second test vector uses the skip command to apply the data
% tokens at column #5. In this case, the resultant vector is
% 00010111 with a 20ns duration.
=5 0111 ;
% The third test vector will be repeated 20 times with a 20ns
% duration during each application.
+20 01111100 ;
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WAVES External File (cont.)
Special Characters (cont.) ‘^’ Introduces Standard Hex Field
example: ^A5 => 10100101 ‘#’ Introduces User Defined Hex Template
Used To Define The Binary Pin Code String Generated By The Hex Field (example: #LH)
‘~’ Introduces User Hex Field example: ~A5 => HLHLLHLH
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WAVES External File Example (cont.)
% In this example, the data tokens are in standard hex format only.
% The control tokens are timing specifiers which indicate the slice
% duration.
^12 : 20 ns;
^77 : 15 ns;
^7C : 10 ns;
% In this example, the data tokens are in user-defined hex format.
% The control tokens are timing specifiers which indicate the slice
% duration.
#LH ~12 : 20 ns;
% data tokens => LLLHLLHL control tokens => #LH, : 20ns
~77 : 15 ns;
% data tokens => LHHHLHHH control token => : 15ns
% This vector uses the standard hex format
^77 : 15 ns;
% data tokens => 01110111 control token => : 15ns
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WAVES External File (cont.)
Special Characters (cont.) ‘:’ Introduces A Timing Specifier
May Be An Integer Or A TimeTime Indicates Duration Of Vector (example: 20 ns)Integer Indicates Timing Set Selection
‘;’ Indicates The End Of The File Slice
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WAVES External File Example (cont.)
% In this example, the data tokens are in binary format only.
% The control tokens are timing specifiers which indicate the timing
% set selection.
00010010 : 2;
% data tokens => 00010010 control token => : 2
% this vector is using timing set 2
01110111 : 1;
% this vector is using timing set 1
01111100 : 2;
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WAVES External File (cont.)
Hexadecimal Data Field Format Field Width Specifier Allowed (^XX:n)
Narrower Than Hex Field SpecifiedTruncate Left Most Charactersexample: ^FF08:14 => 11111100001000
Wider Than Hex Field SpecifiedFill With “Zeros” On The Leftexample: ^AA:16Generates: 0000000010101010
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WAVES External File (cont.)
Hexadecimal Data Field Format (cont.) Rules For Field Expansion
Hexadecimal Fields Generate Contiguous Character Patterns (example: 32 Bits Wide Starting In Column 10)
Total Generated Width Of The Entire Pattern May Not Exceed The Number Of Device Pins
Applies To Both Standard Hex Fields And User Defined Hex Fields
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Module Outline
Introduction Testbench Development Design Verification Challenges WAVES Concepts WAVES Constructor Library and Built-Ins WAVES External File
WAVES Test Set Decoder Example Algorithmic Waveform Generator Example
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WAVES Test Set
Structure Of A WAVES 1164 Test Set UUT Test Pins Package
Enumerated Type Declaration (Test_pins) Waveform Generator Package
Contains One Or More WAVES Waveform Generator Procedures (WAVES Processes)
Testbench File Optional External Pattern File Predefined WAVES 1164 Constructor Library And
WAVES Standard Packages
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WAVES Test Set (cont.)
The WAVES Header File Data Set Identification
Author, Revision Level, Device Name, and so forth WAVES File Identification
Compilation Order File Dependencies
External File Identification Identifies Test Vector File
Waveform Identification Specifies The Waveform Generator Procedures
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WAVES Header File Example
-- ******** Generic Header File
-- Data Set Identification Information
TITLE WAVES Test Set for Component X
DEVICE_ID component_x
DATE Wed July 16 16:03:05 1997
ORIGIN Component X Design Team
AUTHOR The Company of X, Y, and Z
OTHER comments relating to the data set
-- Data Set Construction Information
VHDL_FILENAME component_x.vhd WORK
WAVES_FILENAME test_pins.vhd WORK
library IEEE;
use IEEE.WAVES_1164_Declarations.all;
use IEEE.WAVES_Interface.all;
use WORK.UUT_Test_pins.all;
WAVES_UNIT WAVES_OBJECTS WORK
WAVES_FILENAME component_x_wgp.vhd WORK
VHDL_FILENAME component_x_tstbench.vhd WORK
EXTERNAL_FILENAME component_x_vect.txt VECTORS
WGEN_PROCEDURE WORK.wgp_component_x.waveform
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Module Outline
Introduction Testbench Development Design Verification Challenges WAVES Concepts WAVES Constructor Library and Built-Ins WAVES External File WAVES Test Set
Decoder Example Algorithmic Waveform Generator Example
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Decoder Example
DecoderInstantiation
MonitorProcesses
WAVESWaveformGenerator
Data(6:0) input
ErrorMessages
WAVESTest Vector Set
Testbench
expected A1..G1
A1..G1 output
A0..G0 output
expected A0..G0
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Decoder Example
This WAVES Example Consists Of 6 Files: Header File Behavioral VHDL Description Of Decoder Test Pins File External Test Vector File Waveform Generator File Testbench File
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Header File: Decoder Example
-- ******** Header File for Entity: display_driver
-- Data Set Identification Information
TITLE WAVES Decoder Test set example
DEVICE_ID display_driver
DATE Tue Mar 17 16:25:14 1998
ORIGIN RASSP E&F and UVA
AUTHOR UVA EE Dept
DATE Tue Mar 17 16:25:14 1998
OTHER This example demonstrates a complete WAVES test
OTHER set for a decoder device.
-- Data Set Construction Information
VHDL_FILENAME bcd_decoder.vhd WORK
WAVES_FILENAME bcd_decoder_pins.vhd WORK
library IEEE;
use IEEE.WAVES_1164_Declarations.all;
use IEEE.WAVES_Interface.all;
use WORK.UUT_Test_pins.all;
WAVES_UNIT WAVES_OBJECTS WORK
WAVES_FILENAME bcd_decoder_wgen.vhd WORK
VHDL_FILENAME bcd_decoder_tstbench.vhd WORK
EXTERNAL_FILENAME bcd_decoder_vectors.txt VECTORS
WAVEFORM_GENERATOR_PROCEDURE WORK.wgp_display_driver.waveform
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Decoder VHDL Description
ENTITY display_driver IS
PORT (data : IN std_logic_vector(6 DOWNTO 0);-- binary data input
A0 : OUT std_logic; -- segments for digit 0
B0 : OUT std_logic;
C0 : OUT std_logic;
D0 : OUT std_logic;
E0 : OUT std_logic;
F0 : OUT std_logic;
G0 : OUT std_logic;
A1 : OUT std_logic; -- segments for digit 1
B1 : OUT std_logic;
C1 : OUT std_logic;
D1 : OUT std_logic;
E1 : OUT std_logic;
F1 : OUT std_logic;
G1 : OUT std_logic);
END display_driver;
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Decoder VHDL Description (cont.)
ARCHITECTURE default OF display_driver IS
SIGNAL display1 : std_logic_vector(6 DOWNTO 0);
SIGNAL display0 : std_logic_vector(6 DOWNTO 0);
BEGIN
decode_process : PROCESS(data)
VARIABLE int_data : INTEGER := 0;
VARIABLE tens_place : INTEGER := 0;
VARIABLE ones_place : INTEGER := 0;
BEGIN
-- Convert the input data to an integer
int_data := to_integer(data);
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Decoder VHDL Description (cont.)
-- Next, determine the values for the ten's place digit and
-- the one's place digit
IF (int_data > 99)THEN
-- Error - assign both values = -1
ones_place := -1;
tens_place := -1;
ELSIF (int_data >= 90) THEN
ones_place := int_data - 90;
tens_place := 9;
ELSIF (int_data >= 80) THEN
ones_place := int_data - 80;
tens_place := 8;
ELSIF (int_data >= 70) THEN
ones_place := int_data - 70;
tens_place := 7;
ELSIF (int_data >= 60) THEN
ones_place := int_data - 60;
tens_place := 6;
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Decoder VHDL Description (cont.)
ELSIF (int_data >= 50) THEN
ones_place := int_data - 50;
tens_place := 5;
ELSIF (int_data >= 40) THEN
ones_place := int_data - 40;
tens_place := 4;
ELSIF (int_data >= 30) THEN
ones_place := int_data - 30;
tens_place := 3;
ELSIF (int_data >= 20) THEN
ones_place := int_data - 20;
tens_place := 2;
ELSIF (int_data >= 10) THEN
ones_place := int_data - 10;
tens_place := 1;
ELSE
ones_place := int_data;
tens_place := 0;
END IF;
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Decoder VHDL Description (cont.)
-- Finally, set the values of the output variables that drive
-- the 7-segment displays according to the values of
-- tens_place and ones_place
-- abcdefg
CASE ones_place IS
WHEN 0 => display0 <= "1111110"; -- zero
WHEN 1 => display0 <= "0110000"; -- one
WHEN 2 => display0 <= "1101101"; -- two
WHEN 3 => display0 <= "1111001"; -- three
WHEN 4 => display0 <= "0110011"; -- four
WHEN 5 => display0 <= "1011011"; -- five
WHEN 6 => display0 <= "1011111"; -- six
WHEN 7 => display0 <= "1110000"; -- seven
WHEN 8 => display0 <= "1111111"; -- eight
WHEN 9 => display0 <= "1110011"; -- nine
WHEN OTHERS => display0 <= "1001111"; -- error
END CASE;
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Decoder VHDL Description (cont.)
CASE tens_place IS
WHEN 0 => display1 <= "1111110"; -- zero
WHEN 1 => display1 <= "0110000"; -- one
WHEN 2 => display1 <= "1101101"; -- two
WHEN 3 => display1 <= "1111001"; -- three
WHEN 4 => display1 <= "0110011"; -- four
WHEN 5 => display1 <= "1011011"; -- five
WHEN 6 => display1 <= "1011111"; -- six
WHEN 7 => display1 <= "1110000"; -- seven
WHEN 8 => display1 <= "1111111"; -- eight
WHEN 9 => display1 <= "1110011"; -- nine
WHEN OTHERS => display1 <= "1001111"; -- error
END CASE;
END PROCESS;
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Decoder VHDL Description (cont.)
a0 <= display0(6);
b0 <= display0(5);
c0 <= display0(4);
d0 <= display0(3);
e0 <= display0(2);
f0 <= display0(1);
g0 <= display0(0);
a1 <= display1(6);
b1 <= display1(5);
c1 <= display1(4);
d1 <= display1(3);
e1 <= display1(2);
f1 <= display1(1);
g1 <= display1(0);
END default;
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Decoder Test Pin File
-- ******** This File Was Automatically Generated ******** -- ******** By The WAVES96-VHDL Tool Set ********-- ******** Generated for Entity: display_driver-- ******** This File Was Generated on: Fri Jan 30 16:43:40 1998----PACKAGE uut_test_pins ISTYPE test_pins IS (data_6, data_5, data_4, data_3, data_2, data_1,
data_0, A0, B0, C0, D0, E0, F0, G0, A1, B1, C1, D1, E1, F1, G1);
END uut_test_pins;
A new TYPE is declared for the external pins of the decoder.
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Decoder Test Vector File (excerpt)
% DATA ABCDEFG ABCDEFG% 1111111 00000000000000 1111110 1111110 : 500 ns ;0000001 1111110 0110000 : 500 ns ;0000010 1111110 1101101 : 500 ns ;0000011 1111110 1111001 : 500 ns ;0000100 1111110 0110011 : 500 ns ;0000101 1111110 1011011 : 500 ns ;0000110 1111110 1011111 : 500 ns ;0000111 1111110 1110000 : 500 ns ;0001000 1111110 1111111 : 500 ns ;0001001 1111110 1110011 : 500 ns ;0001010 0110000 1111110 : 500 ns ;0001011 0110000 0110000 : 500 ns ;0001100 0110000 1101101 : 500 ns ;0001101 0110000 1111001 : 500 ns ;0001110 0110000 0110011 : 500 ns ;0001111 0110000 1011011 : 500 ns ;
Each file slice contains data tokens for every test pin on the decoder. The duration for each slice is 500 ns.
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Decoder Waveform Generator File
---- ******** This File Was Automatically Generated ********-- ******** By The WAVES96-VHDL Tool Set ********-- ******** Generated for VHDL entity: ********-- ******** display_driver ********-- ******** Generation date and time: ********-- ******** Fri Jan 30 16:43:40 1998 ********--
use STD.TEXTIO.all;library IEEE;use IEEE.WAVES_1164_Frames.all;use IEEE.WAVES_1164_Declarations.all;use IEEE.WAVES_Interface.all;use WORK.WAVES_Objects.all;use WORK.UUT_Test_Pins.all;
package WGP_display_driver is
procedure WAVEFORM( signal WPL : inout WAVES_PORT_LIST );
end WGP_display_driver;
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Decoder Waveform Generator File (cont.)
package body WGP_display_driver is
procedure WAVEFORM( signal WPL : inout WAVES_PORT_LIST ) is
file VECTOR_FILE : text open READ_MODE is "bcd_decoder_vectors.txt"; variable VECTOR : FILE_SLICE := NEW_FILE_SLICE;
constant data : PINSET := data_6 + data_5 + data_4 + data_3 + data_2 + data_1 + data_0;
constant OUT_PINS : PINSET := A0 + B0 + C0 + D0 + E0 + F0 + G0 + A1 + B1 + C1 + D1 + E1 + F1 + G1;
constant DISP1 : PINSET := A1 + B1 + C1 + D1 + E1 + F1 + G1; constant DISP0 : PINSET := A0 + B0 + C0 + D0 + E0 + F0 + G0;
constant INPUTS : PINSET := data; constant OUTPUTS : PINSET := OUT_PINS;
Test vector filename declared in FILE statement.
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Decoder Waveform Generator File (cont.)
variable TIMING : FRAME_DATA := BUILD_FRAME_DATA( ( (INPUTS, NON_RETURN( 0 ns)), (DISP1, WINDOW( 400 ns, 500 ns)), (DISP0, WINDOW( 400 ns, 500 ns)) ) );
begin -- waveform generator procedure loop READ_FILE_SLICE( VECTOR_FILE, VECTOR ); exit when VECTOR.END_OF_FILE; APPLY( WPL, VECTOR.CODES.all, TIMING ); DELAY( VECTOR.FS_TIME ); end loop;
end WAVEFORM;
END WGP_display_driver;
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Decoder Waveform Generator File (cont.)
The user specifies the frame constructor functions and the appropriate timing values as shown below:
variable TIMING : FRAME_DATA := BUILD_FRAME_DATA( ( (INPUTS, NON_RETURN( 0 ns)), (DISP1, WINDOW( 400 ns, 500 ns)), (DISP0, WINDOW( 400 ns, 500 ns)) ) );
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Decoder Waveform Generator File (cont.)
400ns 500ns 900ns 1000ns0ns
Data(6:0)
A0
A1
test vector = 0000000 1 1 test vector = 0000001 1 0
0000000 0000001
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Decoder Waveform Generator File (cont.)
In the loop, a slice is read from the external file and applied to the corresponding signals as shown below:
loop READ_FILE_SLICE( VECTOR_FILE, VECTOR ); exit when VECTOR.END_OF_FILE; APPLY( WPL, VECTOR.CODES.all, TIMING ); DELAY( VECTOR.FS_TIME ); end loop;
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Decoder Waveform Generator File (cont.)
0000000 1111110 1111110 : 500 ns;
500 ns
VECTOR
File SliceFrom External File
codes fs_time end_of_file
0000000 1..0 1..0 false
End Of External File
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-- ******** This File Was Automatically Generated ******** -- ******** By The WAVES96-VHDL Tool Set ********-- ******** Generated for Entity: display_driver-- ******** This File Was Generated on: Fri Jan 30 16:43:42 1998----
LIBRARY IEEE;USE IEEE.std_logic_1164.ALL;USE IEEE.WAVES_1164_utilities.all;USE IEEE.WAVES_interface.all;
USE WORK.UUT_test_pins.all;USE work.waves_objects.all;USE work.WGP_display_driver.all;
-- Include component library references here-- User Must Modify And ADD component library references here-- Include component library references here
ENTITY test_bench ISEND test_bench;ARCHITECTURE display_driver_test OF test_bench IS
Decoder Testbench
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COMPONENT display_driver PORT ( data : IN std_logic_vector( 6 downto 0 ); A0 : OUT std_logic; B0 : OUT std_logic; C0 : OUT std_logic; D0 : OUT std_logic; E0 : OUT std_logic; F0 : OUT std_logic; G0 : OUT std_logic; A1 : OUT std_logic; B1 : OUT std_logic; C1 : OUT std_logic; D1 : OUT std_logic; E1 : OUT std_logic; F1 : OUT std_logic; G1 : OUT std_logic); END COMPONENT;
-- User Must Modify modify and declare correct -- .. Architecture, Library, Component .. -- Modify entity use statementFOR ALL:display_driver USE ENTITY work.display_driver(default);
Decoder Testbench (cont.)
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--********************************************************** -- stimulus signals for the waveforms mapped into UUT INPUTS --********************************************************** SIGNAL WAV_STIM_data :std_logic_vector( 6 downto 0 );
--**************************************************** -- Expected signals used in monitoring the UUT OUTPUTS --**************************************************** SIGNAL FAIL_SIGNAL :std_logic; SIGNAL WAV_EXPECT_A0 :std_ulogic; SIGNAL WAV_EXPECT_B0 :std_ulogic; SIGNAL WAV_EXPECT_C0 :std_ulogic; SIGNAL WAV_EXPECT_D0 :std_ulogic; SIGNAL WAV_EXPECT_E0 :std_ulogic; SIGNAL WAV_EXPECT_F0 :std_ulogic; SIGNAL WAV_EXPECT_G0 :std_ulogic; SIGNAL WAV_EXPECT_A1 :std_ulogic; SIGNAL WAV_EXPECT_B1 :std_ulogic; SIGNAL WAV_EXPECT_C1 :std_ulogic; SIGNAL WAV_EXPECT_D1 :std_ulogic; SIGNAL WAV_EXPECT_E1 :std_ulogic; SIGNAL WAV_EXPECT_F1 :std_ulogic; SIGNAL WAV_EXPECT_G1 :std_ulogic;
Decoder Testbench (cont.)
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--****************************************************** -- UUT Output signals used In Monitoring ACTUAL Values --****************************************************** SIGNAL ACTUAL_A0 :std_logic; SIGNAL ACTUAL_B0 :std_logic; SIGNAL ACTUAL_C0 :std_logic; SIGNAL ACTUAL_D0 :std_logic; SIGNAL ACTUAL_E0 :std_logic; SIGNAL ACTUAL_F0 :std_logic; SIGNAL ACTUAL_G0 :std_logic; SIGNAL ACTUAL_A1 :std_logic; SIGNAL ACTUAL_B1 :std_logic; SIGNAL ACTUAL_C1 :std_logic; SIGNAL ACTUAL_D1 :std_logic; SIGNAL ACTUAL_E1 :std_logic; SIGNAL ACTUAL_F1 :std_logic; SIGNAL ACTUAL_G1 :std_logic;
--*************************************************************** -- WAVES signals OUTPUTing each slice of the waves port list --***************************************************************
SIGNAL wpl : WAVES_port_list;
Decoder Testbench (cont.)
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BEGIN --*************************************************************** -- process that generates the WAVES waveform --*************************************************************** WAVES: waveform(wpl);
--*************************************************************** -- processes that assign the WPL values to testbench signals --*************************************************************** WAV_STIM_data <= To_StdLogicVector(wpl.signals( 1 to 7 )); WAV_EXPECT_A1 <= wpl.signals( 8 ); WAV_EXPECT_B1 <= wpl.signals( 9 ); WAV_EXPECT_C1 <= wpl.signals( 10 ); WAV_EXPECT_D1 <= wpl.signals( 11 ); WAV_EXPECT_E1 <= wpl.signals( 12 ); WAV_EXPECT_F1 <= wpl.signals( 13 ); WAV_EXPECT_G1 <= wpl.signals( 14 ); WAV_EXPECT_A0 <= wpl.signals( 15 ); WAV_EXPECT_B0 <= wpl.signals( 16 ); WAV_EXPECT_C0 <= wpl.signals( 17 ); WAV_EXPECT_D0 <= wpl.signals( 18 ); WAV_EXPECT_E0 <= wpl.signals( 19 ); WAV_EXPECT_F0 <= wpl.signals( 20 ); WAV_EXPECT_G0 <= wpl.signals( 21 );
Decoder Testbench (cont.)
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--******************************************* -- UUT Port Map - Name Semantics Denote Usage --******************************************* u1: display_driver PORT MAP( data => WAV_STIM_data, A0 => ACTUAL_A0, B0 => ACTUAL_B0, C0 => ACTUAL_C0, D0 => ACTUAL_D0, E0 => ACTUAL_E0, F0 => ACTUAL_F0, G0 => ACTUAL_G0, A1 => ACTUAL_A1, B1 => ACTUAL_B1, C1 => ACTUAL_C1, D1 => ACTUAL_D1, E1 => ACTUAL_E1, F1 => ACTUAL_F1, G1 => ACTUAL_G1);
Decoder Testbench (cont.)
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--********************************************************* -- Monitor Processes To Verify The UUT Operational Response --********************************************************* Monitor_A0: PROCESS(ACTUAL_A0, WAV_expect_A0) BEGIN assert(Compatible (actual => ACTUAL_A0, expected => WAV_expect_A0)) report "Error on A0 output" severity WARNING; END PROCESS;
Monitor_B0: PROCESS(ACTUAL_B0, WAV_expect_B0) BEGIN assert(Compatible (actual => ACTUAL_B0, expected => WAV_expect_B0)) report "Error on B0 output" severity WARNING; END PROCESS;
Decoder Testbench (cont.)
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Monitor_C0: PROCESS(ACTUAL_C0, WAV_expect_C0) BEGIN assert(Compatible (actual => ACTUAL_C0, expected => WAV_expect_C0)) report "Error on C0 output" severity WARNING; END PROCESS;
Monitor_D0: PROCESS(ACTUAL_D0, WAV_expect_D0) BEGIN assert(Compatible (actual => ACTUAL_D0, expected => WAV_expect_D0)) report "Error on D0 output" severity WARNING; END PROCESS;
Monitor_E0: PROCESS(ACTUAL_E0, WAV_expect_E0) BEGIN assert(Compatible (actual => ACTUAL_E0, expected => WAV_expect_E0)) report "Error on E0 output" severity WARNING; END PROCESS;
Decoder Testbench (cont.)
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Monitor_F0: PROCESS(ACTUAL_F0, WAV_expect_F0) BEGIN assert(Compatible (actual => ACTUAL_F0, expected => WAV_expect_F0)) report "Error on F0 output" severity WARNING; END PROCESS;
Monitor_G0: PROCESS(ACTUAL_G0, WAV_expect_G0) BEGIN assert(Compatible (actual => ACTUAL_G0, expected => WAV_expect_G0)) report "Error on G0 output" severity WARNING; END PROCESS;
Monitor_A1: PROCESS(ACTUAL_A1, WAV_expect_A1) BEGIN assert(Compatible (actual => ACTUAL_A1, expected => WAV_expect_A1)) report "Error on A1 output" severity WARNING; END PROCESS;
Decoder Testbench (cont.)
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Monitor_B1: PROCESS(ACTUAL_B1, WAV_expect_B1) BEGIN assert(Compatible (actual => ACTUAL_B1, expected => WAV_expect_B1)) report "Error on B1 output" severity WARNING; END PROCESS;
Monitor_C1: PROCESS(ACTUAL_C1, WAV_expect_C1) BEGIN assert(Compatible (actual => ACTUAL_C1, expected => WAV_expect_C1)) report "Error on C1 output" severity WARNING; END PROCESS;
Monitor_D1: PROCESS(ACTUAL_D1, WAV_expect_D1) BEGIN assert(Compatible (actual => ACTUAL_D1, expected => WAV_expect_D1)) report "Error on D1 output" severity WARNING; END PROCESS;
Decoder Testbench (cont.)
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Monitor_E1: PROCESS(ACTUAL_E1, WAV_expect_E1) BEGIN assert(Compatible (actual => ACTUAL_E1, expected => WAV_expect_E1)) report "Error on E1 output" severity WARNING; END PROCESS;
Monitor_F1: PROCESS(ACTUAL_F1, WAV_expect_F1) BEGIN assert(Compatible (actual => ACTUAL_F1, expected => WAV_expect_F1)) report "Error on F1 output" severity WARNING; END PROCESS;
Monitor_G1: PROCESS(ACTUAL_G1, WAV_expect_G1) BEGIN assert(Compatible (actual => ACTUAL_G1, expected => WAV_expect_G1)) report "Error on G1 output" severity WARNING; END PROCESS;END display_driver_test;
Decoder Testbench (cont.)
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Module Outline
Introduction Testbench Development Design Verification Challenges WAVES Concepts WAVES Constructor Library and Built-Ins WAVES External File WAVES Test Set Decoder Example
Algorithmic Waveform Generator Example
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Algorithmic Waveform Generators
Test vectors can be created algorithmically in the waveform generator
External file not required in this case All information that was previously contained in
file slices is now generated in the waveform generator procedure
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AND Circuit With Algorithmic Waveform Generator
AND CircuitInstantiation
MonitorProcesses
AlgorithmicWAVES
WaveformGenerator
x(3:0) input
ErrorMessagesActual z(3:0) output
Expected z(3:0)
Testbench
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AND Circuit With Algorithmic Waveform Generator Example
This WAVES Example Consists Of 5 Files: Header File Behavioral VHDL Description Of AND Circuit Test Pins File Waveform Generator File Testbench File
Algorithmic Waveform Generator Requires Additional Functionality Compared To Normal Waveform Generators
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AND Circuit With Algorithmic Waveform Generator
Header File-- ******** Header File for Entity: and_ckt
-- Data Set Identification Information
TITLE Algorithmic Waveform Generator Example
DEVICE_ID and_ckt
DATE Sun Sep 28 16:41:28 1997
ORIGIN Advanced WAVES Module
AUTHOR RASSP E&F and UVA
OTHER This example demonstrates an algorithmic waveform
OTHER generator which creates the test vectors without
OTHER using an external file.
-- Data Set Construction Information
VHDL_FILENAME a_ckt.vhd WORK
WAVES_FILENAME a_ckt_pins.vhd WORK
library IEEE;
use IEEE.WAVES_1164_Declarations.all;
use IEEE.WAVES_Interface.all;
use WORK.UUT_Test_pins.all;
WAVES_UNIT WAVES_OBJECTS WORK
WAVES_FILENAME a_ckt_wgen.vhd WORK
VHDL_FILENAME a_ckt_tstbench.vhd WORK
WAVEFORM_GENERATOR_PROCEDURE WORK.wgp_and_ckt.waveform
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AND Circuit VHDL Description
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY and_ckt IS
PORT (x: in std_ulogic_vector(3 downto 0);
z: out std_ulogic_vector(3 downto 0));
END and_ckt;
ARCHITECTURE behave OF and_ckt IS
BEGIN
PROCESS (x)
BEGIN
z(0) <= NOT(x(0)) AND NOT(x(2));
z(1) <= NOT(x(2)) AND x(1);
z(2) <= NOT(x(0)) AND NOT(x(3)) AND x(1);
z(3) <= NOT(x(1)) AND x(2) AND x(3);
END PROCESS;
END behave;
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AND Circuit Test Pin File
-- ******** This File Was Automatically Generated ********
-- ******** By The WAVES96-VHDL Tool Set ********
-- ******** Generated for Entity: and_ckt
-- ******** This File Was Generated on: Sun Sep 28 16:41:28 1997
--
--
PACKAGE uut_test_pins IS
TYPE test_pins IS (x_3, x_2, x_1, x_0, z_3, z_2, z_1, z_0);
END uut_test_pins;
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AND Circuit Algorithmic Waveform Generator
-- ******** This File Was Automatically Generated ********
-- ******** By The WAVES96-VHDL Tool Set ********
-- ******** Generated for VHDL entity: ********
-- ******** and_ckt ********
-- ******** Generation date and time: ********
-- ******** Sun Sep 28 16:41:28 1997 ********
use STD.TEXTIO.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_1164_extensions.all;
use IEEE.WAVES_1164_Frames.all;
use IEEE.WAVES_1164_Declarations.all;
use IEEE.WAVES_Interface.all;
use WORK.WAVES_Objects.all;
use WORK.UUT_Test_Pins.all;
package WGP_and_ckt is
procedure WAVEFORM( signal WPL : inout WAVES_PORT_LIST );
end WGP_and_ckt;
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AND Circuit Algorithmic Waveform Generator
package body WGP_and_ckt is
FUNCTION lfsr (CONSTANT x : IN waves_logic_vector(3 DOWNTO 0))
RETURN waves_logic_vector IS
VARIABLE z: waves_logic_vector(3 DOWNTO 0);
BEGIN
z(3 downto 1) := x(2 downto 0);
z(0) := x(3) xor x(0);
RETURN z;
END lfsr;
procedure WAVEFORM( signal WPL : inout WAVES_PORT_LIST ) is
constant x : PINSET := x_3 + x_2 + x_1 + x_0;
constant z : PINSET := z_3 + z_2 + z_1 + z_0;
variable lfsr_array: waves_logic_vector
((test_pins'pos(test_pins'left) + 1)
to (test_pins'pos(test_pins'right) + 1));
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AND Circuit Algorithmic Waveform Generator
type lfsr_values is array(1 to 15) of
waves_logic_vector(3 downto 0);
constant z_array : lfsr_values :=
( ("0000"), ("0111"), ("0010"), ("0000"), ("0000"), ("0100"),
("0000"), ("0001"), ("0000"), ("0011"), ("0010"), ("1000"),
("1000"), ("0000"), ("0000"));
variable i : positive := 1;
variable j : integer := 0;
variable x_count : integer := 0;
variable pincode_values : pin_code_string;
constant period : delay_time := 20 ns;
variable TIMING : FRAME_DATA :=
BUILD_FRAME_DATA(
(
(x, NON_RETURN(0 ns)),
(z, WINDOW(10 ns, 15 ns))
)
);
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AND Circuit Algorithmic Waveform Generator
begin -- waveform generator procedure
lfsr_array := "01100000"; -- initialize lfsr state
for j in x'range loop
if (x(test_pins(j)) = TRUE) then
x_count := x_count + 1;
end if;
end loop;
loop
lfsr_array((test_pins'pos(test_pins'left)+ 1) to x_count):=
lfsr(lfsr_array((test_pins'pos(test_pins'left) + 1) to
x_count));
lfsr_array(((test_pins'pos(test_pins'left) + 1) + x_count)
to (test_pins'pos(test_pins'right) + 1)) :=
z_array(To_Integer('0' &
lfsr_array((test_pins'pos(test_pins'left) + 1) to
x_count)));
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AND Circuit Algorithmic Waveform Generator
for i in (test_pins'pos(test_pins'left) + 1) to
(test_pins'pos(test_pins'right) + 1) loop
pincode_values(i) :=
pin_codes(logic_value'pos(lfsr_array(i)));
end loop;
APPLY( WPL, pincode_values, TIMING );
DELAY( period );
end loop;
end WAVEFORM;
END WGP_and_ckt;
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AND Circuit Testbench
-- ******** This File Was Automatically Generated ********
-- ******** By The WAVES96-VHDL Tool Set ********
-- ******** Generated for Entity: and_ckt
-- ******** This File Was Generated on: Sun Sep 28 16:41:29 1997
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.WAVES_1164_utilities.all;
USE IEEE.WAVES_interface.all;
USE WORK.UUT_test_pins.all;
USE work.waves_objects.all;
USE work.WGP_and_ckt.all;
-- Include component library references here
-- User Must Modify And ADD component library references here
-- Include component library references here
ENTITY test_bench IS
END test_bench;
ARCHITECTURE and_ckt_test OF test_bench IS
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AND Circuit Testbench (cont.)
--******************************************************
--***********CONFIGURATION SPECIFICATION ***************
--******************************************************
COMPONENT and_ckt
PORT ( x : IN std_ulogic_vector( 3 downto 0 );
z : OUT std_ulogic_vector( 3 downto 0 ));
END COMPONENT;
-- Modify entity use statement
-- User Must Modify modify and declare correct
-- .. Architecture, Library, Component ..
-- Modify entity use statement
FOR ALL:and_ckt USE ENTITY work.and_ckt(behave);
--**********************************************************
-- stimulus signals for the waveforms mapped into UUT INPUTS
--**********************************************************
SIGNAL WAV_STIM_x :std_ulogic_vector( 3 downto 0 );
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AND Circuit Testbench (cont.)
--****************************************************
-- Expected signals used in monitoring the UUT OUTPUTS
--****************************************************
SIGNAL FAIL_SIGNAL :std_logic;
SIGNAL WAV_EXPECT_z :std_ulogic_vector( 3 downto 0 );
--******************************************************
-- UUT Output signals used In Monitoring ACTUAL Values
--******************************************************
SIGNAL ACTUAL_z :std_ulogic_vector( 3 downto 0 );
--***************************************************************
-- WAVES signals OUTPUTing each slice of the waves port list
--***************************************************************
SIGNAL wpl : WAVES_port_list;
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AND Circuit Testbench (cont.)
BEGIN
--***************************************************************
-- process that generates the WAVES waveform
--***************************************************************
WAVES: waveform(wpl);
--***************************************************************
-- processes that assign the WPL values to testbench signals
--***************************************************************
WAV_STIM_x <= wpl.signals( 1 to 4 );
WAV_EXPECT_z <= wpl.signals( 5 to 8 );
--*******************************************
-- UUT Port Map - Name Semantics Denote Usage
--*******************************************
u1: and_ckt
PORT MAP(
x => WAV_STIM_x,
z => ACTUAL_z);
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AND Circuit Testbench (cont.)
--*********************************************************
-- Monitor Processes To Verify The UUT Operational Response
--*********************************************************
Monitor_z:
PROCESS(ACTUAL_z, WAV_expect_z)
BEGIN
assert(Compatible (actual => ACTUAL_z,
expected => WAV_expect_z))
report "Error on z output" severity WARNING;
IF ( Compatible ( ACTUAL_z, WAV_expect_z) ) THEN
FAIL_SIGNAL <='L'; ELSE FAIL_SIGNAL <='1';
END IF;
END PROCESS;
END and_ckt_test;
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References
[Abramovici90] Abramovici, Miron, Melvin A. Breuer, Arthur D. Friedman. Digital Systems Testing And Testable Design. Computer Science Press, New York, 1990.
[Flynn94] Christopher J. Flynn, Frederick G. Hall, James P. Hanna, and Mark T. Pronobis. “Using WAVES In A Top-Down Design Methodology,” VHDL International Users’ Forum, Nov. 1994.
[Hanna97] Hanna, James P., Robert G. Hillman, Herb L. Hirsch, Tim H. Noh, Ranga R. Vemuri. Using WAVES And VHDL For Effective Design And Testing. Kluwer Academic Publishers, Boston, 1997.
[IEEE] All referenced IEEE material is used with permission.
[Pronobis95] Mark T. Pronobis, Robert Hillman, Christopher Flynn. “Test Insertion Without Being A Test Expert,” VHDL International Users’ Forum, Oct. 1995.
[STD97] Draft IEEE Standard For VHDL Waveform And Vector Exchange (WAVES), IEEE Standard 1029.1-1996, IEEE Computer Society & IEEE Standards Coordinating Committee 20, May 1997.