7
103 Hardware/Software Interface © 2019 Uwe R. Zimmer, The Australian National University page 103 of 481 (chapter 2: “Hardware/Software Interface” up to page 150) Adding the value of two registers r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 SP LR PC ALU Register bank Status flags 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 0 0 0 ANDS r5, r6 0 0 0 1 0 1 1 1 0 16#35# 16#40# Assembler Disassembler r5 := r5 & r6 100 Hardware/Software Interface © 2019 Uwe R. Zimmer, The Australian National University page 100 of 481 (chapter 2: “Hardware/Software Interface” up to page 150) Adding the value of two registers r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 SP LR PC ALU Register bank Status flags 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 1 0 0 Rm Rn Rd ADDS <Rd>, <Rn>, <Rm> Op Code Arguments 97 2 Hardware/Software Interface Uwe R. Zimmer - The Australian National University Computer Organisation & Program Execution 2019 104 Hardware/Software Interface © 2019 Uwe R. Zimmer, The Australian National University page 104 of 481 (chapter 2: “Hardware/Software Interface” up to page 150) Adding the value of two registers r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 SP LR PC ALU Register bank Status flags 16#D4# 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 1 0 0 ADDS r4, r2, r3 1 0 0 0 1 0 0 1 1 16#18# 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 1 0 0 ADDS r4, r2, r3 0 1 1 1 0 0 0 1 0 16# 18 # 16# D4 # Assembler Disassembler r4 := r2 + r3 Status flags set: N Negative (MSB = 1) Z Zero (all bits zero) C Carry (carry out) V Overflow (sign wrong) 101 Hardware/Software Interface © 2019 Uwe R. Zimmer, The Australian National University page 101 of 481 (chapter 2: “Hardware/Software Interface” up to page 150) Adding the value of two registers r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 SP LR PC ALU Register bank Status flags 16#D4# 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 1 0 0 ADDS r4, r2, r3 1 0 0 0 1 0 0 1 1 16#18# 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 1 0 0 ADDS r4, r2, r3 0 1 1 1 0 0 0 1 0 16# 18 # 16# D4 # Assembler Disassembler r4 := r2 + r3 Status flags set: N Negative (MSB = 1) Z Zero (all bits zero) C Carry (carry out) V Overflow (sign wrong) 98 Hardware/Software Interface © 2019 Uwe R. Zimmer, The Australian National University page 98 of 481 (chapter 2: “Hardware/Software Interface” up to page 150) References for this chapter [Patterson17] David A. Patterson & John L. Hennessy Computer Organization and Design – The Hardware/Software Interface Chapter 2 “Instructions: Language of the Computer” & Chapter 3 “Arithmetic for Computers” ARM edition, Morgan Kaufmann 2017 105 Hardware/Software Interface © 2019 Uwe R. Zimmer, The Australian National University page 105 of 481 (chapter 2: “Hardware/Software Interface” up to page 150) ARM v7-M 32 bit add instructions add{s}<c><q> {<Rd>,} <Rn>, <Rm> {,<shift>} adc{s}<c><q> {<Rd>,} <Rn>, <Rm> {,<shift>} add{s}<c><q> {<Rd>,} <Rn>, #<const> adc{s}<c><q> {<Rd>,} <Rn>, #<const> qadd<c><q> {<Rd>,} <Rn>, <Rm> s: sets the ags based on the result c: makes the command conditional. <c> can be EQ (equal), NE (not equal), CS (carry set), CC (carry clear), MI (minus), PL (plus), VS (overflow set), VC (overflow clear), HI (unsigned higher), LS (unsigned lower or same), GE (signed greater or equal), LT (signed less), GT (signed greater), LE (signed less or equal), AL (always) q: instruction width. Can be .N for narrow (16 bit) or .W for wide (32 bit) Rd, Rn, Rm: any register, incl. SP, LR and PC (with some restrictions). Result goes to Rn (if no Rd). shift: value of Rm is preprocessed with LSL (logical shift left – fills zeros), LSR (logical shift right – fills zeros), ASR (arithmetic shift right – keeps sign) or ROR (rotate right) followed by the #number of bits to shift/rotate by. There is also a RRX (rotate right by one incl. carry flag) const: an immediate value in the range 0 .. 4095 directly or in the range 0 .. 255 with rotation. adds r1, r4, r5 adcs r1, r4 qadd r1, r4, r5 add r1, #1 102 Hardware/Software Interface © 2019 Uwe R. Zimmer, The Australian National University page 102 of 481 (chapter 2: “Hardware/Software Interface” up to page 150) Adding the value of two registers r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 SP LR PC ALU Register bank Status flags 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 0 0 0 Rm Rdn ANDS <Rdn>, <Rm> Op Code Arguments 0 0 0 99 Hardware/Software Interface © 2019 Uwe R. Zimmer, The Australian National University page 99 of 481 (chapter 2: “Hardware/Software Interface” up to page 150) Adding the value of two registers r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 SP LR PC ALU Register bank Status flags The CPU will fetch the content of the memory cell which PC is pointing to. G We want the CPU to execute: r4 := r2 + r3 G What to store in this memory cell?

COPE-02 Hardware/Software Interface...103 Hardware/Software Interface © 2019 Uwe R. Zimmer, The Australian National University page 103 of 481 (chapter 2: “Hardware/Software Interface”

  • Upload
    others

  • View
    5

  • Download
    0

Embed Size (px)

Citation preview

Page 1: COPE-02 Hardware/Software Interface...103 Hardware/Software Interface © 2019 Uwe R. Zimmer, The Australian National University page 103 of 481 (chapter 2: “Hardware/Software Interface”

103

Har

dw

are/

Soft

war

e In

terf

ace

© 2

019

Uw

e R

. Zim

mer

, The

Aus

tral

ian

Nat

iona

l Uni

vers

ity

page

103

of 4

81 (c

hapt

er 2

: “H

ardw

are/

Softw

are

Inte

rfac

e” u

p to

pag

e 15

0)

Add

ing

the

valu

e of

tw

o re

gist

ers

Ai

XOR

AND

Bi

XOR

AND

OR

S i

C0

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

r0

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

C

r1

r2

r3

r4 r5

r6

r7

r8

r9

r10

r11

r12

SP LR PC

ALU

Regi

ster

ban

k

Status flags

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

1514

1312

1110

98

76

54

32

10

01

00

00

0

ANDS r5, r6

00

01

01

11

0

16#35#

16#40#

Ass

emb

ler

Dis

asse

mb

ler

r5 := r5 & r6

100

Har

dw

are/

Soft

war

e In

terf

ace

© 2

019

Uw

e R

. Zim

mer

, The

Aus

tral

ian

Nat

iona

l Uni

vers

ity

page

100

of 4

81 (c

hapt

er 2

: “H

ardw

are/

Softw

are

Inte

rfac

e” u

p to

pag

e 15

0)

Add

ing

the

valu

e of

tw

o re

gist

ers

Ai

XOR

AND

Bi

XOR

AND

OR

S i

C0

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

r0

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

C

r1

r2

r3

r4 r5

r6

r7

r8

r9

r10

r11

r12

SP LR PC

ALU

Regi

ster

ban

k

Status flags

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

1514

1312

1110

98

76

54

32

10

00

01

10

0R

mR

nR

d

ADDS <Rd>, <Rn>, <Rm>

Op

Cod

eA

rgum

ents

97

2H

ardw

are/

Softw

are

Inte

rfac

e

Uw

e R

. Zim

mer

- T

he A

ustr

alia

n N

atio

nal U

nive

rsity

Co

mp

ute

r Org

anis

atio

n &

Pro

gram

Exe

cuti

on

201

9

104

Har

dw

are/

Soft

war

e In

terf

ace

© 2

019

Uw

e R

. Zim

mer

, The

Aus

tral

ian

Nat

iona

l Uni

vers

ity

page

104

of 4

81 (c

hapt

er 2

: “H

ardw

are/

Softw

are

Inte

rfac

e” u

p to

pag

e 15

0)

Add

ing

the

valu

e of

tw

o re

gist

ers

Ai

XOR

AND

Bi

XOR

AND

OR

S i

C0

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

r0

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

OR

OP 1

-4R

esu

lti

OP 1

-4R

esu

lti

OP 1

-4R

esu

lti

OP 1

-4R

esu

lti

OP 1

-4R

esu

lti

OP 1

-4R

esu

lti

OP 1

-4R

esu

lti

OP 1

-4R

esu

lti

OP 1

-4R

esu

lti

OP 1

-4R

esu

lti

r1

r2

r3

r4 r5

r6

r7

r8

r9

r10

r11

r12

SP LR PC

ALU

Regi

ster

ban

k

Status flags

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

D

C

DD

DD

DD

DD

DD

DD

DD

DD

D

C

DD

DD

DD

DD

DD

DD

DD

DD

D

C

DD

DD

DD

DD

DD

DD

DD

DD

D

C

DD

DD

DD

DD

DD

DD

DD

DD

D

C

DD

DD

DD

16#D

4#

1514

1312

1110

98

76

54

32

10

00

01

10

0

ADDS r4, r2, r3

10

00

10

01

1

16#18#

1514

1312

1110

98

76

54

32

10

00

01

10

0

ADDS r4, r2, r3

01

11

00

01

0

16#18#

16#D

4#

Ass

emb

ler

Dis

asse

mb

ler

r4 := r2 + r3

Res

ult

iO

P 1-4

Res

ult

iO

P 1-4

Res

ult

iO

P 1-4

Res

ult

iO

P 1-4

Res

ult

iO

P 1-4

Res

ult

iO

P 1-4

Res

ult

iO

P 1-4

Res

ult

iO

P 1-4

Res

ult

iO

P 1-4

Res

ult

i

Stat

us

fl ag

s se

t:

• N

Neg

ativ

e (M

SB =

1)

• Z

Zer

o (a

ll b

its

zero

)

• C

Car

ry (c

arry

ou

t)

• V

Ove

rfl o

w (s

ign

wro

ng)

101

Har

dw

are/

Soft

war

e In

terf

ace

© 2

019

Uw

e R

. Zim

mer

, The

Aus

tral

ian

Nat

iona

l Uni

vers

ity

page

101

of 4

81 (c

hapt

er 2

: “H

ardw

are/

Softw

are

Inte

rfac

e” u

p to

pag

e 15

0)

Add

ing

the

valu

e of

tw

o re

gist

ers

Ai

XOR

AND

Bi

XOR

AND

OR

S i

C0

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

r0

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

OR

OP 1

-4

r1

r2

r3

r4 r5

r6

r7

r8

r9

r10

r11

r12

SP LR PC

ALU

Regi

ster

ban

k

Status flags

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

D

C

DD

DD

DD

DD

DD

DD

DD

DD

D

C

DD

DD

DD

DD

DD

DD

DD

DD

D

C

DD

DD

DD

DD

DD

DD

DD

DD

D

C

DD

DD

DD

DD

DD

DD

DD

DD

D

C

DD

DD

DD

16#D

4#

1514

1312

1110

98

76

54

32

10

00

01

10

0

ADDS r4, r2, r3

10

00

10

01

1

16#18#

1514

1312

1110

98

76

54

32

10

00

01

10

0

ADDS r4, r2, r3

01

11

00

01

0

16#18#

16#D

4#

Ass

emb

ler

Dis

asse

mb

ler

r4 := r2 + r3

Stat

us

fl ag

s se

t:

• N

Neg

ativ

e (M

SB =

1)

• Z

Zer

o (a

ll b

its

zero

)

• C

Car

ry (c

arry

ou

t)

• V

Ove

rfl o

w (s

ign

wro

ng)

98

Har

dw

are/

Soft

war

e In

terf

ace

© 2

019

Uw

e R

. Zim

mer

, The

Aus

tral

ian

Nat

iona

l Uni

vers

ity

page

98

of 4

81 (c

hapt

er 2

: “H

ardw

are/

Softw

are

Inte

rfac

e” u

p to

pag

e 15

0)

Ref

eren

ces

for

this

cha

pter

[Pat

ters

on1

7]D

avid

A. P

atte

rso

n &

Joh

n L

. Hen

nes

syC

om

pu

ter O

rgan

izat

ion

an

d D

esig

n –

Th

e H

ard

war

e/So

ftw

are

Inte

rfac

eC

hap

ter 2

“In

stru

ctio

ns:

Lan

guag

e o

f th

e C

om

pu

ter”

& C

hap

ter 3

“A

rith

met

ic fo

r Co

mp

ute

rs”

AR

M e

dit

ion

, Mo

rgan

Kau

fman

n 2

017

105

Har

dw

are/

Soft

war

e In

terf

ace

© 2

019

Uw

e R

. Zim

mer

, The

Aus

tral

ian

Nat

iona

l Uni

vers

ity

page

105

of 4

81 (c

hapt

er 2

: “H

ardw

are/

Softw

are

Inte

rfac

e” u

p to

pag

e 15

0)

AR

M v

7-M

32

bit

add

inst

ruct

ions

add{s}<c><q> {<Rd>,} <Rn>, <Rm> {,<shift>}

adc{s}<c><q> {<Rd>,} <Rn>, <Rm> {,<shift>}

add{s}<c><q> {<Rd>,} <Rn>, #<const>

adc{s}<c><q> {<Rd>,} <Rn>, #<const>

qadd<c><q> {<Rd>,} <Rn>, <Rm>

s: s

ets

the fl

ags

bas

ed o

n th

e re

sult

c: m

akes

the

com

man

d c

ondi

tion

al. <

c> c

an b

e EQ

(eq

ual

), N

E (n

ot e

qu

al),

CS

(car

ry

set)

, CC

(car

ry c

lear

), M

I (m

inu

s), P

L (p

lus)

, VS

(ove

rfl o

w s

et),

VC

(ove

rfl o

w c

lear

), H

I (u

nsi

gned

hig

her

), LS

(un

sign

ed lo

wer

or

sam

e), G

E (s

ign

ed g

reat

er o

r eq

ual

), LT

(sig

ned

less

), G

T (s

ign

ed g

reat

er),

LE (s

ign

ed le

ss o

r eq

ual

), A

L (a

lway

s)

q: in

stru

ctio

n w

idth

. Can

be .N

for

nar

row

(16

bit

) or .W

for

wid

e (3

2 b

it)

Rd, Rn,

Rm:

any

reg

iste

r, in

cl. SP,

LR

and

PC

(wit

h s

om

e re

stri

ctio

ns)

. Res

ult

go

es to

Rn

(if n

o Rd)

.

shift:

val

ue

of R

m is

pre

proc

esse

d w

ith

LSL

(lo

gica

l sh

ift l

eft –

fi lls

zer

os)

, LSR

(lo

gica

l sh

ift

righ

t – fi

lls z

ero

s), ASR

(ari

thm

etic

sh

ift r

igh

t – k

eep

s si

gn) o

r ROR

(ro

tate

rig

ht)

follo

wed

by

the

#nu

mb

er o

f bit

s to

sh

ift/

rota

te b

y. T

her

e is

als

o a

RRX

(ro

tate

rig

ht b

y o

ne

incl

. car

ry fl

ag)

const:

an

imm

edia

te v

alue

in th

e ra

nge

0 ..

409

5 d

irec

tly

or

in th

e ra

nge

0 ..

255

wit

h r

ota

tio

n.

adds r1, r4, r5

adcs r1, r4

qadd r1, r4, r5

add r1, #1

102

Har

dw

are/

Soft

war

e In

terf

ace

© 2

019

Uw

e R

. Zim

mer

, The

Aus

tral

ian

Nat

iona

l Uni

vers

ity

page

102

of 4

81 (c

hapt

er 2

: “H

ardw

are/

Softw

are

Inte

rfac

e” u

p to

pag

e 15

0)

Add

ing

the

valu

e of

tw

o re

gist

ers

Ai

XOR

AND

Bi

XOR

AND

OR

S i

C0

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

r0

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

C

r1

r2

r3

r4 r5

r6

r7

r8

r9

r10

r11

r12

SP LR PC

ALU

Regi

ster

ban

k

Status flags

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

1514

1312

1110

98

76

54

32

10

01

00

00

0R

mR

dn

ANDS <Rdn>, <Rm>

Op

Cod

eA

rgum

ents

00

0

99

Har

dw

are/

Soft

war

e In

terf

ace

© 2

019

Uw

e R

. Zim

mer

, The

Aus

tral

ian

Nat

iona

l Uni

vers

ity

page

99

of 4

81 (c

hapt

er 2

: “H

ardw

are/

Softw

are

Inte

rfac

e” u

p to

pag

e 15

0)

Add

ing

the

valu

e of

tw

o re

gist

ers

Ai

XOR

AND

Bi

XOR

AND

OR

S i

C0

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

r0

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

Ai

XOR

AND

Bi

XOR

AND

OR

S i

AND

AND

AND

AND

OR

OR

OP 1

-4R

esu

lti

C

r1

r2

r3

r4 r5

r6

r7

r8

r9

r10

r11

r12

SP LR PC

ALU

Regi

ster

ban

k

Status flags

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

D

C

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

D

The

CPU

will

fetc

h th

e co

nte

nt o

f th

e m

emo

ry c

ell w

hic

h PC

is p

oin

tin

g to

.

We

wan

t th

e C

PU to

exe

cute

: r4 := r2 + r3

Wh

at to

sto

re in

this

mem

ory

cel

l?

Page 2: COPE-02 Hardware/Software Interface...103 Hardware/Software Interface © 2019 Uwe R. Zimmer, The Australian National University page 103 of 481 (chapter 2: “Hardware/Software Interface”

112

Har

dw

are/

Soft

war

e In

terf

ace

© 2

019

Uw

e R

. Zim

mer

, The

Aus

tral

ian

Nat

iona

l Uni

vers

ity

page

112

of 4

81 (c

hapt

er 2

: “H

ardw

are/

Softw

are

Inte

rfac

e” u

p to

pag

e 15

0)

AR

M v

7-M

Mov

e da

ta in

side

the

CPU

mov{s}<c><q> <Rd>, <Rm>

mov{s}<c><q> <Rd>, #<const>

; Rd := Rm

; Rd := const

lsr{s}<c><q> <Rd>, <Rm>, #<n>

lsr{s}<c><q> <Rd>, <Rm>, <Rs>

; 0

00

3130

2928

2726

2524

2322

2120

1918

1716

x15

1413

1211

109

87

65

43

21

0

..

C . cn

xxxx

ccccc

asr{s}<c><q> <Rd>, <Rm>, #<n>

asr{s}<c><q> <Rd>, <Rm>, <Rs>

; s

ss

3130

2928

s2

10

..

C . cn

sssss

cccc

lsl{s}<c><q> <Rd>, <Rm>, #<n>

lsl{s}<c><q> <Rd>, <Rm>, <Rs>

; 0

00

3130

297

65

43

21

0

..

x

C .n

xxxxcccccc

ror{s}<c><q> <Rd>, <Rm>, #<n>

ror{s}<c><q> <Rd>, <Rm>, <Rs>

; c

ba

3130

2928

2726

2524

2322

2120

1918

1716

x15

1413

1211

109

87

65

43

21

0

xx

xx

xx

xx

xx

xx

xx

xx

xx

xx

xx

xx

xx

xx

x

C .n

xxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxccccc

ccccbbbbb

aaaa

rrx{s}<c><q> <Rd>, <Rm>

; x

x

3130

2928

2726

2524

2322

2120

1918

1716

xx

xx

xx

xx

xx

xx

xx

xx

1514

1312

1110

98

76

54

32

10

xx

xx

xx

xx

xx

xx

xx

xy

xx

xx

xx

xx

xx

xx

xx

xx

xx

xx

xx

xx

xx

xx

x

C y

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxx

xxxxxxxx

xxxxxxxxxx

xxxxxxxxxx

xxxxxxxxxx

xxxxxxxxxx

xxxxxxxxxx

xxxxxxxxxx

xxxxxxxxxx

xxxxxxxxxx

xxxxxxxxxx

xxxxxxxxxx

xxxxxxxxxx

xxxxxxxxxx

xxxxxxxxxx

xxxxxxxxxx

xxxxyyyyyyyy

yyyyyyyccccc

ccccc

If th

is is

nu

mb

ers

then

/R

m2n

ro

un

ded

tow

ard

s 3

-

Rm

2n$fo

r 2’

s co

mp

lem

ents

109

Har

dw

are/

Soft

war

e In

terf

ace

© 2

019

Uw

e R

. Zim

mer

, The

Aus

tral

ian

Nat

iona

l Uni

vers

ity

page

109

of 4

81 (c

hapt

er 2

: “H

ardw

are/

Softw

are

Inte

rfac

e” u

p to

pag

e 15

0)

64 b

it A

ddit

ion,

Sub

trac

tion

As

you

r re

gist

ers

are

32 b

it w

ide,

yo

u n

eed

two

ste

ps

to a

dd

two

64

bit

nu

mb

ers

in

r3:r2,

r5:r4

(wit

h r2

and

r4

bei

ng

the

low

er 3

2 b

its)

to o

ne

64 b

it n

um

ber

in r1:r0

:

adds

r0, r2, r4

; r0 := r2 + r4 add least significant words, set flags

adcs

r1, r3, r5

; r1 := r3 + r5 + C add most significant words and carry bit

… a

nd

sym

met

rica

lly if

yo

u n

eed

a 6

4 b

it s

ub

trac

tio

n:

subs

r0, r2, r4

; r0 := r2 - r4 least significant words, set flags

sbcs

r1, r3, r5

; r1 := r3 - r5 - NOT (C) most significant words and carry bit

106

Har

dw

are/

Soft

war

e In

terf

ace

© 2

019

Uw

e R

. Zim

mer

, The

Aus

tral

ian

Nat

iona

l Uni

vers

ity

page

106

of 4

81 (c

hapt

er 2

: “H

ardw

are/

Softw

are

Inte

rfac

e” u

p to

pag

e 15

0)

AR

M v

7-M

32

bit

add

inst

ruct

ions

add{s}<c><q> {<Rd>,} <Rn>, <Rm> {,<shift>}

adc{s}<c><q> {<Rd>,} <Rn>, <Rm> {,<shift>}

add{s}<c><q> {<Rd>,} <Rn>, #<const>

adc{s}<c><q> {<Rd>,} <Rn>, #<const>

qadd<c><q> {<Rd>,} <Rn>, <Rm>

s: s

ets

the fl

ags

bas

ed o

n th

e re

sult

c: m

akes

the

com

man

d c

ondi

tion

al. <

c> c

an b

e EQ

(eq

ual

), N

E (n

ot e

qu

al),

CS

(car

ry

set)

, CC

(car

ry c

lear

), M

I (m

inu

s), P

L (p

lus)

, VS

(ove

rfl o

w s

et),

VC

(ove

rfl o

w c

lear

), H

I (u

nsi

gned

hig

her

), LS

(un

sign

ed lo

wer

or

sam

e), G

E (s

ign

ed g

reat

er o

r eq

ual

), LT

(sig

ned

less

), G

T (s

ign

ed g

reat

er),

LE (s

ign

ed le

ss o

r eq

ual

), A

L (a

lway

s)

q: in

stru

ctio

n w

idth

. Can

be .N

for

nar

row

(16

bit

) or .W

for

wid

e (3

2 b

it)

Rd, Rn,

Rm:

any

reg

iste

r, in

cl. SP,

LR

and

PC

(wit

h s

om

e re

stri

ctio

ns)

. Res

ult

go

es to

Rn

(if n

o Rd)

.

shift:

val

ue

of R

m is

pre

proc

esse

d w

ith

LSL

(lo

gica

l sh

ift l

eft –

fi lls

zer

os)

, LSR

(lo

gica

l sh

ift

righ

t – fi

lls z

ero

s), ASR

(ari

thm

etic

sh

ift r

igh

t – k

eep

s si

gn) o

r ROR

(ro

tate

rig

ht)

follo

wed

by

the

#nu

mb

er o

f bit

s to

sh

ift/

rota

te b

y. T

her

e is

als

o a

RRX

(ro

tate

rig

ht b

y o

ne

incl

. car

ry fl

ag)

const:

an

imm

edia

te v

alue

in th

e ra

nge

0 ..

409

5 d

irec

tly

or

in th

e ra

nge

0 ..

255

wit

h r

ota

tio

n.

An

y o

f th

ose

inst

ruct

ion

s re

qu

ires

exa

ctly

on

e C

PU c

ycle

(i

n te

rms

of t

hro

ugh

pu

t).

“Red

uce

d In

stru

ctio

n

Set C

om

pu

tin

g (R

ISC

)”

113

Har

dw

are/

Soft

war

e In

terf

ace

© 2

019

Uw

e R

. Zim

mer

, The

Aus

tral

ian

Nat

iona

l Uni

vers

ity

page

113

of 4

81 (c

hapt

er 2

: “H

ardw

are/

Softw

are

Inte

rfac

e” u

p to

pag

e 15

0)

Sim

ple

arit

hmet

ic in

side

the

CPU

Cal

cula

te:

e := a + b - 2*c

assu

min

g al

l typ

es a

re 3

2 b

it 2

’s c

om

ple

men

t nu

mb

ers

(Integer

),r1

ho

lds a,

r2

ho

lds b,

r3

ho

lds c,

an

d th

e re

sult

s sh

ou

ld b

e in

r4.

110

Har

dw

are/

Soft

war

e In

terf

ace

© 2

019

Uw

e R

. Zim

mer

, The

Aus

tral

ian

Nat

iona

l Uni

vers

ity

page

110

of 4

81 (c

hapt

er 2

: “H

ardw

are/

Softw

are

Inte

rfac

e” u

p to

pag

e 15

0)

AR

M v

7-M

32

bit

Boo

lean

(bi

t-w

ise)

inst

ruct

ions

and{s}<c><q> {<Rd>,} <Rn>, <Rm> {,<shift>} ;

:R

dR

nR

msh

ifte

d/

=

bic{s}<c><q> {<Rd>,} <Rn>, <Rm> {,<shift>} ;

:R

dR

nR

msh

ifte

d/

=orr{s}<c><q> {<Rd>,} <Rn>, <Rm> {,<shift>} ;

:R

dR

nR

msh

ifte

d0

=

orn{s}<c><q> {<Rd>,} <Rn>, <Rm> {,<shift>} ;

:R

dR

nR

msh

ifte

d0

=eor{s}<c><q> {<Rd>,} <Rn>, <Rm> {,<shift>} ;

:R

dR

nR

msh

ifte

d5

=and{s}<c><q> {<Rd>,} <Rn>, #<const>

;

:R

dR

nco

nst

/=

bic{s}<c><q> {<Rd>,} <Rn>, #<const>

;

:R

dR

nco

nst

/=

orr{s}<c><q> {<Rd>,} <Rn>, #<const>

;

:R

dR

nco

nst

0=

orn{s}<c><q> {<Rd>,} <Rn>, #<const>

;

:R

dR

nco

nst

0=

eor{s}<c><q> {<Rd>,} <Rn>, #<const>

;

:R

dR

nco

nst

5=

cmp<c><q> <Rn>, <Rm> {,<shift>}

; R

RFl

ags

nm

shif

ted

"-

^h

cmn<c><q> <Rn>, <Rm> {,<shift>}

; R

RFl

ags

nm

shif

ted

"+

^h

tst<c><q> <Rn>, <Rm> {,<shift>}

; R

RFl

ags

nm

shif

ted

"/

^h

teq<c><q> <Rn>, <Rm> {,<shift>}

; R

RFl

ags

nm

shif

ted

"5

^h

cmp<c><q> <Rn>, #<const>

; R

con

stFl

ags

n"

-^

hcmn<c><q> <Rn>, #<const>

; R

con

stFl

ags

n"

+^

htst<c><q> <Rn>, #<const>

; R

con

stFl

ags

n"

/^

hteq<c><q> <Rn>, #<const>

; R

con

stFl

ags

n"

5^

h

This

exh

aust

s th

e si

mp

le

ALU

fro

m

chap

ter

1 …

107

Har

dw

are/

Soft

war

e In

terf

ace

© 2

019

Uw

e R

. Zim

mer

, The

Aus

tral

ian

Nat

iona

l Uni

vers

ity

page

107

of 4

81 (c

hapt

er 2

: “H

ardw

are/

Softw

are

Inte

rfac

e” u

p to

pag

e 15

0)

Num

eric

CPU

sta

tus

fl ag

s

0N

atur

al b

inar

y nu

mbe

rs2n -1

ab

a+b

Car

ry

Wra

p-ar

ound

or

mod

ulo

2n

2's

com

plem

ent b

inar

y nu

mbe

rs

02n-

1 -1a

ba+

b

Ove

rflow

Wra

p-ar

ound

-2n-

1c

2c

Ove

rflow

0a

ba+

b

Satu

rate

c

Satu

rate

2c

d2d

Wh

ich

of t

ho

se

op

erat

ion

s w

ill

set w

hic

h fl

ag?

adds

adcs

qadd

114

Har

dw

are/

Soft

war

e In

terf

ace

© 2

019

Uw

e R

. Zim

mer

, The

Aus

tral

ian

Nat

iona

l Uni

vers

ity

page

114

of 4

81 (c

hapt

er 2

: “H

ardw

are/

Softw

are

Inte

rfac

e” u

p to

pag

e 15

0)

Sim

ple

arit

hmet

ic in

side

the

CPU

Cal

cula

te:

e := a + b - 2*c

assu

min

g al

l typ

es a

re 3

2 b

it 2

’s c

om

ple

men

t nu

mb

ers

(Integer

),r1

ho

lds a,

r2

ho

lds b,

r3

ho

lds c,

an

d th

e re

sult

s sh

ou

ld b

e in

r4.

add

r5, r1, r2

lsl

r6, r3, #1

; you could also write: mov r6, r3, lsl #1

sub

r4, r5, r6

We

nee

d te

mp

ora

ry s

tora

ge (r

5, r6)

in th

e p

roce

ss a

s w

e d

idn

’t w

ant t

o o

ver-

wri

te th

e o

rigi

nal

val

ues

. Yet

the

tota

l nu

mb

er o

f reg

iste

rs is

alw

ays

limit

ed.

111

Har

dw

are/

Soft

war

e In

terf

ace

© 2

019

Uw

e R

. Zim

mer

, The

Aus

tral

ian

Nat

iona

l Uni

vers

ity

page

111

of 4

81 (c

hapt

er 2

: “H

ardw

are/

Softw

are

Inte

rfac

e” u

p to

pag

e 15

0)

AR

M v

7-M

Mov

e da

ta in

side

the

CPU

mov{s}<c><q> <Rd>, <Rm>

mov{s}<c><q> <Rd>, #<const>

; Rd := Rm

; Rd := const

lsr{s}<c><q> <Rd>, <Rm>, #<n>

lsr{s}<c><q> <Rd>, <Rm>, <Rs>

; 0

00

3130

2928

2726

2524

2322

2120

1918

1716

xx

xx

xx

xx

xx

xx

xx

xx

1514

1312

1110

98

76

54

32

10

xx

xx

xx

xx

xx

xx

x.

.

xx

xx

xx

xx

xx

xx

xx

xx

xx

xx

xx

xx

xx

xx

x

C . cn

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxccccc

ccccc

asr{s}<c><q> <Rd>, <Rm>, #<n>

asr{s}<c><q> <Rd>, <Rm>, <Rs>

; s

ss

3130

2928

2726

2524

2322

2120

1918

1716

sx

xx

xx

xx

xx

xx

xx

xx

1514

1312

1110

98

76

54

32

10

xx

xx

xx

xx

xx

xx

xc

..

sx

xx

xx

xx

xx

xx

xx

xx

xx

xx

xx

xx

xx

xx

x

C . cn

ssssssxxxxx

xxxxxxxxxx

xxxxxxxxxx

xxxxxxxxxx

xxxxxxxxxx

xxxxxxxxxx

xxxxxxxxxx

xxxxxxxxxx

xxxxxxxxxx

xxxxxxxxxx

xxxxxxxxxx

xxxxxxxxxx

xxxxxxxxxx

xxxxxxxxxx

xxxxx

ssssxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxcccc

ccccc

lsl{s}<c><q> <Rd>, <Rm>, #<n>

lsl{s}<c><q> <Rd>, <Rm>, <Rs>

; 0

00

3130

2928

2726

2524

2322

2120

1918

1716

xx

xx

xx

xx

xx

xx

xx

xx

1514

1312

1110

98

76

54

32

10

xx

xx

xx

xx

xx

xx

x.

.

xx

xx

xx

xx

xx

xx

xx

xx

xx

xx

xx

xx

xx

xx

x

C .n

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxccccc

ccccc

ror{s}<c><q> <Rd>, <Rm>, #<n>

ror{s}<c><q> <Rd>, <Rm>, <Rs>

; c

ba

3130

2928

2726

2524

2322

2120

1918

1716

xx

xx

xx

xx

xx

xx

xx

xx

1514

1312

1110

98

76

54

32

10

xx

xx

xx

xx

xx

xx

xc

ba

xx

xx

xx

xx

xx

xx

xx

xx

xx

xx

xx

xx

xx

xx

x

C .ccccc

bbbbbbaaaaa

nxxxxx

xxxxxxxxxx

xxxxxxxxxx

xxxxxxxxxx

xxxxxxxxxx

xxxxxxxxxx

xxxxxxxxxx

xxxxxxxxxx

xxxxxxxxxx

xxxxxxxxxx

xxxxxxxxxx

xxxxxxxxxx

xxxxxxxxxx

xxxxxxxxxx

xxxxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxcccccc

cccccbbbbbb

aaaaa

rrx{s}<c><q> <Rd>, <Rm>

; x

x

3130

2928

2726

2524

2322

2120

1918

1716

xx

xx

xx

xx

xx

xx

xx

xx

1514

1312

1110

98

76

54

32

10

xx

xx

xx

xx

xx

xx

xx

xy

xx

xx

xx

xx

xx

xx

xx

xx

xx

xx

xx

xx

xx

xx

x

C y

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxx

xxxxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxxxx

xxxxxyyyyyyy

yyyyyyycccccc

ccccc

108

Har

dw

are/

Soft

war

e In

terf

ace

© 2

019

Uw

e R

. Zim

mer

, The

Aus

tral

ian

Nat

iona

l Uni

vers

ity

page

108

of 4

81 (c

hapt

er 2

: “H

ardw

are/

Softw

are

Inte

rfac

e” u

p to

pag

e 15

0)

AR

M v

7-M

32

bit A

ddit

ion,

Sub

trac

tion

inst

ruct

ions

add{s}<c><q> {<Rd>,} <Rn>, <Rm> {,<shift>}

; Rd := Rn + Rm(shifted)

adc{s}<c><q> {<Rd>,} <Rn>, <Rm> {,<shift>}

; Rd := Rn + Rm(shifted) + C

add{s}<c><q> {<Rd>,} <Rn>, #<const>

; Rd := Rn + #<const>

adc{s}<c><q> {<Rd>,} <Rn>, #<const>

; Rd := Rn + #<const> + C

qadd<c><q> {<Rd>,} <Rn>, <Rm>

; Rd := Rn + Rm ; saturated

sub{s}<c><q> {<Rd>,} <Rn>, <Rm> {,<shift>}

; Rd := Rn - Rm(shifted)

sbc{s}<c><q> {<Rd>,} <Rn>, <Rm> {,<shift>}

; Rd := Rn - Rm(shifted) - NOT (C)

rsb{s}<c><q> {<Rd>,} <Rn>, <Rm> {,<shift>}

; Rd := Rm(shifted) - Rn

sub{s}<c><q> {<Rd>,} <Rn>, #<const>

; Rd := Rn - #<const>

sbc{s}<c><q> {<Rd>,} <Rn>, #<const>

; Rd := Rn - #<const> - NOT (C)

rsb{s}<c><q> {<Rd>,} <Rn>, #<const>

; Rd := #<const> - Rn

qsub<c><q> {<Rd>,} Rn, Rm

; Rd := Rn - Rm ; saturated

All

inst

ruct

ion

s o

per

ate

on

32

bit

wid

e n

um

ber

s.

… v

ersi

on

s fo

r n

arro

wer

nu

mb

ers,

as

wel

l as

vers

ion

s w

hic

h o

per

ate

on

mu

ltip

le n

arro

wer

nu

mb

ers

in p

aral

lel e

xist

as

wel

l.

Page 3: COPE-02 Hardware/Software Interface...103 Hardware/Software Interface © 2019 Uwe R. Zimmer, The Australian National University page 103 of 481 (chapter 2: “Hardware/Software Interface”

121

Har

dw

are/

Soft

war

e In

terf

ace

© 2

019

Uw

e R

. Zim

mer

, The

Aus

tral

ian

Nat

iona

l Uni

vers

ity

page

121

of 4

81 (c

hapt

er 2

: “H

ardw

are/

Softw

are

Inte

rfac

e” u

p to

pag

e 15

0)

AR

M v

7-M

Cop

y da

ta in

and

out

of t

he C

PU

ssss eeessssssssssssssceeeeeeeeeeeeeeeeeeeeeeee

Rb

- Add

ress

ssssssseeeeeeee

Mem

ory

cell

Rd

- D

estin

atio

n

In it

s m

ost

bas

ic fo

rm th

e va

lue

of a

reg

iste

r is

inte

rpre

ted

as

an

addr

ess

and

the

mem

ory

cont

ent t

her

e is

load

ed in

to a

no

ther

reg

iste

r.

ec pspac

AAAddre ddpa

Yet:

mo

st d

ata

is s

tru

ctu

red

.

… li

ke a

gro

up

of l

oca

l var

iab

les,

a r

eco

rd, a

n

arra

y an

d a

ny

com

bin

atio

n o

f th

e ab

ove

Ho

w to

rea

d a

n e

ntr

y in

an

arr

ay/r

eco

rd?

118

Har

dw

are/

Soft

war

e In

terf

ace

© 2

019

Uw

e R

. Zim

mer

, The

Aus

tral

ian

Nat

iona

l Uni

vers

ity

page

118

of 4

81 (c

hapt

er 2

: “H

ardw

are/

Softw

are

Inte

rfac

e” u

p to

pag

e 15

0)

Sim

ple

arit

hmet

ic in

side

the

CPU

Cal

cula

te:

e := a + b - 2*c

We

nee

d to

ch

eck

resu

lts

afte

r ea

ch s

tep

:

adds

r1, r1, r2

; need to check overflow flag

lsl

r3, r3, #1

; need to check that the sign did not change

subs

r4, r1, r3

; need to check overflow flag again

We

do

n’t

hav

e th

e m

ean

s ye

t to

bra

nch

off

into

dif

fere

nt

acti

on

s in

cas

e th

ings

go

bad

… to

co

me

soo

n.

Or

we

use

sat

ura

tio

n a

rith

met

ic a

nd

live

wit

h th

e er

ror:

qadd

r1, r1, r2

qadd

r3, r3, r3

qsub

r4, r1, r3

If w

e kn

ow

we

nee

d to

car

ry o

n e

ith

er w

ay, t

his

at

leas

t min

imiz

es th

e lo

cal e

rro

rs.

115

Har

dw

are/

Soft

war

e In

terf

ace

© 2

019

Uw

e R

. Zim

mer

, The

Aus

tral

ian

Nat

iona

l Uni

vers

ity

page

115

of 4

81 (c

hapt

er 2

: “H

ardw

are/

Softw

are

Inte

rfac

e” u

p to

pag

e 15

0)

Sim

ple

arit

hmet

ic in

side

the

CPU

Cal

cula

te:

e := a + b - 2*c

assu

min

g al

l typ

es a

re 3

2 b

it 2

’s c

om

ple

men

t nu

mb

ers

(Integer

),r1

ho

lds a,

r2

ho

lds b,

r3

ho

lds c,

an

d th

e re

sult

s sh

ou

ld b

e in

r4.

add

r5, r1, r2

lsl

r6, r3, #1

; you could also write: mov r6, r3, lsl #1

sub

r4, r5, r6

We

nee

d te

mp

ora

ry s

tora

ge (r

5, r6)

in th

e p

roce

ss a

s w

e d

idn

’t w

ant t

o o

ver-

wri

te th

e o

rigi

nal

val

ues

. Yet

the

tota

l nu

mb

er o

f reg

iste

rs is

alw

ays

limit

ed.

Ho

w a

bo

ut w

e as

sum

e th

at v

alu

es a

re n

o lo

nge

r n

eed

ed a

fter

this

exp

ress

ion

:

122

Har

dw

are/

Soft

war

e In

terf

ace

© 2

019

Uw

e R

. Zim

mer

, The

Aus

tral

ian

Nat

iona

l Uni

vers

ity

page

122

of 4

81 (c

hapt

er 2

: “H

ardw

are/

Softw

are

Inte

rfac

e” u

p to

pag

e 15

0)

AR

M v

7-M

Cop

y da

ta in

and

out

of t

he C

PUssss AAAAAddddree dddesssssssssssss ddddddddddddddddddrrr dddddddddd

psssspppppppce peeeeeeeeeeeee aaaaaaaaaacaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaR

b -

Bas

e ad

dres

s

ssssssseeee

Bas

e m

emor

y ce

ll

Ri o

r co

nst -

Inde

x

ddddrr daaaaaaaaaaaaaaaaaaaaaaaaa

Inde

xed

mem

ory

cell

Rd

- D

estin

atio

nW

rite

-bac

k

+

Mo

st c

op

y o

per

atio

ns

bet

wee

n C

PU a

nd

m

emo

ry fo

llow

this

bas

ic s

chem

e.

119

Har

dw

are/

Soft

war

e In

terf

ace

© 2

019

Uw

e R

. Zim

mer

, The

Aus

tral

ian

Nat

iona

l Uni

vers

ity

page

119

of 4

81 (c

hapt

er 2

: “H

ardw

are/

Softw

are

Inte

rfac

e” u

p to

pag

e 15

0)

Cor

tex-

M4

Add

ress

Spa

ce

You

r C

PU h

as 3

2 b

it o

f ad

dre

ss s

pac

e 4

GB

… a

dd

ress

sp

ace

do

es n

ot e

qu

ate

to p

hys

ical

mem

ory

!

No

t all

mem

ory

is e

qu

al: S

om

e m

emo

ry …

… c

an b

e ex

ecut

ed…

can

be

wri

tten

to

or

read

from

or

both

… h

as s

ide-

effe

cts

(co

ffee

cu

ps

fall

ove

r)…

has

str

ictl

y-or

dere

d ac

cess

… d

oes

not

phys

ical

ly e

xist

A

16#0

0000

000#

16#1

FFFF

FFF#

16#3

FFFF

FFF#

16#2

0000

000#

16#5

FFFF

FFF#

16#4

0000

000#

16#9

FFFF

FFF#

16#6

0000

000#

16#D

FFFF

FFF#

16#A

0000

000#

16#E

00FF

FFF#

16#E

0000

000#

16#F

FFFF

FF#

16#E

0100

000#

Cod

e

AAA

SRA

M

Peri

pher

al

dddddddddrrreeeeppppppaaaaaccce aaaaa

Exte

rnal

RA

M

eessssssseeeeeee

Exte

rnal

dev

ice

Priv

ate

peri

pher

al b

us

Ven

dor-

spec

ific

mem

ory

0.5 GB

0.5 GB

0.5 GB

1 GB

1 GB

1 MB

511 MB

116

Har

dw

are/

Soft

war

e In

terf

ace

© 2

019

Uw

e R

. Zim

mer

, The

Aus

tral

ian

Nat

iona

l Uni

vers

ity

page

116

of 4

81 (c

hapt

er 2

: “H

ardw

are/

Softw

are

Inte

rfac

e” u

p to

pag

e 15

0)

Sim

ple

arit

hmet

ic in

side

the

CPU

Cal

cula

te:

e := a + b - 2*c

assu

min

g al

l typ

es a

re 3

2 b

it 2

’s c

om

ple

men

t nu

mb

ers

(Integer

),r1

ho

lds a,

r2

ho

lds b,

r3

ho

lds c,

an

d th

e re

sult

s sh

ou

ld b

e in

r4.

add

r5, r1, r2

lsl

r6, r3, #1

; you could also write: mov r6, r3, lsl #1

sub

r4, r5, r6

We

nee

d te

mp

ora

ry s

tora

ge (r

5, r6)

in th

e p

roce

ss a

s w

e d

idn

’t w

ant t

o o

ver-

wri

te th

e o

rigi

nal

val

ues

. Yet

the

tota

l nu

mb

er o

f reg

iste

rs is

alw

ays

limit

ed.

Ho

w a

bo

ut w

e as

sum

e th

at v

alu

es a

re n

o lo

nge

r n

eed

ed a

fter

this

exp

ress

ion

:

add

r1, r1, r2

lsl

r3, r3, #1

sub

r4, r1, r3

… y

ou

r co

mp

iler

will

kn

ow

wh

en s

uch

sid

e-ef

fect

s ar

e o

k an

d w

hen

no

t.

An

y o

verfl

ow

s?

123

Har

dw

are/

Soft

war

e In

terf

ace

© 2

019

Uw

e R

. Zim

mer

, The

Aus

tral

ian

Nat

iona

l Uni

vers

ity

page

123

of 4

81 (c

hapt

er 2

: “H

ardw

are/

Softw

are

Inte

rfac

e” u

p to

pag

e 15

0)

AR

M v

7-M

Mov

e da

ta in

and

out

of t

he C

PU

ssss AAAAAddddree dddessssssssssssss ddddddddddddddddddddrrr ddddddddddpsssspppppppce peeeeeeeeeeeee aaaaaaaaaacaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa

Rb

- B

ase

addr

ess

ssssssseeee

Bas

e m

emor

y ce

ll

offs

et

ddddrr daaaaaaaaaaaaaaaaaaaaaaaaa

Offs

et m

emor

y ce

llR

d -

Des

tinat

ion

+

ldr<c><q> <Rd>, [<Rb> {, #+/-<offset>}]

str<c><q> <Rs>, [<Rb> {, #+/-<offset>}]

Rea

ds

fro

m a

po

ten

tial

ly o

ffse

t mem

ory

cel

l wit

h a

bas

e re

gist

er a

dd

ress

.

Imm

edia

te a

dd

ress

ing

ldr r1, [r4]

ldr r1, [r4, #8]

120

Har

dw

are/

Soft

war

e In

terf

ace

© 2

019

Uw

e R

. Zim

mer

, The

Aus

tral

ian

Nat

iona

l Uni

vers

ity

page

120

of 4

81 (c

hapt

er 2

: “H

ardw

are/

Softw

are

Inte

rfac

e” u

p to

pag

e 15

0)

AR

M v

7-M

Cop

y da

ta in

and

out

of t

he C

PU

ssss AAAAAddddrrree ddddesssssssssssspsssspppppppaace paaeeeeeeeeeeeeeeeeeeeeee

Rb

- Add

ress

ssssssseeeeeeee

Mem

ory

cell

Rd

- D

estin

atio

n

In it

s m

ost

bas

ic fo

rm th

e va

lue

of a

reg

iste

r is

inte

rpre

ted

as

an

addr

ess

and

the

mem

ory

cont

ent t

her

e is

load

ed in

to a

no

ther

reg

iste

r.

117

Har

dw

are/

Soft

war

e In

terf

ace

© 2

019

Uw

e R

. Zim

mer

, The

Aus

tral

ian

Nat

iona

l Uni

vers

ity

page

117

of 4

81 (c

hapt

er 2

: “H

ardw

are/

Softw

are

Inte

rfac

e” u

p to

pag

e 15

0)

Sim

ple

arit

hmet

ic in

side

the

CPU

Cal

cula

te:

e := a + b - 2*c

We

nee

d to

ch

eck

resu

lts

afte

r ea

ch s

tep

:

adds

r1, r1, r2

; need to check overflow flag

lsl

r3, r3, #1

; need to check that the sign did not change

subs

r4, r1, r3

; need to check overflow flag again

We

do

n’t

hav

e th

e m

ean

s ye

t to

bra

nch

off

into

dif

fere

nt

acti

on

s in

cas

e th

ings

go

bad

… to

co

me

soo

n.

Page 4: COPE-02 Hardware/Software Interface...103 Hardware/Software Interface © 2019 Uwe R. Zimmer, The Australian National University page 103 of 481 (chapter 2: “Hardware/Software Interface”

130

Har

dw

are/

Soft

war

e In

terf

ace

© 2

019

Uw

e R

. Zim

mer

, The

Aus

tral

ian

Nat

iona

l Uni

vers

ity

page

130

of 4

81 (c

hapt

er 2

: “H

ardw

are/

Softw

are

Inte

rfac

e” u

p to

pag

e 15

0)

AR

M v

7-M

Mov

e da

ta in

and

out

of t

he C

PU

ssss AAAAAddddree dddessssssssssssss ddddddddddddddddddrrr ddddddddddpsssspppppppce peeeeeeeeeeeee aaaaaaaaaacaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa

Rb

- B

ase

addr

ess

ssssssseeee

Bas

e m

emor

y ce

ll

Ri -

Inde

x {s

hifte

d}

ddddddddrrr daaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa

Offs

et m

emor

y ce

llR

s -

Sour

ce

+

ldr<c><q> <Rd>, [<Rb>, <Ri> {, LSL #<shift>}]

str<c><q> <Rs>, [<Rb>, <Ri> {, LSL #<shift>}]

Wri

tes

to a

mem

ory

cel

l wit

h a

bas

e re

gist

er a

dd

ress

plu

s a

po

ten

tial

ly s

hif

ted

ind

ex r

egis

ter.

Ind

ex r

egis

ter

add

ress

ing

str r1, [r4, r3]

ill

hif

di

di

str r1, [r4, r3, LSL #2]

127

Har

dw

are/

Soft

war

e In

terf

ace

© 2

019

Uw

e R

. Zim

mer

, The

Aus

tral

ian

Nat

iona

l Uni

vers

ity

page

127

of 4

81 (c

hapt

er 2

: “H

ardw

are/

Softw

are

Inte

rfac

e” u

p to

pag

e 15

0)

AR

M v

7-M

Mov

e da

ta in

and

out

of t

he C

PU

ssss AAAAAddddree dddessssssssssss dddddddddddddddddddrrr ddddddddddpsssspppppppce peeeeeeeeee aaaaaaaaaaaaaaaaaaaacaaaaaaaaaeeeeeeeeeeee

Rb

- B

ase

addr

ess

ssssssseeeeeeee

Bas

e m

emor

y ce

ll

offs

et

ddddrr daaaaaaaaaaa

Offs

et m

emor

y ce

ll

Rd

- D

estin

atio

n

+

Wri

te-b

ack

ldr<c><q> <Rd>, [<Rb>], #+/-<offset>

str<c><q> <Rs>, [<Rb>], #+/-<offset>

Rea

ds

fro

m a

mem

ory

cel

l wit

h a

bas

e re

gist

er a

dd

ress

and

wri

tes

the

off

set a

dd

ress

bac

k in

to th

e o

rigi

nal

bas

e re

gist

er.

Imm

edia

te a

dd

ress

ing

(“Po

st-i

nd

exed

”)

ldr r1, [r4], #8

124

Har

dw

are/

Soft

war

e In

terf

ace

© 2

019

Uw

e R

. Zim

mer

, The

Aus

tral

ian

Nat

iona

l Uni

vers

ity

page

124

of 4

81 (c

hapt

er 2

: “H

ardw

are/

Softw

are

Inte

rfac

e” u

p to

pag

e 15

0)

AR

M v

7-M

Mov

e da

ta in

and

out

of t

he C

PU

ssss AAAAAddddree dddessssssssssss dddddddddddddddddddrrr dddddddddpsssspppppppce peeeeeeeeeeeee aaaaaaaaaaacaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa

Rb

- B

ase

addr

ess

sssssssseeee

Bas

e m

emor

y ce

ll

offs

et

ddddddddrrrr daaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa

Offs

et m

emor

y ce

llR

s -

Sour

ce

+

ldr<c><q> <Rd>, [<Rb> {, #+/-<offset>}]

str<c><q> <Rs>, [<Rb> {, #+/-<offset>}]

Wri

tes

to a

po

ten

tial

ly o

ffse

t mem

ory

cel

l wit

h a

bas

e re

gist

er a

dd

ress

.

Imm

edia

te a

dd

ress

ing

str r1, [r4, #-12]

str r1, [r4]

131

Har

dw

are/

Soft

war

e In

terf

ace

© 2

019

Uw

e R

. Zim

mer

, The

Aus

tral

ian

Nat

iona

l Uni

vers

ity

page

131

of 4

81 (c

hapt

er 2

: “H

ardw

are/

Softw

are

Inte

rfac

e” u

p to

pag

e 15

0)

AR

M v

7-M

Mov

e da

ta in

and

out

of t

he C

PUssss AAAAAddddree dddesssssssssssss ddddddddddddddddddrrr dddddddddd

psssspppppppce peeeeeeeeeeeee aaaaaaaaaacaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaPC

ssssssseeee

Cur

rent

inst

ruct

ion

offs

et

ddddrr daaaaaaaaaaaaaaaaaaaaaaaaa

Dat

a in

cod

eR

d -

Des

tinat

ion

+

<la

bel>

:

ldr<c><q> <Rd>, <label>

ldr<c><q> <Rd>, [PC, #+/-<offset>]

Rea

ds

fro

m a

dat

a ar

ea e

mb

edd

ed in

to th

e co

de

sect

ion

.

Lite

ral a

dd

ress

ing

No

te th

ere

is n

o

sto

re v

ersi

on

.

ldr r1, data

128

Har

dw

are/

Soft

war

e In

terf

ace

© 2

019

Uw

e R

. Zim

mer

, The

Aus

tral

ian

Nat

iona

l Uni

vers

ity

page

128

of 4

81 (c

hapt

er 2

: “H

ardw

are/

Softw

are

Inte

rfac

e” u

p to

pag

e 15

0)

AR

M v

7-M

Mov

e da

ta in

and

out

of t

he C

PU

ssss AAAAAddddree dddessssssssssss dddddddddddddddddddrrr ddddddddddpsssspppppppce peeeeeeeeee aaaaaaaaaaaaaaaaaaaacaaaaaaaaaeeeeeeeeeeee

Rb

- B

ase

addr

ess

ssssssssssssseeeeeeeeeeeeee

Bas

e m

emor

y ce

ll

offs

et

ddddrr daaaaaaaaaaa

Offs

et m

emor

y ce

ll

Rs

- So

urce

+

Wri

te-b

ack

ldr<c><q> <Rd>, [<Rb>], #+/-<offset>

str<c><q> <Rs>, [<Rb>], #+/-<offset>

Wri

tes

to a

mem

ory

cel

l wit

h a

bas

e re

gist

er a

dd

ress

and

wri

tes

the

off

set a

dd

ress

bac

k in

to th

e o

rigi

nal

bas

e re

gist

er.

Imm

edia

te a

dd

ress

ing

(“Po

st-i

nd

exed

”)

str r1, [r4], #8

125

Har

dw

are/

Soft

war

e In

terf

ace

© 2

019

Uw

e R

. Zim

mer

, The

Aus

tral

ian

Nat

iona

l Uni

vers

ity

page

125

of 4

81 (c

hapt

er 2

: “H

ardw

are/

Softw

are

Inte

rfac

e” u

p to

pag

e 15

0)

AR

M v

7-M

Mov

e da

ta in

and

out

of t

he C

PU

ssss AAAAAddddree dddessssssssssss dddddddddddddddddddrrr dddddddddpsssspppppppce peeeeeeeeeeeee aaaaaaaaaaacaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa

Rb

- B

ase

addr

ess

sssssssseeee

Bas

e m

emor

y ce

ll

offs

et

ddddrrr daaaaaaaaaaaaaaaaaaaaaaa

Offs

et m

emor

y ce

llR

d -

Des

tinat

ion

+

Wri

te-b

ack

ldr<c><q> <Rd>, [<Rb>, #+/-<offset>]!

str<c><q> <Rs>, [<Rb>, #+/-<offset>]!

Rea

ds

fro

m a

n o

ffse

t mem

ory

cel

l wit

h a

bas

e re

gist

er a

dd

ress

and

wri

tes

the

off

set a

dd

ress

bac

k in

to th

e o

rigi

nal

bas

e re

gist

er.

Imm

edia

te a

dd

ress

ing

(“Pr

e-in

dex

ed”)

ldr r1, [r4, #8]!

132

Har

dw

are/

Soft

war

e In

terf

ace

© 2

019

Uw

e R

. Zim

mer

, The

Aus

tral

ian

Nat

iona

l Uni

vers

ity

page

132

of 4

81 (c

hapt

er 2

: “H

ardw

are/

Softw

are

Inte

rfac

e” u

p to

pag

e 15

0)

AR

M v

7-M

Mov

e da

ta in

and

out

of t

he C

PU

ssss AAAs AAddddee ddddrrrrrrrrrrreeeesssssssssssssspsssspppppppace paaaaaaaacccccceeeeeeeeeee aaaaaccccccccccccccccceeeeeeeeeeee

Rs

- St

ack

addr

ess

rrrrrrreeeeeeeeeeecccccccccccccccccccccccccccccccccccc

Rel

ativ

e ce

ll n

Rz

- So

urce

sssssssssssseeeeeeeeeeeeee

Rel

ativ

e ce

ll 1

Rx

- So

urce

Wri

te-b

ack

……

stmia<c><q> <Rs>{!}, <registers>

ldmdb<c><q> <Rs>{!}, <registers>

Sto

res

mu

ltip

le r

egis

ters

into

seq

uen

tial

mem

ory

ad

dre

sses

.St

ore

s “i

ncr

emen

t aft

er”

and

load

s “d

ecre

men

t bef

ore

”.

Mu

ltip

le r

egis

ters

(po

siti

ve g

row

ing

stac

k)

stmia r9!, {r1, r3, r4, fp}

129

Har

dw

are/

Soft

war

e In

terf

ace

© 2

019

Uw

e R

. Zim

mer

, The

Aus

tral

ian

Nat

iona

l Uni

vers

ity

page

129

of 4

81 (c

hapt

er 2

: “H

ardw

are/

Softw

are

Inte

rfac

e” u

p to

pag

e 15

0)

AR

M v

7-M

Mov

e da

ta in

and

out

of t

he C

PU

ssss AAAAAddddree dddessssssssssss ddddddddddddddddddrrr dddddddddpsssspppppppce peeeeeeeeeeeee aaaaaaaaacaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa

Rb

- B

ase

addr

ess

ssssssseeee

Bas

e m

emor

y ce

ll

Ri -

Inde

x {s

hifte

d}

ddddrr daaaaaaaaaaaaaaaaaaaaa

Offs

et m

emor

y ce

llR

d -

Des

tinat

ion

+

ldr<c><q> <Rd>, [<Rb>, <Ri> {, LSL #<shift>}]

str<c><q> <Rs>, [<Rb>, <Ri> {, LSL #<shift>}]

Rea

ds

fro

m a

mem

ory

cel

l wit

h a

bas

e re

gist

er a

dd

ress

plu

s a

po

ten

tial

ly s

hif

ted

ind

ex r

egis

ter.

Ind

ex r

egis

ter

add

ress

ing

ldr r1, [r4, r3]

ill

hif

di

di

ldr r1, [r4, r3, LSL #2]

126

Har

dw

are/

Soft

war

e In

terf

ace

© 2

019

Uw

e R

. Zim

mer

, The

Aus

tral

ian

Nat

iona

l Uni

vers

ity

page

126

of 4

81 (c

hapt

er 2

: “H

ardw

are/

Softw

are

Inte

rfac

e” u

p to

pag

e 15

0)

AR

M v

7-M

Mov

e da

ta in

and

out

of t

he C

PU

ssss AAAAAddddree dddessssssssssss ddddddddddddddddddddrrr dddddddddpsssspppppppce peeeeeeeeeeeee aaaaaaaaaaacaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa

Rb

- B

ase

addr

ess

sssssssseeee

Bas

e m

emor

y ce

ll

offs

et

ddddddddrrrr daaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa

Offs

et m

emor

y ce

llR

s -

Sour

ce

+

Wri

te-b

ack

ldr<c><q> <Rd>, [<Rb>, #+/-<offset>]!

str<c><q> <Rs>, [<Rb>, #+/-<offset>]!

Wri

tes

to a

n o

ffse

t mem

ory

cel

l wit

h a

bas

e re

gist

er a

dd

ress

and

wri

tes

the

off

set a

dd

ress

bac

k in

to th

e o

rigi

nal

bas

e re

gist

er.

Imm

edia

te a

dd

ress

ing

(“Pr

e-in

dex

ed”)

str r1, [r4, #-12]!

Page 5: COPE-02 Hardware/Software Interface...103 Hardware/Software Interface © 2019 Uwe R. Zimmer, The Australian National University page 103 of 481 (chapter 2: “Hardware/Software Interface”

139

Har

dw

are/

Soft

war

e In

terf

ace

© 2

019

Uw

e R

. Zim

mer

, The

Aus

tral

ian

Nat

iona

l Uni

vers

ity

page

139

of 4

81 (c

hapt

er 2

: “H

ardw

are/

Softw

are

Inte

rfac

e” u

p to

pag

e 15

0)

AR

M v

7-M

Bra

nch

inst

ruct

ions

b<c><q> <label>

; if c then PC := label

bl<c> <label>

; if c then LR := PC_next; PC := label

bx<c> <Rm>

; if c then PC := Rm

blx<c><q> <Rm>

; if c then LR := PC_next; PC := Rm

cbz<q> <Rn>, <label>

; if Rn = 0 then PC := label

cbnz<q> <Rn>, <label>

; if Rn /= 0 then PC := label

<c>

Mea

nin

gsFlags

eqEq

ual

Z = 1

neN

ot e

qu

alZ

= 0

cs, hs

Car

ry s

et, U

nsi

gned

hig

her

or

sam

eC

= 1

cc, lo

Car

ry c

lear

, Un

sign

ed lo

wer

C = 0

miM

inu

s, N

egat

ive

N = 1

plPl

us,

Po

siti

ve o

r ze

roN

= 0

vsO

verfl

ow

V = 1

vcN

o o

verfl

ow

V = 0

hiU

nsi

gned

hig

her

C = 1 /

Z =

0ls

Un

sign

ed lo

wer

or

sam

eC

= 0 0

Z =

1ge

Sign

ed g

reat

er o

r eq

ual

N = Z

ltSi

gned

less

N ! Z

gtSi

gned

gre

ater

Z

= 0 /

N =

Vle

Sign

ed le

ss o

r eq

ual

Z = 1 0

N !

Val, <none>

Alw

ays

any

136

Har

dw

are/

Soft

war

e In

terf

ace

© 2

019

Uw

e R

. Zim

mer

, The

Aus

tral

ian

Nat

iona

l Uni

vers

ity

page

136

of 4

81 (c

hapt

er 2

: “H

ardw

are/

Softw

are

Inte

rfac

e” u

p to

pag

e 15

0)

Sim

ple

arit

hmet

ic in

mem

ory

Cal

cula

te a

gain

:

e := a + b - 2*c

bu

t no

w a

, b, c

an

d e

are

sto

red

in m

emo

ry, r

elat

ive

to a

n a

dd

ress

sto

red

in FP

(“Fr

ame

Poin

ter”

):a

is h

eld

at [

fp - 12]

, b a

t [fp - 16]

, c a

t [fp - 20]

an

d e

at [

fp - 24]

In o

rder

to d

o a

rith

met

ic w

e n

eed

to lo

ad th

ose

val

ues

into

the

CPU

fi

rst a

nd

aft

erw

ard

s w

e n

eed

to s

tore

the

resu

lt in

mem

ory

:

ldr

r1, [fp, #-12]

ldr

r2, [fp, #-16]

add

r1, r1, r2

ldr

r2, [fp, #-20]

lsl

r2, r2, #1

sub

r1, r1, r2

str

r1, [fp, #-24]

No

tice

that

this

tim

e w

e o

nly

use

d tw

o r

egis

ters

.

133

Har

dw

are/

Soft

war

e In

terf

ace

© 2

019

Uw

e R

. Zim

mer

, The

Aus

tral

ian

Nat

iona

l Uni

vers

ity

page

133

of 4

81 (c

hapt

er 2

: “H

ardw

are/

Softw

are

Inte

rfac

e” u

p to

pag

e 15

0)

AR

M v

7-M

Mov

e da

ta in

and

out

of t

he C

PU

ssss AAAAAddddee ddddrrrrrrrrrreeeesssssssssssspsssspppppppae paaaaaaacccccceeeeeeeee aaaaacccccccccccccccceeeeeeeeeeee

Rs

- St

ack

addr

ess

rrrreeeeeeeecccccccccccccccccccccc

Rel

ativ

e ce

ll n

Rz

- D

estin

atio

n

sssssssseeeeeeee

Rel

ativ

e ce

ll 1

Rx

- D

estin

atio

nW

rite

-bac

k

……

stmia<c><q> <Rs>{!}, <registers>

ldmdb<c><q> <Rs>{!}, <registers>

Rea

ds

mu

ltip

le r

egis

ters

fro

m s

equ

enti

al m

emo

ry a

dd

ress

es.

Sto

res

“in

crem

ent a

fter

” an

d lo

ads

“dec

rem

ent b

efo

re”.

Mu

ltip

le r

egis

ters

(po

siti

ve g

row

ing

stac

k)

No

te th

at a

ny

regi

ster

can

be

use

as

stac

k b

ase,

i.e

. yo

u c

an h

ave

mu

ltip

le s

tack

s si

mu

ltan

eou

sly.

ldmdb r9!, {r1, r3, r4, fp}

140

Har

dw

are/

Soft

war

e In

terf

ace

© 2

019

Uw

e R

. Zim

mer

, The

Aus

tral

ian

Nat

iona

l Uni

vers

ity

page

140

of 4

81 (c

hapt

er 2

: “H

ardw

are/

Softw

are

Inte

rfac

e” u

p to

pag

e 15

0)

Sim

ple

arit

hmet

ic in

mem

ory

Cal

cula

te a

gain

:

e := a + b - 2*c

Or

wit

h o

verfl

ow

ch

ecks

:

ldr

r1, [fp, #-12]

ldr

r2, [fp, #-16]

adds

r1, r1, r2

bvs

Overflow

; branch if overflow is set

ldr

r2, [fp, #-20]

adds

r2, r2, r2

bvs

Overflow

; branch if overflow is set

subs

r1, r1, r2

bvs

Overflow

; branch if overflow is set

str

r1, [fp, #-24]

… Overflow:

svc

#5

; call the operating system or runtime environment with #5

; (assuming that #5 indicates an overflow situation)

137

Har

dw

are/

Soft

war

e In

terf

ace

© 2

019

Uw

e R

. Zim

mer

, The

Aus

tral

ian

Nat

iona

l Uni

vers

ity

page

137

of 4

81 (c

hapt

er 2

: “H

ardw

are/

Softw

are

Inte

rfac

e” u

p to

pag

e 15

0)

Sim

ple

arit

hmet

ic in

mem

ory

Cal

cula

te a

gain

:

e := a + b - 2*c

Or

in s

atu

rati

on

ari

thm

etic

:

ldr

r1, [fp, #-12]

ldr

r2, [fp, #-16]

qadd

r1, r1, r2

ldr

r2, [fp, #-20]

qadd

r2, r2, r2

qsub

r1, r1, r2

str

r1, [fp, #-24]

134

Har

dw

are/

Soft

war

e In

terf

ace

© 2

019

Uw

e R

. Zim

mer

, The

Aus

tral

ian

Nat

iona

l Uni

vers

ity

page

134

of 4

81 (c

hapt

er 2

: “H

ardw

are/

Softw

are

Inte

rfac

e” u

p to

pag

e 15

0)

AR

M v

7-M

Mov

e da

ta in

and

out

of t

he C

PU

ssss AAAAAddddee ddddrrrrrrrrrreeeesssssssssssspsssspppppppae paaaaaaacccccceeeeeeeee aaaaacccccccccccccccceeeeeeeeeeee

Rs

- St

ack

addr

ess

rrrrrreeeeeeeeeeecccccccccccccccccccccccccccccccccc

Rel

ativ

e ce

ll n

Rz

- So

urce

sssssssssssseeeeeeeeeeee

Rel

ativ

e ce

ll 1

Rx

- So

urce

Wri

te-b

ack

……

stmdb<c><q> <Rs>{!}, <registers>

ldmia<c><q> <Rs>{!}, <registers>

Sto

res

mu

ltip

le r

egis

ters

to s

equ

enti

al m

emo

ry a

dd

ress

es.

Sto

res

“dec

rem

ent b

efo

re”

and

load

s “i

ncr

emen

t aft

er”.

Mu

ltip

le r

egis

ters

(neg

ativ

e gr

ow

ing

stac

k)N

egat

ive

gro

win

g st

acks

are

the

de-

fact

o

stan

dar

d in

ind

ust

ry.

stmdb SP!, {r1, r3, r4, fp}

141

Har

dw

are/

Soft

war

e In

terf

ace

© 2

019

Uw

e R

. Zim

mer

, The

Aus

tral

ian

Nat

iona

l Uni

vers

ity

page

141

of 4

81 (c

hapt

er 2

: “H

ardw

are/

Softw

are

Inte

rfac

e” u

p to

pag

e 15

0)

Sim

ple

arit

hmet

ic in

mem

ory

Cal

cula

te a

gain

:

e := a + b - 2*c

Or

wit

h o

verfl

ow

ch

ecks

:

ldr

r1, [fp, #-12]

ldr

r2, [fp, #-16]

adds

r1, r1, r2

bvs

Overflow

; branch if overflow is set

ldr

r2, [fp, #-20]

adds

r2, r2, r2

bvs

Overflow

; branch if overflow is set

subs

r1, r1, r2

bvs

Overflow

; branch if overflow is set

str

r1, [fp, #-24]

… Overflow:

svc

#5

; call the operating system or runtime environment with #5

; (assuming that #5 indicates an overflow situation)

… b

ut h

ow

do

we

kno

w

wh

ere

this

hap

pen

ed o

r h

ow

to

co

nti

nu

e o

per

atio

ns?

138

Har

dw

are/

Soft

war

e In

terf

ace

© 2

019

Uw

e R

. Zim

mer

, The

Aus

tral

ian

Nat

iona

l Uni

vers

ity

page

138

of 4

81 (c

hapt

er 2

: “H

ardw

are/

Softw

are

Inte

rfac

e” u

p to

pag

e 15

0)

Sim

ple

arit

hmet

ic in

mem

ory

Cal

cula

te a

gain

:

e := a + b - 2*c

Or

wit

h o

verfl

ow

ch

ecks

:

ldr

r1, [fp, #-12]

ldr

r2, [fp, #-16]

adds

r1, r1, r2

; need to check overflow flag

ldr

r2, [fp, #-20]

lsl

r2, r2, #1

; need to check that the sign did not change

subs

r1, r1, r2

; need to check overflow flag

str

r1, [fp, #-24]

It’s

tim

e w

e le

arn

ab

ou

t bra

nch

ing

off

into

al

tern

ativ

e ex

ecu

tio

n p

ath

s.

135

Har

dw

are/

Soft

war

e In

terf

ace

© 2

019

Uw

e R

. Zim

mer

, The

Aus

tral

ian

Nat

iona

l Uni

vers

ity

page

135

of 4

81 (c

hapt

er 2

: “H

ardw

are/

Softw

are

Inte

rfac

e” u

p to

pag

e 15

0)

AR

M v

7-M

Mov

e da

ta in

and

out

of t

he C

PU

ssss AAAAAddddee ddddrrrrrrrrrreeeesssssssssssspsssspppppppae paaaaaaacccccceeeeeeeee aaaaaccccccccccccccceeeeeeeeeeee

Rs

- St

ack

addr

ess

rrrreeeeeeeecccccccccccccccccccccc

Rel

ativ

e ce

ll n

Rz

- D

estin

atio

n

sssssssseeeeeeee

Rel

ativ

e ce

ll 1

Rx

- D

estin

atio

n

Wri

te-b

ack

……

stmdb<c><q> <Rs>{!}, <registers>

ldmia<c><q> <Rs>{!}, <registers>

Rea

ds

mu

ltip

le r

egis

ters

fro

m s

equ

enti

al m

emo

ry a

dd

ress

es.

Sto

res

“dec

rem

ent b

efo

re”

and

load

s “i

ncr

emen

t aft

er”.

Mu

ltip

le r

egis

ters

(neg

ativ

e gr

ow

ing

stac

k)

ldmia SP!, {r1, r3, r4, fp}

Page 6: COPE-02 Hardware/Software Interface...103 Hardware/Software Interface © 2019 Uwe R. Zimmer, The Australian National University page 103 of 481 (chapter 2: “Hardware/Software Interface”

148

Har

dw

are/

Soft

war

e In

terf

ace

© 2

019

Uw

e R

. Zim

mer

, The

Aus

tral

ian

Nat

iona

l Uni

vers

ity

page

148

of 4

81 (c

hapt

er 2

: “H

ardw

are/

Softw

are

Inte

rfac

e” u

p to

pag

e 15

0)

Bas

ic in

stru

ctio

n se

ts

Cat

ego

rySi

de

effe

cts

ARM v7-M

Ari

thm

etic

, Lo

gic

Sets

an

d u

ses

CPU

fl ag

s

add, adc, qadd, sub, sbc, qsub, rsb,

mul, mla, mls, udiv, sdiv,

umull, umlal, smull, smlal,

and, bic, orr, orn, eor, cmp, cmn, tst, teq

Mo

ve a

nd

sh

ift

regi

ster

smov, lsr, asr, lsl, ror, rrx

Bra

nch

ing

Use

s C

PU fl

ags

b, bl, bx, blx, tbb, tbh

Load

& S

tore

Effe

cts

mem

ory

ldr, str, ldmdb, ldmia, stmia, stmdb

145

Har

dw

are/

Soft

war

e In

terf

ace

© 2

019

Uw

e R

. Zim

mer

, The

Aus

tral

ian

Nat

iona

l Uni

vers

ity

page

145

of 4

81 (c

hapt

er 2

: “H

ardw

are/

Softw

are

Inte

rfac

e” u

p to

pag

e 15

0)

Mor

e po

wer

Cal

cula

te:

c := a ^ b

mov

r1, #7

; a

mov

r2, #11

; b ; has to be non-negative

mov

r3, #1

; c

mov

r4, r1

; base a to the powers of two, starting with a ^ 1

power:

cbz

r2, end_power

; exponent zero?

tst

r2, #0b1

; right-most bit of exponent set?

beq

skip

; skip this power if not

mul

r3, r4

; multiply the current power into result

skip:

mul

r4, r4

; calculate next power

lsr

r2, #1

; divide exponent by 2

b

power

end_power:

nop

; c = a ^ b

Ho

w m

any

iter

atio

ns?

Ho

w m

any

cycl

es?

77

77

118

21

$$

=

142

Har

dw

are/

Soft

war

e In

terf

ace

© 2

019

Uw

e R

. Zim

mer

, The

Aus

tral

ian

Nat

iona

l Uni

vers

ity

page

142

of 4

81 (c

hapt

er 2

: “H

ardw

are/

Softw

are

Inte

rfac

e” u

p to

pag

e 15

0)

Sim

ple

arit

hmet

ic in

mem

ory

Cal

cula

te a

gain

:

e := a + b - 2*c

Or

wit

h o

verfl

ow

ch

ecks

:

ldr

r1, [fp, #-12]

ldr

r2, [fp, #-16]

adds

r1, r1, r2

blvs

Overflow

; branch if overflow is set; keep next location in LR

ldr

r2, [fp, #-20]

adds

r2, r2, r2

blvs

Overflow

; branch if overflow is set; keep next location in LR

subs

r1, r1, r2

blvs

Overflow

; branch if overflow is set; keep next location in LR

str

r1, [fp, #-24]

… Overflow:

; … for example writing a log entry with location

bx

lr

; resume operations - assuming the above did not change LR

149

Har

dw

are/

Soft

war

e In

terf

ace

© 2

019

Uw

e R

. Zim

mer

, The

Aus

tral

ian

Nat

iona

l Uni

vers

ity

page

149

of 4

81 (c

hapt

er 2

: “H

ardw

are/

Softw

are

Inte

rfac

e” u

p to

pag

e 15

0)

Bas

ic in

stru

ctio

n se

ts

Cat

ego

rySi

de

effe

cts

ARM v7-M

Ari

thm

etic

, Lo

gic

Sets

an

d u

ses

CPU

fl ag

s

add, adc, qadd, sub, sbc, qsub, rsb,

mul, mla, mls, udiv, sdiv,

umull, umlal, smull, smlal,

and, bic, orr, orn, eor, cmp, cmn, tst, teq

Mo

ve a

nd

sh

ift

regi

ster

smov, lsr, asr, lsl, ror, rrx

Bra

nch

ing

Use

s C

PU fl

ags

b, bl, bx, blx, tbb, tbh

Load

& S

tore

Effe

cts

mem

ory

ldr, str, ldmdb, ldmia, stmia, stmdb

Inst

ruct

ion

set

s in

the

fi el

d:

RIS

C: P

ow

er, A

RM

, MIP

S, A

lph

a, S

PAR

K, A

VR

, PIC

, …

CIS

C: x

86, Z

80, 6

502,

680

00, …

Ove

r 50

bill

ion

CPU

s o

n

this

pla

net

are

ru

nn

ing

AR

M in

stru

ctio

n s

ets

146

Har

dw

are/

Soft

war

e In

terf

ace

© 2

019

Uw

e R

. Zim

mer

, The

Aus

tral

ian

Nat

iona

l Uni

vers

ity

page

146

of 4

81 (c

hapt

er 2

: “H

ardw

are/

Softw

are

Inte

rfac

e” u

p to

pag

e 15

0)

Tabl

e ba

sed

bran

chin

gtbb<c><q> [<Rn>, <Rm>]

; for tables of offset bytes (8 bit)

tbh<c><q> [<Rn>, <Rm>, lsl #1]

; for tables of offset halfwords (16 bit)

Co

mm

on

usa

ge fo

r b

yte

(8 b

it) t

able

s

tbb [PC, Ri]

; PC is base of branch table, Ri is index

Branch_Table:

.byte

(Case_A - Branch_Table)/2 ; Case_A 8 bit offset

.byte

(Case_B - Branch_Table)/2 ; Case_B 8 bit offset

.byte

(Case_C - Branch_Table)/2 ; Case_C 8 bit offset

.byte

0x00

; Padding to re-align with halfword boundaries

Case_A:

; any instruction sequence

b End_Case

; “break out”

Case_B:

; any instruction sequence

b End_Case

; “break out”

Case_C:

; any instruction sequence

End_Case:

143

Har

dw

are/

Soft

war

e In

terf

ace

© 2

019

Uw

e R

. Zim

mer

, The

Aus

tral

ian

Nat

iona

l Uni

vers

ity

page

143

of 4

81 (c

hapt

er 2

: “H

ardw

are/

Softw

are

Inte

rfac

e” u

p to

pag

e 15

0)

AR

M v

7-M

Ess

enti

al m

ulti

plic

atio

ns a

nd d

ivis

ions

32 b

it to

32

bit

mul{s}<c><q> {<Rd>,} <Rn>,<Rm>

; Rd := (Rn*Rm)

mla<c> <Rd>, <Rn>,<Rm>,<Ra>

; Rd := Ra + (Rn*Rm)

mls<c> <Rd>, <Rn>,<Rm>,<Ra>

; Rd := Ra - (Rn*Rm)

udiv<c> <Rd>, <Rn>,<Rm>

; Rd := unsigned (Rn/Rm); rounded towards 0

sdiv<c> <Rd>, <Rn>,<Rm>

; Rd := signed (Rn/Rm); rounded towards 0

32 b

it to

64

bit

umull<c> <RdLo>,<RdHi>,<Rn>,<Rm>

; RdHi:RdLo := unsigned ( (Rn*Rm))

umlal<c><q> <RdLo>,<RdHi>,<Rn>,<Rm>

; RdHi:RdLo := unsigned (RdHi:RdLo + (Rn*Rm))

smull<c> <RdLo>,<RdHi>,<Rn>,<Rm>

; RdHi:RdLo := signed ( (Rn*Rm))

smlal<c> <RdLo>,<RdHi>,<Rn>,<Rm>

; RdHi:RdLo := signed (RdHi:RdLo + (Rn*Rm))

… v

ersi

on

s fo

r n

arro

wer

nu

mb

ers,

as

wel

l as

vers

ion

s w

hic

h o

per

ate

on

mu

ltip

le n

arro

wer

nu

mb

ers

in p

aral

lel e

xist

as

wel

l.

150

Har

dw

are/

Soft

war

e In

terf

ace

© 2

019

Uw

e R

. Zim

mer

, The

Aus

tral

ian

Nat

iona

l Uni

vers

ity

page

150

of 4

81 (c

hapt

er 2

: “H

ardw

are/

Softw

are

Inte

rfac

e” u

p to

pag

e 15

0)

Bas

ic in

stru

ctio

n se

ts

Cat

ego

rySi

de

effe

cts

ARM v7-M

Ari

thm

etic

, Lo

gic

Sets

an

d u

ses

CPU

fl ag

s

add, adc, qadd, sub, sbc, qsub, rsb,

mul, mla, mls, udiv, sdiv,

umull, umlal, smull, smlal,

and, bic, orr, orn, eor, cmp, cmn, tst, teq

Mo

ve a

nd

sh

ift

regi

ster

smov, lsr, asr, lsl, ror, rrx

Bra

nch

ing

Use

s C

PU fl

ags

b, bl, bx, blx, tbb, tbh

Load

& S

tore

Effe

cts

mem

ory

ldr, str, ldmdb, ldmia, stmia, stmdb

Wh

at’s

mis

sin

g?

Ch

angi

ng

CPU

pri

vile

ges

and

han

dlin

g in

terr

up

ts.

Syn

chro

niz

ing

inst

ruct

ion

s

Co

min

g in

late

r ch

apte

rs

abo

ut c

on

curr

ency

an

d

op

erat

ing

syst

ems.

147

Har

dw

are/

Soft

war

e In

terf

ace

© 2

019

Uw

e R

. Zim

mer

, The

Aus

tral

ian

Nat

iona

l Uni

vers

ity

page

147

of 4

81 (c

hapt

er 2

: “H

ardw

are/

Softw

are

Inte

rfac

e” u

p to

pag

e 15

0)

Tabl

e ba

sed

bran

chin

gtbb<c><q> [<Rn>, <Rm>]

; for tables of offset bytes (8 bit)

tbh<c><q> [<Rn>, <Rm>, lsl #1]

; for tables of offset halfwords (16 bit)

Co

mm

on

usa

ge fo

r h

alfw

ord

(16

bit

) tab

les

tbh [PC, Ri, lsl #1]

; PC used as base of branch table, Ri is index

Branch_Table:

.hword (Case_A - Branch_Table)/2

; Case_A 16 bit offset

.hword (Case_B - Branch_Table)/2

; Case_B 16 bit offset

.hword (Case_C - Branch_Table)/2

; Case_C 16 bit offset

Case_A:

; any instruction sequence

b End_Case

; “break out”

Case_B:

; any instruction sequence

b End_Case

; “break out”

Case_C:

; any instruction sequence

End_Case:

144

Har

dw

are/

Soft

war

e In

terf

ace

© 2

019

Uw

e R

. Zim

mer

, The

Aus

tral

ian

Nat

iona

l Uni

vers

ity

page

144

of 4

81 (c

hapt

er 2

: “H

ardw

are/

Softw

are

Inte

rfac

e” u

p to

pag

e 15

0)

Stra

ight

pow

erC

alcu

late

:

c := a ^ b

mov

r1, #7

; a

mov

r2, #11

; b ; has to be non-negative

mov

r3, #1

; c

power:

cbz

r2, end_power

; exponent zero?

mul

r3, r1

sub

r2, #1

b

power

end_power:

nop

; c = a ^ b

Ho

w m

any

iter

atio

ns?

Ho

w m

any

cycl

es?

77

77

77

77

77

77

11$

$$

$$

$$

$$

$=

Page 7: COPE-02 Hardware/Software Interface...103 Hardware/Software Interface © 2019 Uwe R. Zimmer, The Australian National University page 103 of 481 (chapter 2: “Hardware/Software Interface”

151

Har

dw

are/

Soft

war

e In

terf

ace

© 2

019

Uw

e R

. Zim

mer

, The

Aus

tral

ian

Nat

iona

l Uni

vers

ity

page

151

of 4

81 (c

hapt

er 2

: “H

ardw

are/

Softw

are

Inte

rfac

e” u

p to

pag

e 15

1)

Har

dw

are/

Soft

war

e In

terf

ace

• In

stru

ctio

n fo

rmat

s

• R

egis

ter

sets

• In

stru

ctio

n e

nco

din

g

• A

rith

met

ic /

Log

ic in

stru

ctio

ns in

side

the

CPU

• Su

mm

atio

n, S

ub

trac

tio

n, M

ult

iplic

atio

n, D

ivis

ion

• Lo

gic

and

sh

ift o

per

atio

ns

• Lo

ad /

Sto

re a

nd a

ddre

ssin

g m

odes

• D

irec

t, re

lati

ve, i

nd

exed

, an

d a

uto

-in

dex

-in

crem

ent a

dd

ress

ing

form

s

• B

ranc

hing

• C

on

dit

ion

al b

ran

chin

g an

d u

nco

nd

itio

nal

jum

ps.

Sum

mar

y