Course Structure Computer Hardware Engineering - … · Computer Hardware Engineering ... Course Structure L Module 1: Logic Design ... Software Hardware/Software Interface

Computer Hardware Engineering

Lecture 5: ALU and Single-Cycle Processors

David Broman Associate Professor, KTH Royal Institute of Technology

Assistant Research Engineer, University of California, Berkeley

IS1200, spring 2015

Slides version 1.1 Revision v1.1, June 17, 2015: Minor fix in the figures on slides 21 and 22.

Part I Arithmetic Logic Unit

Part III Control Unit in a Single-Cycle Processor

David Broman [email protected]

2

Part II Data Path in a Single-Cycle Processor

Course Structure

L

Module 1: Logic Design

Module 3: Processor Design

Module 2: C and Assembly Programming

Module 5: Memory Hierarchy

Module 4: I/O Systems

Module 6: Parallel Processors and Programs

L

L1

L3

L4

L5

L8

L7

L10

DCÖ1 Lab:dicom

E1

Lab: nios2time

Home lab: C

Home Lab: cache

Lab: nios2io

Lab: nios2int

L6 L9

DCÖ2

L2

E2

E4

E3

E5

E6 E7

E8

E9

E10




3


Abstractions in Computer Systems

Instruction Set Architecture

Microarchitecture

Logic and Building Blocks

Digital Circuits

Analog Circuits

Devices and Physics

Operating System

Application Software

Computer System Networked Systems and Systems of Systems

Software

Hardware/Software Interface

Digital Hardware Design

Analog Design and Physics




4


Agenda

Part II

Data Path in a Single-Cycle Processor

Part I

Arithmetic Logic Unit

Part III

Control Unit in a Single-Cycle Processor




5


Part I

Arithmetic Logic Unit

Acknowledgement: The structure and several of the good examples are derived from the book “Digital Design and Computer Architecture” (2013) by D. M. Harris and S. L. Harris.




6


Arithmetic Logic Unit (ALU)

An ALU saves hardware by combining different arithmetic and logic operations in one single unit/element.

ALU

A

Y

F

N

3 N

B N

ALU

Y

F 3

N N

N

B

A

ALU symbol: both figures have the same function

Input F specifies the function that the ALU should perform

ALUs can have different functions and be designed differently.

An ALU can also include output flags, for instance: •  Overflow flag (adder overflowed) •  Zero flag (output is zero)




7


Arithmetic Logic Unit (ALU)

+

0

1

0 1 2 3

F1:0

Y

F2

N

Zero Extend

N

N

N

A

B

Most significant bit (number 2) Bits 1 to 0

F2:0 Function

A AND B

not used

000 001 010 011 100 101 110 111

Exercise: Determine the functional behavior for each value of F.

[N-1]

Extract the most significant bit

Add zeros from bit N-1 to 1.

N

E H

A OR B A + B

A AND !B A OR !B

A – B SLT




8


Part II

Data Path in a Single-Cycle Processor





9


Data Path and Control Unit

A processor is typically divided into two parts

Data Path •  Operates on a word of data. •  Consists of elements such as

registers, memory, ALUs etc.

Control Unit •  Gets the current instruction from the data

path and tells the data path how to execute the instruction.




10


Instructions

In this lecture, we construct a microarchitecture for a subset of a MIPS processor with the following instructions

R-Type:

addi, lw, sw, beq

j

Arithmetic / logic instructions

add, sub, and, or, slt

I-Type:

J-Type:

Memory instructions

Arithmetic immediate instruction

Branch instructions




11


State Elements (1/2) Program Counter and Register File

The architectural states for this MIPS processor are the program counter (PC) and the 32 registers ($0, $t0, … $s0, $s1, … etc.)

Program Counter (PC) 32-bit register

PC at the current clock cycle

PC at the next clock cycle

32 registers of size 32-bit

5-bit address results in 25 = 32 registers

Reads 32-bit data

Two read ports (RD1 and RD2) and one write port (WD3).

CLK

PC

32 32 PCnext

CLK

A1 RD1

A2 5

A3 5

WD3 32

32 RD2

32

WE3

5




12


State Elements (2/2) Instructions and Data Memories

Nonarchitectural states are used to simply logic or increase performance (introduced in next lecture).

A simplified instruction memory, modeled as a read-only memory (ROM)

32-bit address Reads 32-bit word of data

Reads or writes 32-bit word of data

32-bit address

Writes on the rising clock edge and when write enable (WE) is true

32 A RD

Inst

ruct

ion

Mem

ory

32 A RD

32

Dat

a M

emor

y

CLK

WE

WD 32

32




13


Read Instruction from the Current PC

First step. Read the instruction at the current PC address.

A 32-bit instruction Instr is fetched.

CLK

PC

32 32 A RD

32

Inst

ruct

ion

Mem

ory

Inst PCnext




14


lw instruction – Read Base Address

op rs

6 bits 5 bits

31 26 25

rt

21 20

5 bits

imm

16 15

16 bits

0 Example lw $s0,4($s1)

Base address in rs Read out the base address from the register file. 25:21 cuts out the 5 bits from the instruction. RD1 has now the address stored

in $s1 (in the above example). CLK

PC

32 32 A RD

32

Inst

ruct

ion

Mem

ory

CLK

A1 RD1

A2 5

A3 5

WD3 32

32 RD2

32

WE3 25:21 Inst

PCnext




15


lw instruction – Read Offset

op rs

6 bits 5 bits

31 26 25

rt

21 20

5 bits

imm

16 15

16 bits

0 Example lw $s0,4($s1)

The offset is stored in the imm field.

The offset is signed. Sign extend to 32 bits.

CLK

PC

32 32 A RD

32

Inst

ruct

ion

Mem

ory

CLK

A1 RD1

A2 5

A3 5

WD3 32

32 RD2

32

WE3 25:21

Sign Extend 15:0

Inst PCnext

32

The offset is found in the least significant 16 bits of the instruction.

That is: Simm15:0 = Inst15:0 Simm31:16 = Inst15

Simm




16


lw instruction – Read Data Word

Example lw $s0,4($s1)

The base address and the offset are added together

CLK

PC

32 32 A RD

32

Inst

ruct

ion

Mem

ory

CLK

A1 RD1

A2 5

A3 5

WD3 32

32 RD2

32

WE3 25:21

Sign Extend 15:0

Inst PCnext

32

Simm

ALU

32 A RD

Dat

a M

emor

y

CLK

WE

WD 32

0102

Control code for +

Reads out the data word from data memory.

32

0




17


lw instruction – Write Back

Example lw $s0,4($s1)

CLK

PC

32 32 A RD

32

Inst

ruct

ion

Mem

ory

CLK

A1 RD1

A2 5

A3 20:16

WD3 32

32 RD2

32

WE3 25:21

Sign Extend 15:0

Inst PCnext

32

Simm

ALU

32 A RD

Dat

a M

emor

y

CLK

WE

WD 32

0102

32

op rs

31 26 25

rt

21 20

imm

16 15 0

Reads out 5 bits of the rt register to enable write back of result.

1

Write enable

Write back the result

0




18


lw instruction – Increment PC

CLK

PC

32 32 A RD

32

Inst

ruct

ion

Mem

ory

CLK

A1 RD1

A2 5

A3 20:16

WD3 32

32 RD2

32

WE3 25:21

Sign Extend 15:0

Inst PCnext

32

Simm

ALU

32 A RD

Dat

a M

emor

y

CLK

WE

WD 32

0102

32

1

+

4

Increment the PC by 4. (Next instruction is at address PC + 4)

This is the complete data path for the load word (lw) instruction.

0




19


sw instruction – Increment PC

CLK

PC

32 32 A RD

32

Inst

ruct

ion

Mem

ory

CLK

A1 RD1

A2

A3 20:16

WD3 32

32 RD2

WE3 25:21

Sign Extend 15:0

Inst PCnext

32

Simm

ALU

32 A RD

Dat

a M

emor

y

CLK

WE

WD 32

0102

32

0

+

4

We need to read the base address, read the offset, and compute an address. Good news: Example

sw $s0,4($s1)

20:16

The word to be stored is saved in a register (rt-field in the I-type) The data word is

stored into the memory

Write enable must be false

1

We have already done that!.




20


R-type instructions – Machine Encoding

We are now going to handle all R-type instructions the same uniform way. That is, we should handle add, sub, and, or, and slt.

op rs

6 bits 5 bits

31 26 25

rt

21 20

5 bits

imm

16 15

16 bits

0

I-Type

op rs

6 bits 5 bits

31 26 25

rt

21 20

5 bits

rd

5 bits

16 15

shamt

5 bits

11 10

funct

6 bits

6 5 0

R-Type

The rs and rt fields are in the same place for both I-Type and R-Type




21


R-type instructions – ALU Usage

CLK

PC

32 32 A RD

32

Inst

ruct

ion

Mem

ory

CLK

A1 RD1

A2

A3 15:11

WD3 32

32 RD2

WE3 25:21

Sign Extend 15:0

Inst PCnext

32

Simm

ALU

32 A RD

Dat

a M

emor

y

CLK

WE

WD 32

ALUControl

32

+

4

20:16

3

ALUSrc = 0 1

0

1

We want to send the second operand to the ALU, but still be compatible with the lw-instruction.

Different ALU control signals for different instructions.

MemWrite = 0




22


R-type instructions – Write to Register

CLK

PC

32 32 A RD

32

Inst

ruct

ion

Mem

ory

CLK

A1 RD1

A2

A3 15:11

WD3 32

32 RD2

WE3 25:21

Sign Extend 15:0

Inst PCnext

32

Simm

ALU

32 A RD

Dat

a M

emor

y

CLK

WE

WD 32

ALUControl

32

+

4

20:16

3

ALUSrc = 0 1

0

1

Bypass the data memory if an R-Type instruction

0

1

MemWrite = 0

MemToReg = 0

R-Type instructions write to registers and not to memory.




23


R-type instructions – Machine Encoding

op rs

6 bits 5 bits

31 26 25

rt

21 20

5 bits

imm

16 15

16 bits

0

I-Type

op rs

6 bits 5 bits

31 26 25

rt

21 20

5 bits

rd

5 bits

16 15

shamt

5 bits

11 10

funct

6 bits

6 5 0

R-Type

For the lw instruction, the target register is stored in the rt field (bits 20:16)

For R-type instructions, the target register is stored in the rd field (bits 15:11)




24


R-type instructions – Use the rd field

CLK

PC

32 32 A RD

32

Inst

ruct

ion

Mem

ory

CLK

A1 RD1

A2

A3

WD3 32

32 RD2

WE3 25:21

Sign Extend 15:0

Inst PCnext

32

ALU

32 A RD

Dat

a M

emor

y

CLK

WE

WD 32

ALUControl

32

+

4

20:16

3

ALUSrc = 0

RegWrite = 1

0

1

0

1

MemWrite = 0

MemToReg = 0

0

1

20:16

15:11

RegDst = 1

Create a control variable for register write. Write to register using rd field

instead of rt.




25


beq instruction – Machine Encoding

Recall that the beq instruction is a branch instruction, encoded in the I-Type.

op rs

6 bits 5 bits

31 26 25

rt

21 20

5 bits

imm

16 15

16 bits

0

I-Type

The rs and rt fields specify the registers that should be compared.

Example beq $s0,$s1,loop

Recall how to compute the BTA: BTA = PC + 4 + imm * 4

The imm field is used when computing the branch target address (BTA)




26


beq instruction

CLK

PC

32 A RD

32

Inst

ruct

ion

Mem

ory

CLK

A1 RD1

A2

A3

WD3 32

32 RD2

WE3 25:21

Sign Extend 15:0

Inst

PCnext

32

ALU

32 A RD

Dat

a M

emor

y

CLK

WE

WD 32

ALUControl

32

+

4

20:16

3

ALUSrc = 0

RegWrite = 1

0

1

0

1

MemWrite = 0

MemToReg = 0

0

1

20:16

15:11

RegDst = 1

<<2

+

0

1 Zero

Branch = 1

Compare if equal

Compute BTA

Branch taken if equal, else increment PC by 4




27


Pseudo-Direct Addressing (Revisited) The J and JAL instructions are encoded using the J-type. But, the address is not 32 bits, only 26 bits.

op

6 bits

31 26 25

addr

26 bits

0

A 32-bit Pseudo-Direct Address is computed as follows: •  Bits 1 to 0 (least significant) are always zero because word

alignment of code. •  Bits 27 to 2 is taken directly from the addr field of the machine

code instruction. •  Bits 31 to 28 are obtained from the four most significant bits from

PC + 4.




28


j instruction

CLK

PC

32 A RD

32

Inst

ruct

ion

Mem

ory

CLK

A1 RD1

A2

A3

WD3 32

32 RD2

WE3 25:21

Sign Extend 15:0

Inst

32

ALU

32 A RD

Dat

a M

emor

y

CLK

WE

WD 32

ALUControl

32

+

4

20:16

3

ALUSrc

RegWrite

0

1

0

1

MemWrite

MemToReg

0

1

20:16

15:11

RegDst

<<2

+

0

1 Zero

Branch

0

1

Jump

<<2 25:0 27:0

31:28

32




29


Data Path for Instructions add,sub,and,or,slt,addi,lw,sw,beq,j

CLK

PC

32 A RD

32 In

stru

ctio

n M

emor

y

CLK

A1 RD1

A2

A3

WD3 32

32 RD2

WE3 25:21

Sign Extend 15:0

Inst

32

ALU

32 A RD

Dat

a M

emor

y

CLK

WE

WD 32

ALUControl

32

+

4

20:16

3

ALUSrc

RegWrite

0

1

0

1

MemWrite

MemToReg

0

1

20:16

15:11

RegDst

<<2

+

0

1 Zero

Branch

H

0

1

Jump

<<2 25:0 27:0

31:28

32




30


Part III

Control Unit in a Single-Cycle Processor





31


What to Control?

CLK

PC

32 A RD

32

Inst

ruct

ion

Mem

ory

CLK

A1 RD1

A2

A3

WD3 32

32 RD2

WE3 25:21

Sign Extend 15:0

Inst

32

ALU

32 A RD

Dat

a M

emor

y

CLK

WE

WD 32

ALUControl

32

+

4

20:16

3

ALUSrc

RegWrite

0

1

0

1

MemWrite

MemToReg

0

1

20:16

15:11

RegDst

<<2

+

0

1 Zero

Branch

0

1

Jump

<<2 25:0 27:0

31:28

32

We should set the control signals depending on the instruction.




32


Control Unit Input: Machine Code

op rs

6 bits 5 bits

rt

5 bits

imm

16 bits

I-Type

op rs

6 bits 5 bits

rt

5 bits

rd

5 bits

shamt

5 bits

funct

6 bits

R-Type

op

6 bits

addr

26 bits

J-Type

For I-Type and J-Type, the control signals depend on the op field

For the R-Type, the op field is 0. The control signals depend on the funct field




33


Control Unit Structure

Main Decoder

ALU Decoder

op 6

2 ALUOp

funct 6

RegWrite RegDst ALUSrc Branch MemWrite MemToReg Jump

ALUControl 3

The 6 bits op field from all instruction types

Internal signal ALUOp ALUOp = 00 means add ALUOp = 01 means subtract ALUOp = 10 look at the funct field ALUOp = 11 n/a

The 6 bits funct field from the R-type. Ignored if other types.

Control signals to the data path

H




34


ALU Decoder

00 ? 010 (add) ALUOp funct ALUControl

?1 ? 110 (subtract)

1? 100000 (add) 010 (add)

1? 100010 (sub) 110 (subtract)

1? 100100 (and) 000 (and)

1? 100101 (or) 001 (or)

1? 101010 (slt) 111 (set less than)

ALU Decoder

2 ALUOp

funct 6

ALUControl 3

Enough to check one bit (faster decoding)




35


Main Decoder E H

Inst op RegWrite RegDst ALUSrc Branch MemWrite MemToReg Jump ALUOp R-Type lw sw beq addi j

000000

100011

101011

000100

001000

000010

1 1 0 0 1 0

1 0 ? ? 0 ?

0 1 1 0 1 ?

0 0 0 1 0 ?

0 0 1 0 0 0

0 1 ? ? 0 ?

0 0 0 0 0 1

10

00

00

01

00

??




36


Performance Analysis (1/2) General View

How should we analyze the performance of a computer?

•  By clock frequency? •  By instructions per program?

Problem: •  Your program may have many inputs. •  Not only one specific program might be

interesting.

Solution: Use a benchmark (a set of programs). Example: SPEC CPU Benchmark

Execution time (in seconds) # instructions

clock cycles ×

instruction ×

seconds clock cycle

=

Number of instructions in a program (# = number of)

Average cycles per instruction (CPI)

Seconds per cycle = clock period TC.

Determined by the critical path in the logic.

Determined by programmer or the compiler or both.

Determined by the micro-architecture implementation.




37


Performance Analysis (2/2) Single-Cycle Processor

Execution time (in seconds) # instructions

clock cycles ×

instruction ×

seconds clock cycle

=

Number of instructions in a program (# = number of)

Average cycles per instruction (CPI)

Seconds per cycle = clock period TC.

Determined by the critical path in the logic.

Determined by programmer or the compiler or both.

Determined by the micro-architecture implementation.

Each instruction takes one clock cycle. That is, CPI = 1.

The main problem with this design is the long critical path.

The lw instruction has longer path than R-Type instructions. However, because of synchronous logic, the clock period is determined by the slowest instruction.




38


Critical Path Example: Load Word (lw) Instruction

CLK

PC

32 A RD

32

Inst

ruct

ion

Mem

ory

CLK

A1 RD1

A2

A3

WD3 32

32 RD2

WE3 25:21

Sign Extend 15:0

Inst

32

ALU

32 A RD

Dat

a M

emor

y

CLK

WE

WD 32

ALUControl

32

+

4

20:16

3

ALUSrc

RegWrite

0

1

0

1

MemWrite

MemToReg

0

1

20:16

15:11

RegDst

<<2

+

0

1 Zero

Branch

0

1

Jump

<<2 25:0 27:0

31:28

32




39


Reading Guidelines

Main content in Chapter 4 in the course book. See also the optional book by Harris & Harris (see course web page)

Module 3 (Processor Design) P&H Chap. 4 (except 4.9, 4.10, 4.12) P&H Appx. B (review) - Exercise 5

You need to review logic design. See Appendix B and slides on the course website.




40


Summary

•  The ALU performs most of the arithmetic and logic computations in the processor.

Thanks for listening!

Some key take away points:

•  The data path consists of sequential logic that performs processing of words in the processor.

•  The control unit decodes instructions and tells the data path what to do.

•  The single-cycle processor has a long critical path. We will solve this in the next lecture by introducing a pipelined processor.

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Course Structure Computer Hardware Engineering - … · Computer Hardware Engineering ... Course Structure L Module 1: Logic Design ... Software Hardware/Software Interface