Continuum Simulation for Continuum Simulation for Power Integrity AnalysisPower Integrity Analysis

Raj NairRaj Nair Dec. 16, 2010 Dec. 16, 2010

December 2010December 2010 AnaSIMAnaSIM 22

Presentation OverviewPresentation Overview

BackgroundBackground Methodology fundamentalsMethodology fundamentals ExamplesExamples Benefits: chip floorplan optimizationBenefits: chip floorplan optimization

Tool demoTool demo

ConclusionConclusion

December 2010December 2010 AnaSIMAnaSIM 33

0.1

1

10

100

’71 ’74 ’78 ’85 ’92 ’00 ’04 ’08

Pow

er (

Wat

ts)

40048008

80808085

8086

286

386

486

Pentium®processors

Processor power doubles every ~36 months…

0.1

1

10

100

’71 ’74 ’78 ’85 ’92 ’00 ’04 ’08

Pow

er (

Wat

ts)

40048008

80808085

8086

286

386

486

Pentium®processors

0.1

1

10

100

’71 ’74 ’78 ’85 ’92 ’00 ’04 ’08

Pow

er (

Wat

ts)

40048008

80808085

8086

286

386

486

Pentium®processors

Processor power doubles every ~36 months…

CPU Operating State Currents Time(s)

(Amp)

0.0

+20.00

+40.00

+60.00

+30.00u +30.00u +30.01u +30.01u +30.02u +30.02u +30.03u +30.03u

Sleep

Active

CPU Operating State Currents Time(s)

(Amp)

0.0

+20.00

+40.00

+60.00

+30.00u +30.00u +30.01u +30.01u +30.02u +30.02u +30.03u +30.03u

Sleep

Active

CPU On-Chip Voltage DroopsTime(s)Volts

(V)

+500.00m

+1.00

+30.00u +30.05u +30.10u +30.15u

Voltage Droops BlueScreens!

CPU On-Chip Voltage DroopsTime(s)Volts

(V)

+500.00m

+1.00

+30.00u +30.05u +30.10u +30.15u

Voltage Droops BlueScreens!BlueScreens!

Power Integrity Challenges: Power Integrity Challenges: CPUCPU

Power doublesevery ~36 months

Transistors doubleevery ~18 months

Operating modescreate load shifts

Which createsupply voltage‘droops’, on-die

Managed in part by package devices

Mother Board

Capacitors

MicroprocessorHeat Spreader

PackageSubstrate

Pentium™ is a trademark of Intel® Corporation

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Decoupling Cap Loop-L Decoupling Cap Loop-L ScalingScaling

st

d

pif Iret

C

LIVV

)sin( 1

d

p

C

LIV

1

1

1

12

11

1

1111 C

L

V

fVCk

C

LIVkV iv

2

2

2

12

22

2

2222 C

L

V

fVCk

C

LIVkV iv and gives

2

1

fcl SSS

Quintuplet and Triplet loop-L scaling

0.01

0.1

1

10

P858 P860 P1262 P1264

Process

loo

p-L

, p

H

Q-scaling T-scaling

Load shift induced voltage noise equation and derivation of decapcomponent characteristics scaling

Inversely related to process scaling(on-die cap) & (freq. scaling)2

65nm

<<0.1pH! References:Nair2001 Intel Assembly Technology Journal – Invited Paper on ‘Pathfinding’2002 Intel Technology Journal paper “Emerging Directions for Packaging…”

With Die Caps

Without Die Caps

With Die Caps

Without Die Caps

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On-die L & L*di/dt challengeOn-die L & L*di/dt challengeConsider a Roots of Two Scaling [1] scenario:

Capacitance-per-unit-area, Ca, scales by 2 , operating voltage scales by2

1, frequency

scales by 2 , and chip area scales by 2

1.

Following this constant-power scaling direction, and inspecting the change in Dynamic Voltage Droop in a unit area (/ua) of integrated silicon, we get:

Since C/ua scales by 2 and voltage scales by 2

1, I scales by 2 * 2 .

Assuming the effective L/ua doesn't change, C

L reduces by a factor of

2

1.

Multiplying I and C

L in the scaled process generation, the dynamic voltage droop amplitude:

IC

L scales by 2 * 2 *

2

1, or by a factor of 2 for constant power scaling.

References:Nair 2008, Nair & Bennett 2008, Nair & Bennett 2010EDADesignline “A Power Integrity Wall follows the Power Wall” & “Dynamic Voltage Droops & Total PI”, Prentice-Hall “PI Analysis & Mngmnt”

PI degradation scales exponentially as k -1.5, where k is the process scaling factor (0.7 for example), regardless of constant-power scaling.

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MotivationMotivation

Atomic or Abstract? Atomic or Abstract? Analyze ripples by Analyze ripples by

molecular molecular interactions? interactions?

Polygonal AnalysesPolygonal Analyses Nanoscale IC’s face Nanoscale IC’s face

exploding, exponential exploding, exponential computation computation complexitycomplexity

Energy & EfficiencyEnergy & Efficiency Must know IC’s ripples Must know IC’s ripples

for lowest Vfor lowest Vsupplysupply

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Meeting the ChallengeMeeting the Challenge Differential Power Differential Power

Voltage is a potential Voltage is a potential difference; treat difference; treat power grid power grid differentiallydifferentially

Partition hierarchically & Partition hierarchically & exploit symmetryexploit symmetry

ECDECD: Continuum models: Continuum models Grid is uniform; treat as a Grid is uniform; treat as a

voltage-continuum voltage-continuum along a along a single surfacesingle surface USPTO PUBUSPTO PUB

Include R, L, C and solve Include R, L, C and solve ‘true-electromagnetically’‘true-electromagnetically’

Abstract silicon, packageAbstract silicon, package Include Include distributed modelsdistributed models

for silicon loads, CAP, pkg for silicon loads, CAP, pkg and board componentsand board components

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Abstraction & Physics-based Abstraction & Physics-based SimsSims

High levels of Abstraction High levels of Abstraction Power GRID as SURFACEPower GRID as SURFACE DISTRIBUTED circuit load DISTRIBUTED circuit load

currents & capacitancecurrents & capacitance SYMMETRY in physical as SYMMETRY in physical as

well as electrical aspects well as electrical aspects

Comprehensive ModelingComprehensive Modeling All All gridgrid electromagnetic electromagnetic

properties, R, properties, R, LL, C used, C used Actual block load current Actual block load current

profiles used; profiles used; di/dtdi/dt, load , load activityactivity factors included factors included

Physics based SimulationPhysics based Simulation Field solver employed for Field solver employed for

Maxwell’s equationsMaxwell’s equations on on ‘surfaces’ / NO ‘models’ ‘surfaces’ / NO ‘models’

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SoC Power Integrity SoC Power Integrity SimulationSimulation

Do CAPACITORS really absorb noise energy?

9 x 7mm chip

5nF /sq. cm distributedCAP

100mA peak noise pulseof 100pswidth

Power grid simulation

Explicit CAP LENS

Pulse noise source

Differential noise

R+L+C Dynamic Noise Simulation in -fp

Source: D. Bennett, ANASIM Corp., -fp power integrity aware floor planner, www.anasim.com

Animation slideUse slide show

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Advanced SiP SimulationAdvanced SiP Simulation Near load systemsNear load systems

Active Noise Active Noise Regulator*Regulator*

Distributed Local (POL) Distributed Local (POL) Voltage RegulatorsVoltage Regulators

Spatial & TemporalSpatial & Temporal Power supply variation Power supply variation

in x, y and tin x, y and t Data can feed into Data can feed into

future future Dynamic Timing Dynamic Timing AnalysisAnalysis??

Simulation speed Simulation speed allows ‘allows ‘what-ifwhat-if’ ’ experiments for experiments for optimizationoptimization

Chip power grid noise

ANR attached to top left corner of gridReference:* Nair & Bennett, ComLSI Power Management Designline article http://www.powermanagementdesignline.com/howto/175800373

Animation slideUse slide show

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Example: System-level Chip Example: System-level Chip Sim Sim

GUI or Netlist capture GUI or Netlist capture Chip Chip NETLISTNETLIST Load current profiles are Load current profiles are

pulse100gap100 and pulse100gap100 and pulse200gap200pulse200gap200

SYMMETRY in physical as SYMMETRY in physical as well as electrical aspects well as electrical aspects

Experiment-1 resultsExperiment-1 results Chip grid Chip grid ANIMATIONANIMATION & &

MirrorMirror Notice substantial Notice substantial

voltage variation of top voltage variation of top left cornerleft corner

Cap 200pF added: Cap 200pF added: resultsresults

Chip grid Chip grid ANIMATIONANIMATION & & MirrorMirror

-fp simulation schematic illustration(hyperlinked image)

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Floorplanning / OptimizationFloorplanning / Optimization

GRID wire width, spacing, pitchGRID wire width, spacing, pitch Metal resource savings, routing / timing Metal resource savings, routing / timing

facilitationfacilitation DECAP optimizationDECAP optimization

Area savingsArea savings Block placement tweaks for PIBlock placement tweaks for PI

Noise generation, propagationNoise generation, propagation Chip-Package-Board early co-simulationChip-Package-Board early co-simulation Operating voltage (Energy) tuningOperating voltage (Energy) tuning Resonance detection and avoidance…Resonance detection and avoidance…

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SummarySummary

Continuum modeling facilitates Continuum modeling facilitates high high levels of abstraction and physics-levels of abstraction and physics-based analysesbased analyses for power integrity for power integrity

True-electromagnetic simulations True-electromagnetic simulations feasiblefeasible

Simulation speed permits “what-if” Simulation speed permits “what-if” expts. expts.

Chip resource optimization prior to Chip resource optimization prior to place and route / physical designplace and route / physical design

Facilitates low power/energy designFacilitates low power/energy design