Continuous-Time Analog Filter Design in CMOS Nanoscale Era · A. Baschirotto, “Continuous-Time Analog Filter Design in CMOS Nanoscale Era” 7 Outline Analog filter applications

Continuous-Time Analog Filter Design in CMOS Nanoscale Era

Andrea Baschirotto(1), Marcello De Matteis(1), Alessandro Pezzotta(1), Stefano D’Amico(2)

1 Dept. of Physics “G. Occhialini”

University of Milano-Bicocca Milan – Italy

2 Dept. of Innovation Engineering University of Salento

Lecce – Italy

A. Baschirotto, “Continuous-Time Analog Filter Design in CMOS Nanoscale Era” 2


Outline

Analog filter applications Analog Design vs. CMOS Nanometer Technologies

Analog filter recent developments

Conclusions


Nanometer Technology Outline

Digital circuits

o Smaller area

o Lower power consumption More circuit complexity and larger functionality


Nanometer Technology Outline

Analog circuits o Lower supply No cascode o Higher power for noise reduction Lower swing for the same SNR o Lower gain o Leakage current o Larger Threshold voltage variabity

STI, WPE

Node Nm 250 180 130 90 65 ⇓ LGATE Nm 180 130 92 63 43 tOX(inv.) Nm 6.2 4.45 3.12 2.2 1.8 ⇓ Peak gm µS/µm 335 500 720 1060 1400 ⇑ gds** µS/µm 22 40 65 100 230 ⇑⇑ gm/gds - 15.2 12.5 11.1 10.6 6.1 ⇓ VDD V 2.5 1.8 1.5 1.2 1 ⇓⇓ VTH V 0.44 0.43 0.34 0.36 0.24 ⇓ fT GHz 35 53 94 140 210* ⇑⇑



Outline

Analog Design vs. CMOS Nanometer Technologies Analog filter applications


Conclusions


Outline Analog filter applications

Analog filters are key blocks in analog signal processing o Telecom transceiver

o Detectors Read-out channel


Outline Analog filter applications

Analog filters are typically required to perform:

o Low-voltage operation (<1V) Bias Bias vs. Signal amplitude

o High-speed

Large bandwidth (≈2GHz) Small time-of-response

o Large linearity THD (<60dB @ 500mVpp) Linear range

o Low-noise PSD (<5nV/√Hz)

Lowpass filters are considered

o Bandpass could be considered too


gm-C Filters Pros & Cons

gm-C filters features

o Open-loop structure (MOS-based)

Transconductor problems • Parasitic cap sensitivity

• Lower linearity (No Rail-to-rail) o Linearity ≈ Vov

• Larger bandwidth

o gm ≈ 2·I/Vov

𝑔𝑚 =𝐼

𝑉𝑜𝑣

𝐵𝑎𝑛𝑑𝑤𝑖𝑑𝑡ℎ =𝑃𝑜𝑤𝑒𝑟

𝐿𝑖𝑛𝑒𝑎𝑟𝑖𝑡𝑦

Biquad cell problem

• One branch per-transconductor o Four transconductors per-biquad


Active-RC Filters Pros & Cons

Active-RC filters features

o Closed-loop structure

Smaller bandwidth • UGB spec UGBopamp > 50·fcut-off

Parasitic cap INsensitivity

Larger linearity (Rail-to-rail)

• Critical DC-bias @ LV



Outline

Analog Design vs. CMOS Nanometer Technologies Analog filter applications


Conclusions



Advanced Filter solutions

• Advanced technologies & Advanced Application

o No optimum filter

o Advanced custom filter design

Large signal processing Closed-loop Active-RC

o UGB spec reduction Active-gm-RC

o LV Current-based level-shift

o Noise reduction ( DR increase) IFLF

o Bandwidth increase Current-feedback

o Bandwidth increase Advanced source-follower

Small signal processing Open loop gm-C

o Power reduction Source-follower based

o Diode-C


Active-RC filters: UGB spec reduction From the Rauch Cell to the Active-Gm-RC Cell

• The Low-Pass Cell

• R2-C2 integrator in the frequency range of interest

• replaced by a bandwidth-controlled opamp

€

A(s) =ADC

1+ s ⋅ τ=ωu ⋅ τ1+ s ⋅ τ

• 1/τ is the 1st-pole angular frequency

• ADC is the DC-gain

• Unity gain angular frequency:

€

ωu =ADCτ

vivo

R1

R3

R2C1

C2

vivo

R1

R3

C1 ADC

1+s�t


Active-Gm-RC Filters The Low-Pass Cell

. Miller opamp

€

ADC = gm1 ⋅Ro1 ⋅gm2 ⋅Ro2

• The adjusting circuit sets

€

gm1= 1/ kg ⋅R1( )

dependence on the opamp frequency response parameters (gm1, & CC)

dependence on parasitic component values (R1, R2 , & C1)

vivo

R1

R3

C1 ADC

1+s�t

ro1 Co1

gm1

gm2ro2 Co2

vi

C1

R1

R3

vo

RC CC

Bias circuit to havegm1=kg/R1 gm2=1/RC


Active-Gm-RC Filters The Low-Pass Cell

• 4th-order UMTS&WLAN reconfigurable filter

UMTS WLAN 1st cell 2nd cell 1st cell 2nd cell fcut-off [MHz] 3.39 3.02 19.27 17.19 Q 0.806 0.522 0.806 0.522 k 1.26 1.26 1.26 1.26 UGBopamp [MHz] 6.17 3.56 35.08 20.27 UGBopamp/f cut-off 1.82 1.18 1.82 1.18

o Active-gm-RC

UGBopamp ≈ fcut-off

o Active-RC

UGBopamp ≈ 50· fcut-off

Vi+ R11 R21 R12 R22

C2 C1

Vi–

Vo+

Vo–

VCM


Active-Gm-RC Filters In-band & Out-of-band Linearity

• Large linear range

o In-band Signals

The closed loop operation guarantees large linearity

o Out-of-band Signals

The larger signal part is processed by passive linear elements (R1, R2 and C1)

The smaller part is processed by the non-linear opamp stages

R1

C1

vi

R2

voADC1+s·τ

Opamp freqresp


Active-Gm-RC Filters Experimental results (130nm)


Active-Gm-RC Filters Large-bandwidth implementation – UWB standard (90nm) *

• 5th-order structure

* Cito, PRIME 2008


LV Active-RC Filters Bias Point Design

o Closed-loop structure Bias point vs. Swing

Rail-to-rail swing Vo_DC = VDD/2

Cell DC-coupling Vi_DC = Vo_DC = VDD/2

DC-currents balance Vioa_DC = Vi_DC = Vo_DC = VDD/2

PMOS input pair bias Vioa_DC = VDD - (VGS_inputpair + VDSsat) = VDD/2

VDDmin = 2· Vioa_DC = 2· (VGS_inputpair + VDSsat)

VDDmin = 2·VTH + 4·Vov

VDSSAT

VGS

VDSSAT

VGS

VDD


Current-based Level-shift Active-RC Filter Bias Point Design

I1 reduces VDDmin

ILS =Vi _DC −Vioa_DC

R1+Vo _DC −Vioa_DC

R3

ILS =VDD / 2−Vov

R1+VDD / 2−Vov

R3

ILS = VDD / 2−Vov( ) ⋅ 1R1

+1R3

#

$%

&

'(

VDDmin = Vov +VGS_inputpair+ VDSsat

VDDmin = VTH + 3·Vov << 2·VTH+4·Vov Example:

o VTH = 0.35V

o Vov= 0.1 V

VDDmin = 0.65V << 1.1V

VDSSAT

VGS

VDD


Current-based Level-shift Active-RC Filter LV Rauch Cell

VDDmin = VTH+3·Vov

Inserting ILS

o reduces VDDmin

BUT o Increases noises o Reduces DR !! o Increases parasitic capacitance sensitivity

vo_DCR1

R3

R2

C1

C2

vi_DC

vioa_DCI1Cp


Current-based Level-shift Active-RC Filter LV Active-gm-RC (130nm) *

WLAN Receivers baseband filter design o Control loop to adjust ILS vs PVT variations

* De Matteis, ESSCIRC07


Low-Noise Active-RC Filter Inverse-Follow-the-Leader-Feedback (IFLF)

• Low-noise solution

€

No =Nopamp1+NR1 +NR2

€

Nopamp1=Nin ⋅ 1+R2R1

#

$ %

&

' (

• At low frequency only the noise vn1 reaches the output node o Vn2 & vn3 do not reach the output

Vo

Vi

-1

Vn3Vn2

Vn1


Low-Noise Active-RC Filter Advanced High-order IFLF

• IFLF architecture + Active-gm-RC

o Two internal biquad Active- gm-RC

o 3 Opamps for 5 poles


Low-Noise Active-RC Filter Advanced High-order IFLF (45nm)


Filter Bandwidth Extension Advanced Source-follower

• Source follower as:

o VGA cell

1st-order + Gain stage

o Biquad cell


Filter Bandwidth Extension Advanced Source-follower

• 7th-order filter

o 3 VGA cells (3 poles)

o 2 biquad cells (2 complex poles)

• Alternate P-type and N-type based cell for maintaining operating point


Filter Bandwidth Extension Advanced Source-follower - Global Performance (28nm)

CUT-OFF Freq=1.76GHz CUT-OFF Freq=870MHz

DC-GAIN 5dB

DC-GAIN 25dB

DC-GAIN 5dB

DC-GAIN 25dB

Supply Voltage 1.1V 1.1V 1.1V 1.1V

-3dB Bandwidth 1.87GHz 1.81GHz 889MHz 868MHz

IRN 5.01nV/√Hz 5.07nV/√Hz 5nV/√Hz 4.7nV/√Hz

PN,OUT (In-Band Integrated Noise at the

filter output, between 100kHz and 2GHz)

285µVrms 2.99mVrms 283µVrms 2.3mVrms

VOUT,SWING@THD≥30dBc 0.3V0-pk,diff (THD=33dBc)

0.28V0-pk,diff (THD=31dBc)

0.3V0-pk,diff (THD=34dBc)

0.2V0-pk,diff (THD=31.5dBc)

SNR 57.13dB 36.5dB 57.4dB 35.77dB Power 13mW 20mW 5mW 7mW

Output IP3 (1GHz&1.1GHz for 1.76GHz) 7dBm 2dBm - -


Active-RC Filters Optimum Design Automatic Design Approach ? *

Case-A: Dominant resistance noise o Opamp noise ⇓ Opamp input stage current ⇑ o R ⇑ Opamp output stage current (driving R) ⇓

* De Matteis, IEEE PRIME 2006

€

αN =IRNopamp

2

IRNcell2

Output stage Input stage current current



Case-B: Dominant opamp noise o Opamp noise ⇑ Opamp input stage current ⇓ o R ⇓ Opamp output stage current (driving R) ⇑


€

αN =IRNopamp

2

IRNcell2

Output stage Input stage current current



Linear design o Transfer function o Noise

Preliminary MATLAB routines

Non-Linear design o THD

Iterative SPICE simulations



Active-RC Filters Optimum Design Automatic Design Approach - Cascade design *

Power minimization (4th-order filter 2-biquad cascade) o Cell sequence & gain amount optimization

* De Matteis, ICECS 2009


Active-RC Filters Optimum Design Automatic Design Approach (65nm) *

* De Matteis, AVLSI 2010


Shunt-feedback Filter Filter & PGA

o Shunt feedback configuration Wide band Merge Filter & PGA functions 2nd-order transfer function


Shunt-feedback Filter Filter & PGA

o Large gain programmability Gain up to 15dB-20dB per stage


Shunt-feedback Filter Experimental results (90nm) *

* D’Amico, ESSCIRC2009, TCASI2012


gm-gm-C Filter 1st-order cell – Linearity

Standard design approach o Assume linear output load

Linearize input driver • Larger Vov

o No LV • Larger power

Alternative design approach o Assume non-linear input driver

Design non-linear output load to compensate input driver non-linearity • Smaller Vov

o Good for LV • Lower power

Non-linearity compensation is valid for small linear range


gm-gm-C Filter 2nd order cell

• Complex pole in the active (non-linear) load

o Single–Branch biquad !!!


gm-gm-C Filter 3rd order cell *

* Ruckaert, IEEE-JSSC2007

Additional input stage for gain control


gm-gm-C Filter Experimental results – (180nm - UWB) *

* D’Amico, ESSCIRC2007


gm-gm-C Filter Experimental results (180nm) *

Case I II III IV fo [MHz] 250 1000 DC-Gain [dB] 2 19 0 14 IR-Noise Level [nV/ √Hz] (simulated)

18 4.5 10 2.5

IR-In-band Noise [µVrms] (simulated)

285 71 320 80

THD@100mVpp [dB] (simulated)

-30 -30 -32 -37

SNR [dB] 45 53 44 53 Power consumption

[mW] 0.21 1.2 0.59 3.2

Technology CMOS 180nm Power supply 1.8V

* D’Amico, ESSCIRC2007


gm-gm-C Filter Complete system – UWB receiver *

* Ryckaert, ISSCC2006


Source-follower as an analog filter

Source-follower-based Filter 1st-order LP cell

€

H(s) =1

1+ s ⋅C / gm

Feedback structure

o The linearity improves with a larger closed-loop gain (gm·Rout) Linearity ≈ 1/ Vov

Vov ⇓ THD ⇑

𝐵𝑎𝑛𝑑𝑤𝑖𝑑𝑡ℎ = !"#$%

!"#$%&"'( 𝐵𝑎𝑛𝑑𝑤𝑖𝑑𝑡ℎ = 𝑃𝑜𝑤𝑒𝑟 · 𝐿𝑖𝑛𝑒𝑎𝑟𝑖𝑡𝑦

Vov ⇓ I ⇓ for a given gm (=I/ Vov)

Power reduction for the same linearity

• In Active-RC & Gm-C filters

o linearity requires larger Vov

Unitary gain

Vi

Vo


Vi

Vo

Source-follower-based Filter 1st-order LP cell

Large gm (with a low current) good noise performance (at low power) large cap for a given fo

• t.f. robustness w.r.t. parasitic cap

No parasitic poles,

No extra power to push non-dominant singularities at high frequency

No CMFB circuit Output CM voltage is fixed Vo_CM = Vi_CM + VGS

Low output impedance Power reduction

Large VDDmin

VDDmin = Vsat+Vswing+VGS+Vsat


Source-follower-based Filter 2nd-order LP filter

A single-branch biquad structure o Complex pole in the active (non-linear) degeneration load

VDDmin = 3·Vov + 2·VTH + Vswing

Vi+ Vi–

Vo+ Vo–

C1/2

C2/2

M1 M2

M3M4

I0 I0


Vo+ Vo–

C12/2

C22/2

M12 M22

M32M42

I0 I0Vi+ Vi–C11/2

C21/2

M11 M21

M31M41

I0 I0

Source-follower-based Filter Experimental results (180nm) *

• 4th-order Lowpass filter performance summary

* D’Amico, ISSCC06


Source-follower-based Filter 2nd-order LP filter

Single branch Folded structure .

VDDmin = Vsat + 2·VGS + Vswing VDDmin = 2·Vsat + VGS + Vswing g VDDmin = (3·Vov + VTH) + VTH + Vswing VDDmin = (3·Vov + VTH) + Vov + Vswing g


vi voR

C

Diode-C Filter Basic concept

In a passive RC filter

Concept_1: R can be highly non-linear • At LF (f<fpole)

o C is open o No current through R o Vo=Vi independently on R linearity

• At HF (f>fpole) o C is short o Vo=0 independently on R linearity

• Pole (f≈fpole) o ZR≈ZC o Large R-non-linearity effects

Use non-linear devices for linear t.f. P⇓


Diode-C Filter Basic concept

Concept_2: Cascade-RC’s do not synthesize complex poles New architecture solutions

o Two building blocks

NMOS Positive source-follower RC cell

NMOS Negative source-follower RC cell

€

Vmin = 3 ⋅Vov +Vth +Vswing

vi voR

C

vi voR*

Ci=-(vi+vo)/R*

in+

out+

in-

out-

in+

out+

in-

out-


Diode-C Filter 2nd-order filter

R*

C2vi R

C1vov1


Diode-C Filter High-order filter

Cascade of positive and negative cells o No DC current

R*

C2vi R

C1

R*

C4

R

C3

R

Cn-1

R*

Cnvo

vi voR

C

vi voR*

Ci=-(vi+vo)/R*


Diode-C Filter Experimental results (130nm – UWB) *

A 6th-order filter for UWB receiver o fo = 280MHz



Diode-C Filter Experimental results (130nm) *



Application: Radar (60GHz) receiver Architecture

Exploit the best solution for different blocks

Active-RC Source-follower-based Current-feedback

Good virtual ground Low-power Gain-programmability

6th-order LPF 20dB-gain fo>900MHz

Input passive mixer


Application: Radar (60GHz) receiver Experimental results (90nm) *

* D’Amico, RFIC2011

Documents

Continuous-Time Analog Filter Design in CMOS Nanoscale Era · A. Baschirotto, “Continuous-Time Analog Filter Design in CMOS Nanoscale Era” 7 Outline Analog filter applications