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(12) United States Patent Pan et al.
US006370671B1
US 6,370,671 B1 Apr. 9, 2002
(10) Patent N0.: (45) Date of Patent:
(54) CONFIGURABLE DECODER AND METHOD FOR DECODING A REED-SOLOMON CODEWORD
(75) Inventors: Wenwei Pan; Yue-Peng Zheng, both of Ocean Township, NJ (US)
(73) Assignee: Globespan, Inc., Red Bank, NJ (US)
( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.
(21) Appl. No.: 09/335,975
(22) Filed: Jun. 18, 1999
Related US. Application Data (60) Provisional application No. 60/090,027, ?led on Jun. 18,
1998.
(51) Int. Cl.7 ............................................. .. H03M 13/00
(52) US. Cl. ...................... .. 714/784; 774/785; 774/774
(58) Field of Search ............................... .. 714/784, 785, 714/774
(56) References Cited
U.S. PATENT DOCUMENTS
4,162,480 A 7/1979 Berlekamp ............. .. 240/146.1
4,809,275 A * 2/1989 Inoue et al. .. 4,833,678 A 5/1989 Cohen ....................... .. 371/37
(List continued on neXt page.)
OTHER PUBLICATIONS
FettWeis, G. and Hassner, M.; A combined Reed—Solomon encoder and syndrome generator With small hardWare com pleXity; Proceedings 1992 IEEE International Symposium on Circuits and Systems, vol. 4, 1992; pp. 1871—1874.* Dabiri, D. and Blake, I.F.; Fast parallel algorithms for decoding Reed—Solomon codes based on remainder poly nomials; IEEE Transactions on Information Theory, vol. 41 Issue: 4, Jul. 1995; pp. 873—885.*
Parallel Multiply Syndrome
Data In Accumulator array
E
State Control Signals
Sobski, A. and Albicki, A.; Parallel encoder, decoder detec tor, corrector for cyclic redundancy checking; Proceedings 1992 IEEE International Symposium on Circuit and Sys tems, ISCAS ’92, vol. 6, 1992 pp. 2945—2948.* Richard E. Blahut, “Theory and Practice of Error Control Codes,” Addison—Wesley Publishing Co., Inc., 1983 pp. 174—191.
Lin, et al., “Error Control Coding Fundamentals and Appli cations,” Prentice—Hall, Inc. 1983, pp. 170—176. Whitaker, et al.,. “Reed Solomon VLSI Codec for Advanced Television,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 1, No. 2, Jun. 1991, pp. 230—236. Kuang Yung—Liu, “Architecture for VLSI Design of Red Solomon Decoders,” IEEE Transactions on Computers, vol. C—33, No. 2, Feb. 1984, pp. 178—189. Shayan, et al., “A Versatile Time—Domain Reed—Solomon Decoder,” IEEE Journal on Selected Areas in Communica tions, vol. 8, No. 8, Oct. 1990, pp. 1535—1542.
* cited by examiner
Primary Examiner—Albert Decady Assistant Examiner—Joseph D. Torres (74) Attorney, Agent, or Firm—Thomas, Horstemeyer & Risley
(57) ABSTRACT
Kayden,
Disclosed is a con?gurable Reed-Solomon (RS) decoder that comprises a parallel multiply accumulator having a data input to receive at least one RS codeWord, the parallel multiply accumulator being con?gured to generate a syn drome array from the RS codeWord. The con?gurable RS decoder also includes a Galois ?eld computation unit coupled to the parallel multiply accumulator, and an RS decoder controller coupled to the parallel multiply accumu lator and the Galois ?eld computation unit, Wherein the RS decoder controller controls the operation of the parallel multiply accumulator and the Galois ?eld computation unit. The RS decoder may be con?gured for different numbers of symbols in the RS codeWords, parity symbols in the RS codeWords, and modulation types employed in creating the RS codeWords.
17 Claims, 19 Drawing Sheets
Galois Field Computation Unit
299
1 State Control Signals 7
Configuration Syndrome - . 4’
input 213
RS Decoder Controller
mus @ 236 239
US 6,370,671 B1 Page 2
US. PATENT DOCUMENTS 5,974,580 A * 10/1999 266k et a1. ............... .. 714/755
5446 743 A 8/1995 ZOOk ........................ .. 371/371 6,052,815 A * 4/2000 Z001‘ ------------------------ -- 714/758
5,467,297 A * 11/1995 Zook _______ __ 708/492 6,055,277 A * 4/2000 Stephens et a1. .......... .. 375/285
5555250 A * 9/1996 Walker et a1- 714/763 6,145,113 A * 11/2000 Back ........................ .. 714/784 5,610,929 A * 3/1997 Yamamoto 714/785 ,, 5,818,854 A * 10/1998 Meyer ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ " 714/785 6,163,871 A * 12/2000 YaI~1g ........................ .. 714/769
5,905,740 A * Williamson _____________ " 714/784 6,175,945 B1 1/2001 Oklta ....................... .. 714/784
U.S. Patent Apr. 9, 2002 Sheet 1 0f 19 US 6,370,671 B1
mm? /
25$
m: 1/
com
U H
U D
a: /
\oor mo? /
680mm A\\ B ,Y Lmuoocm mm 5:520 mm EEoQ E252 E262 mzmomm :EwCw; mow
U.S. Patent Apr. 9, 2002 Sheet 2 0f 19 US 6,370,671 B1
84 O O
126 f 9 I0 11 12 I3 14
O
8
O Oa7OOa3O
V
Syndrome
66 f1 1
K153 0 e12 810 a14
V
Massey/ Berlekamp
A\159
156 \v 812
169
183
K173
163 x I
V
@ien V
a6 a3 812
Correct Data
I0 11 12 13 I4 9 8 7
000000000000000
U.S. Patent
Data
Apr. 9, 2002 Sheet 4 0f 19
If 251 f _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 1
| |
| a l | ' |
| |
i 253 I | ‘ | | r I
: )V ‘\ I | 256 259 l l_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
612% ‘\L/ '
(13% \J/ ' —
>
O ' Q
Q '
US 6,370,671 B1
203 /
269
Syndrome Array t0
Galois Field Computation
Unit
U.S. Patent Apr. 9, 2002 Sheet 5 0f 19 US 6,370,671 B1
8m. A wolm 03m 255 V Q . “
N 6 _m w m m ? E 6.60:5 E9“. \
Q ll. i Q %
50 A! cozowtoo ES 5:5 E8
{no :0 $63 Allo<|_ mm Alwwj PM ‘IE4 * > %
v/kwm
m0
v0
A % mam vmmm V
U.S. Patent Apr. 9, 2002 Sheet 6 0f 19 US 6,370,671 B1
403 ( Decoder Enable
Idle
Decoder Enable = 1
@@ Berlekamg/Massey BM Master Start = 1 406
i 409 Ome a Done <> 1
Omega Omega Start = 1
Exception = 1
vK416 Exception ( Omega Done = 1 )
r 413
@@ Chien 4) 423\v Chien Start = 1 Success
Success = 1
Forney @@ Forney Start = 1
216/
Fig. 7
U.S. Patent Apr. 9, 2002 Sheet 8 0f 19 US 6,370,671 B1
546 i
1 549 é : BMM8 SL Done <> 1 - /
B8 =1
‘7/553 (SL Done =1 ) A # (SL Done <> 1) 592N110
SL Done <> 1 BM—M-9_ V B7 =1 \
569 SL Done = 1
BMM11 r L
583 586 \V
SL Done = 1 i
BMM12 r = 2t?
False
589
\ BMM13 BM done = 1
219/
U.S. Patent Apr. 9, 2002 Sheet 9 0f 19 US 6,370,671 B1
459 \ BMS Idle
B1, B3, B5, B7, B8 or B9 =1?
@@ /223 f 463
V
BMSlnit j=O, k=O
G) G)
479 f
Fig. 9A
U.S. Patent Apr. 9, 2002 Sheet 10 0f 19 US 6,370,671 B1
BMS1.1 466 Set C6 = "5" 4/ / 2238 store "0" at mem(k) k = k+1
BMS1 2 469
Set C6 = "6" 4) store "1" at |ambda(j) in MB 1
V
BMS1.3 473
store "1" at B(j) in MB 3 4/ set k = 0
set C6 = "O"
" 476
BMS1.4 / store S(x) at mem(k) in M80 k = k+1
Fig. 9B
U.S. Patent Apr. 9, 2002 Sheet 11 0f 19 US 6,370,671 B1
489
BMS3.1 4) Set C7 = "0"
Load R1 w/ "0" Load R2 W/ "O"
V
[223D 493
BMS3.2 Set C2 to "1" Set C3 to "0'' Set C4 t0 "0" Load R4 w/ R1*R2+O (LR4)
V
BMS3.3 Set 07 = "2"
Load R1 w/ Lambda(j) in MB 1
496
499
BMS3.4 Load R2 w/ S(r-j-1) in MB 0
BMS3.5 Set C4 to "1“ Load R4 W/ dr=R1*R2+R4
503
/
Fig. 9C
U.S. Patent Apr. 9, 2002 Sheet 12 0f 19 US 6,370,671 B1
BMS9 1 509
Set C6 = "2" 4/ Set 07 = "2" 2230 \
V
513 BMS9.2
Load R2 w/ B(t-1-j) in MB 3 </
V
BMS9.3 / Store R2 at B(t-j) in MB 3 i=1 + 1
( = t-1
' 519 BMS9.4
Set C6 = "5" ‘/ Store 0 at B(O) in MB 3
Fig. 9D
U.S. Patent Apr. 9,2002 Sheet 13 0f 19 US 6,370,671 B1
529 BMS5.1 /
Set = "0"’ = "1n, = "2",
C6 = and C7 = "2"
v 533
BMS5.2 / Load R1 W/ B(j) in MB 3
v 536
BMS5.3 4/ Load R2 w/ lambda(j) in MB 1
‘ 539
BMS5.4 /
V 543
BMS5.5 / Store R3 at T(j) in MB 2 . :1. + 1
Fig. 9E
U.S. Patent Apr. 9, 2002 Sheet 14 0f 19 US 6,370,671 B1
2236 \
556 BMS8.1 /
Set 61 = "0", c2 = C3 : "3", = "0",
C6 = "1", and C7 = "0"
Load R2 w/ "0" Load R5 w/ |NV(R4) (LR5)
‘ 559
BMS8.2 Set C7 = "2" / Load R1 w/ |ambda(j) in MB 1
‘ 563
BMS8.3 /
BMS8.4 566
store R3 at B(j) in MB 3 4/ j :j + 1
Fig. 9F
U.S. Patent Apr. 9, 2002 Sheet 15 0f 19 US 6,370,671 B1
2213f \ BMS'I 1 573
Set C6 = "2" 4/ Set C7 = "2"
l BMS7.2 /
load R2 W/ T(j) in MB 2
l BMS7.3 /
store R2 at Iambda(j) in MB 1 J =] + 1
576
579
U.S. Patent
ii?
Apr. 9, 2002 Sheet 16 0f 19 US 6,370,671 B1
9211192 Idle
Omea Start <> 1
.t__.__ ( Omega Start = 1 J
606
616 f
Omega lnit j = O, i = O / Fig. 10A
609 Omega Error
Degree Error = 1 Set C7 Load R1 w/ lambda (t-j) in MB 1
081 "2"
4/ f 226
R1 <> 0 and t-j <> 1.
and MT=O
619 \'
053 Set C6 = 5
Store "0" at omega(i) in M82
629 f
623 f
054 Set 07 = "1"
Load R1 w/ "1" (LR1)
625 f V
085 Set C7 = "2"
Load R2 w/ 8(0) in M80
627 f V
057 Set C6 = 3
Store R4 at omega(i) in MB 2 A
E Set C2 = 1
Set C3 = 0 Set C4 = 0
Load R4 W/ R1*R2 + O (LR4)
U.S. Patent Apr. 9, 2002
Fig. 105
@is
Sheet 17 0f 19
038 Set C7 = "1", C4 = "0"
Load R1 w/ "1"
US 6,370,671 B1
Set C7 = "2"
226
089
Load R2 w/ lambda (i) in MB 1 Load R4 w/ R1*R2+O
0810 Set C7 = "0" Load R2 W/ "0"
f. 633 0611
1= 0
‘ 639
0612 643
Set 07 = 2 4/ Load R1 w/ S(j) in M50
Load
646 \v @3 E
R2 w/ lambda(i-j) in MB 1
656 \v
0816 Set C6 = "3"
Store R4 at omega(i) in M52
MT = 0 and j<>(i-1), or
/ K 636 <\
649 f
0314 Load R2 w/ |ambda(i-j-1) in MB 1
V
0615 Set 04 = c2 = C3="O"
Load R4 w/ R4 + R1*R2
Omega Last Omega Done = 1
MT=0andj=(i-1), or MT=1andj=i
653
U.S. Patent Apr. 9, 2002
Chien Idle Chien Start = 1
Sheet 18 0f 19 US 6,370,671 B1
Chien lnit Setm,k,v,j=0 Set AC = 1, C7 = "0"
Load R1 and R2 w/ "0" 229 K 703 \
CH1
709 Set (:5 = c1 = c2 = and C3 = "O"
Load R3 W/ R2+R1 Load R5 w/ inv(AC)
*R2
.CH_2 Set C1 = C2 = C3 = "1"
Load R1 w/ lambda(t~j) in M51 Load R3 w/ R1+R3*AC j =1 + 1
Chien Error Chien error = 1 Set C6 =
Store R5 at X(v) in M80, 1st Half
CH3 "4"
723
CH6 Chien Done = 1
L’
726
57% Set C6 = "7"
Store N-1-m in M83 v=v+1
\
CH5 m = m + 1
inc AC (ACC)