Computer Science 37 Lecture 5

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    4.1

    Lecture5

    MemoryChips

    and

    FiniteStateMachines

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    4.2

    MoreandMoreBits

    Flip-flop:onesinglebit

    Register:asetofbits

    Registerfile:asetofregisters

    Whatsnext?

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    4.3

    Memory

    MemoryChip

    Width=wordsize=mbits

    Height=2^nwords

    Bitsize=HeightxWidth

    Addressn

    ]0..1[ mDin

    ]0..1[ mDout

    Chip

    select

    Write

    enable

    Output

    enable

    m

    m

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    4.4

    ErrorDetection

    ParityGenerator

    data

    paritybit

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    4.5

    ErrorDetection

    ParityGenerator

    data

    stored

    parity

    bit

    comparator

    computedparity

    bit

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    4.6

    TypesofMemory

    ROM:Read-OnlyMemoryPROM:ProgrammableROM

    EPROM:Erasable(byUV)PROMEEPROM:ElectricallyErasablePROM

    RAM:RandomAccessMemory

    SRAM:StaticRAM

    DRAM:DynamicRAM

    Writetoitanytime,readfromitanytime.

    Writetoitoff-line,readfromitanytime.

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    4.7

    SRAM

    Storeeachbitinsidealatchanditsvalueremainsaslongasthechipispoweredup.

    Accesstimeisfixed(maybedifferentforreadorwriteoperations).

    Setupandholdtimesmustbeobservedfor

    writes.

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    4.8

    DRAM

    Thebitsarestoredincapacitorsratherthaninlatches.

    Catch:capacitorsleakcharge=>mustrefreshperiodically.

    Refreshingtakesonly1%to2%ofactivecycles.

    CostislowerthanSRAM,butaccesstimeis

    higher.

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    4.9

    SSRAMandSDRAM

    Donthavetoaccessonewordatatime,butratherinchunksorbursts.

    Giveitaaddressandburstlengthforeach

    access.

    Dontneedtopassoneaddressatatime,but

    mustgiveitaclocksignaltosequentializeoperationswithinaburst.

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    4.10

    SequentialLogic

    CombinationalLogic:Nomemory.

    Whatextracapabilitieswoulda

    circuitwithmemoryhave?

    Memory

    CombinationalLogicClock

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    4.11

    Whatsinastate?

    Studytheproblemanddeterminewhat

    informationneedstoberememberedbythe

    circuitastimeevolves.

    Thestateindicatesthecurrentcontentsof

    memoryandwhatthevalueofanyoutput

    linesthecircuitmayhave.

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    4.12

    Example:SequenceGenerator

    (orCounter)

    A/000

    B/001

    C/010

    D/011

    E/100

    F/101

    G/110H/111

    Noneedforinputsotherthana

    referencesignalfortimekeeping.

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    4.13

    Example:SequenceGenerator

    (orCounter)

    000111

    111110110101

    101100

    100011

    011010

    010001

    001000

    Nextstate

    (XYZ)

    Currentstate(XYZ)

    YZXZXYXX ++='

    ZYZYY +='

    ZZ ='

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    4.14

    SequenceGeneratorCircuitCombinationallogic=generatesnextstate(statetransitionfunction)

    Memory=storescurrentstate

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    4.15

    Example:AnotherKindofCounter

    A/000

    B/001

    C/010

    D/011

    E/100

    F/101

    G/110H/111

    SinglebitinputWtellscircuittoeither

    stoporgooncounting.

    W=1

    W=1

    W=1

    W=1

    W=1

    W=1

    W=1W=1

    W=0

    W=0

    W=0

    W=0

    W=0

    W=0W=0

    W=0

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    4.16

    Example:AnotherKindofCounter

    1

    0

    1

    0

    1

    0

    1

    0

    W

    011011

    100011

    010010

    011010

    001001

    010001

    000000

    001000

    Nextstate

    (XYZ)

    Current

    state(XYZ)

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    4.17

    ASprinkleofFormalismMooreMachines

    Memory

    NextState

    Function

    Clock

    Current

    State Next

    StateControl

    Inputs

    OutputGeneration

    Circuit

    Output

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    4.18

    ASprinkleofFormalismMealyMachines

    Memory

    NextState

    Function

    Clock

    Current

    State Next

    StateControl

    Inputs

    OutputGeneration

    Circuit

    Output