8/4/2019 Computer Science 37 Lecture 19

http://slidepdf.com/reader/full/computer-science-37-lecture-19 1/11

Lecture19

AnOverviewofPipelining

8/4/2019 Computer Science 37 Lecture 19

http://slidepdf.com/reader/full/computer-science-37-lecture-19 2/11

8/4/2019 Computer Science 37 Lecture 19

http://slidepdf.com/reader/full/computer-science-37-lecture-19 3/11

Time76 PM 8 9 10 11 12 1 2 AM

 A

B

C

D

Time

76 PM 8 9 10 11 12 1 2 AM

 A

B

C

D

Task

order

Task

order

Note: itstilltakesme2hoursto

completeoneload.

Note: totaltimeisnow3h30mins.

Note: afterthe2nd hour,Ifinishone

loadevery30mins.

8/4/2019 Computer Science 37 Lecture 19

http://slidepdf.com/reader/full/computer-science-37-lecture-19 4/11

0

5000

10000

15000

20000

2500030000

35000

40000

45000

0 2000 4000 6000

numberofinstructions

     t    o     t    a     l     t     i    m    e

Non-pipelined

Pipelined

Theperformancegainwithpipelining

Thegainswithpipeliningcomefromthroughputnotfromreducing

theexecutiontimeofanindividualinstruction.

8/4/2019 Computer Science 37 Lecture 19

http://slidepdf.com/reader/full/computer-science-37-lecture-19 5/11

MIPSinstructionexecutionsequence

1.Fetchinstructionfrommemory.

2.Readregistersanddecodeinstruction.

3.Executeoperationorcalculateanaddress.

4.Accessanoperandindatamemory.

5.Writetheresultintoaregister.

Wecanbreakdowntheexecutionofeachinstructionintoasequenceoffivedifferentsteps:

8/4/2019 Computer Science 37 Lecture 19

http://slidepdf.com/reader/full/computer-science-37-lecture-19 6/11

812212lw

5212Branch

61212R-format

72212sw

Total

Time

Reg

Write

Data

Access

ALU

Op

Reg

Read

FetchClass

Timingforeachinstructionexecutionstep

Question: IfwewanttobuildapipelinedCPUforMIPS,

howwillwedealwiththefactthatthetotalexecutiontime

variesaccordingtothekindofinstruction?

8/4/2019 Computer Science 37 Lecture 19

http://slidepdf.com/reader/full/computer-science-37-lecture-19 7/11

8/4/2019 Computer Science 37 Lecture 19

http://slidepdf.com/reader/full/computer-science-37-lecture-19 8/11

Instruction

memory

 Address

4

32

0

Add Add

result

Shift

left 2

Instruction

M

ux

0

1

Add

PC

0Writedata

Mu

x

1

Registers

Readdata 1

Readdata 2

Readregister 1

Readregister 2

16Sign

extend

Writeregister

Writedata

Readdata

 Address

Data

memory1

 ALUresult

Mux

ALU

Zero

IF: Instruction fetch ID: Instruction decode/register file read

EX: Execute/address calculation

MEM: Memory access WB: Write back

AdaptingtheSingle-cycleDatapath

forPipelining

8/4/2019 Computer Science 37 Lecture 19

http://slidepdf.com/reader/full/computer-science-37-lecture-19 9/11

Pipelineregisters: Intermediatestorage

Question: Howdoesonedeterminethewidthoftheseregisters?

8/4/2019 Computer Science 37 Lecture 19

http://slidepdf.com/reader/full/computer-science-37-lecture-19 10/11

PipelineHazards

Whatifthenextinstructioncannotexecuteinthefollowingclockcycle?

Structuralhazard:

Badhardwaresupport.

Wecan’texecuteacombo

ofinstructionsinthesame

clockcycle.

Example: memory.

Solution:stall,design.

Controlhazard:

Theresultofoneinstructiondetermines

whathappenstootherinstructions..

Example: branch.

Solutions:stall,reorder,predict.

Datahazard:

Aninstructiondependsontheresultresultofapreviousinstruction

thatisstillinthepipeline..

Example: add$s0,$t0,$t1

sub$t2,$s0,$t3

Solution:stall,reorder,forwarding(orbypassing).

8/4/2019 Computer Science 37 Lecture 19

http://slidepdf.com/reader/full/computer-science-37-lecture-19 11/11

Time2 4 6 8 10

add $s0, $t0, $t1

IF ID WBEX MEM

add $s0, $t0, $t1

sub $t2, $s0, $t3

Programexecutionorder(in instructions)

IF ID WBEX

IF ID MEMEX

Time2 4 6 8 10

MEM

WBMEM

ChangingthePipelinetoEnableForwarding