Computer Architecture – Unit 2 : Control and Central ...chettinadtech.ac.in/storage/11-12-12/11-12-12-11-01-26-1239-sakthi...to make various functional units operate in parallel

Computer Architecture – Unit 2 :

Control and Central Processing Unit

Dept of EEE – VI Sem

UNIT II - CONTROL AND CENTRAL PROCESSING UNIT

Unit objective

� How a processor executes instructions,

� The micro programming approach,

� micro program organization,

� stack organization

� Instruction formats,

� Addressing modes,

� Data transfer and manipulation

Unit Introduction

In this unit we focus on the processing unit, which executes machines

instructions and coordinates the activities of the other nits. In this unit is often

called the Instruction Set Processor (ISP) or simply the processor. We examine

its internal structure and how it performs the tasks of Fetching, Decoding, and

executing instructions of a program. The processing used to be called Central

Processing Unit (CPU). The organization of the processor has evolved over the

year, driven by developments in technology and the need to provide high

performance.

A common strategy in the development of high-performance processor is

to make various functional units operate in parallel as much as possible. High

performance has a pipelined organization where the execution of one

instruction is started before the execution of the preceding instruction is

completed. In another approach is called superscalar operation, several

instruction are fetched and executed at the same time. A typical computing

task consist of a series of steps specified by a sequence of machine instructions

that consists a program. An instruction is executed by carrying out a sequence

of more rudimentary operations.




MICROPROGRAMMED CONTROL

Control signals are generated by a program similar to machine

language programs.

Control Word (CW); microroutine; microinstruction. Microprogramming is

a method of control unit design in which the control signal selection and

sequencing information is stored in ROM or RAM called control

memory(CM). The control signal to be activated at any time or specified

by a micro instruction, which is fetched from CM in much similar way an

instruction fetched from main memory.

A sequence of one or more micro operations designed to control specific

operation ,such as addition, multiplication is called a microprogram. The

address where the micro instruction are stored in CM is generated by

micro program sequencer or micro program controller.

The components of control unit work together as follows:

The control address register (MPC) holds the address of the next

microinstruction to be read. Every time a new micro instruction is loaded in

to the IR, the output of the block labeled starting address generator is

loaded in to the micro program controller. When address is available to

control register, the sequencer issues READ command to the control

memory. After issue of READ command the word from the addressed

memory location is read in to the micro instruction register. The micro

program controller is then automatically incremented by the clock, causing

successive microinstructions to be read from the control memory. The

content of the micro instruction register generates control signals which are

delivered to various parts of micro processor in the control sequence.




Conditional branch

The previous organization cannot handle the situation when the

control unit is required to check the status of the condition codes or

external inputs to choose between alternative courses of action. Use

conditional branch microinstruction.

Addres

s Microinstructio

n 0 P

C out , MA

R in , Read

, Select4,

Add,

Zin 1 Zout , P

C in , Yin , WM

F C

2 MDR

out , I in

3 Branch

to

starting

address

of

appropriate

microroutine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

25

If

N=0,

then

branch

to

microinstruction

0

26

Offset-field-of-IR

out , SelectY,

Add,

Zin 27

Zout , PC

in , End

Microroutine for the instruction Branch<0.




Advantage of microprogrammed control unit

• It simplifies the design of control unit ,thus it both,cheaper less error

prone to implement.

• Control functions are implemented in software rather than hardware.

• The design process orderly and systematic.

• More flexible ,can be changed to accommadate new system

specification or to correct the design errors quickly and cheaply.

• Complex functions such as floating point arithmetic can be realized

efficiently.

Disadvantage of microprogrammed control unit

Control store

Clock

generator

Starting and branch address Condition

codes

inputs External

CW

IR

µ P C




• A microprogrammed control unit is somewhat slower than the

hardwired contol unit ,because time is required to access the micro

instructions from control memory.

• The flexibility is achieved at some extra hardware cost due to the

control memory and its access circuitry.

Microinstructions

A straightforward way to structure microinstructions is to

assign one bit position to each control signal. However, this is very

inefficient. The length can be reduced: most signals are not needed

simultaneously, and many signals are mutually exclusive. All mutually

exclusive signals are placed in the same group in binary coding.

Grouping of control signals

Grouping technique is used to reduce the number bits in the

microinstruction.

• Gating signals:(IN and OUT signals)

• Control signals :Read ,Write,clear A etc

• ALU signals: Add, Sub etc

There are in all 39 control signals and hence each micro instruction will

have 39 bits.it is not at all neccassary to use all 39 bits for every micro

instruction because by using grouping of control signals we minimize

number of bits for microinstruction.

Way to reduce number of bits in micro instruction

Most signals are not needed simultaneously. Many signals are

mutually exclusive (eg) only one function of ALU can be activated at a

time.A source for data transfers must be unique which means that it

should not be possible to get the content of two different registers on

to the bus at the same time.Read and write signals to the memory




cant be activated simultaneously.39 control signals can be grouped in

to 8 different categories.

Techniques of grouping of control signals.

The grouping of control signals can be done either by using technique

called vertical organization or horizontal organization.

Highly encoded scheme that use compact codes to specify only a small

number of control functions in each micro instruction are reffered to asa

vertical organization.

The minimally encoded scheme, in which resources can be controlled with a

single instruction, is called a horizontal organization.

Comparison between horizontal and vertical organization.

Sr.no Horizantal Vertical

1

2

3

4

Long formats

Ability to express high degree of

parallesism.

Little encoding of control

information.

Useful when higher operating speed

is desired.

Short formats

Limited ability to express

parallel micro operations

Considerable encoding of

the control information.

Slower operating speeds.

Advantage and disadvantage of horizontal and vertical organizations.




• The horizontal organization approach is suitable when operating

speed of computer is a critical factor and where the machine

structure allows parallel usage of anumber of resource.

• Vertical apporoach result in slower operations speed but less bits are

required in the micro instruction.

• In vertical approach the significant factor is reduced.

Microprogram Sequencing

If all microprograms require only straightforward sequential execution of

microinstructions except for branches, letting a µPC governs the

sequencing would be efficient.

Two disadvantages:

� Having a separate microroutine for each machine instruction

results in a large total number of microinstructions and a large

control store.

� Longer execution time because it takes more time to carry out the

required branches.

� Example: Add src, Rdst

Four addressing modes: register, autoincrement, autodecrement, and

indexed (with indirect forms).







Microinstructions with Next-Address Field

The microprogram we discussed requires several branch

microinstructions, which perform no useful operation in the datapath. A

powerful alternative approach is to include an address field as a part of

every microinstruction to indicate the location of the next

microinstruction to be fetched. Pros: separate branch microinstructions

OP code 0 1 0 Rsrc Rdst Contents of IR

0 34 7 8 10 11

Address Microinstruction

(octal)

000 PC out , MAR in , Read, Select4 , Add, Zin

001 Z out , PC

in, Y

in , WMFC

002 MDR out , IR

in

003 µ Branch {

µ PC ← 101 (from Instruction decoder);

µ PC 5,4 ← [IR10,9]; µ PC 3 ← 121 Rsrc

ou

t , MAR

in, Read, Select4, Add, Z in

122 Z out

, Rsrcin

123 170 MDR

out, MAR

in , Read, WMFC

171 MDR out

, Yin

172 Rdst ou

t , SelectY, Add, Z in

173 Z out

, Rdstin , End

[IR 10 ] ⋅ [IR 9] ⋅ [IR8 ]}

µ Branch {µ PC ← 170;µ PC 0 ← [IR8 ]}, WMFC




are virtually eliminated; few limitations in assigning addresses to

microinstructions.

Cons: additional bits for the address field (around 1/6)

Micro instruction execution.

A microprogrammed computer has two distinct level of control.

(i) instruction level

(ii)micro instruction level

At the instruction level,the CPU continuously executes instruction cycles

that involve the following steps.

1. The CPU fetches an instruction from main memory ,whose address is

stored in the program counter PC.

2. The opcode part of I is placed in an instruction register IR,the

operation specified by IR is then decode and executed.

3. PC is altered to point to the next instruction to be fetched from

memory.

Micro instruction level

A similar sequence of operation takes place at the micro instruction level,

where the control unit continuously executes micro cyclea as follows.

1. The addressing portion(micro program sequencer)of the control unit

fetches a micro instruction MI from the control memory CM, whose address

is stored in the micro program counter.

2. MI is loaded in to micro instruction register MIR and is decoded to

produce the required control signals.




3. Micro program controller is altered to point to the next micro instruction

to be fetched from CM.

NANO PROGRAMMING

The Nano computer language primarily came from the nano

technology. Nano technology refers from the fields of applied science that

control matter on its molecular and atomic scale. The technology can be

used in materials science, applied physics, and of course, computer

programming.

The nano program is basically very easy to learn and to apply. Texts

can be typed immediately into the interface. It is also quite simple to insert

text into the program with the use of some editing configuration. There is

also the nano editor software that you can use with the main program base

so that saving, cutting, pasting, and searching becomes fairly

straightforward.

Currently, there are a lot of instructions software and basic instructional

kits for use of those who want to learn computer programming in nano.

Since nano is being one of the more popular languages today, this software

is being applied in almost all newer applications.

Comparison between Hardwired and Microprogrammed Control

Attribute Hardwired control Micro programmed control

Speed Fast Slow

Control functions Implemented in hardware

Implemented in software

Flexibility

Not flexible,to accomadate new system specifications or new instructions.

More flexible,to accomadate new system specifications or new instructions redesign is required.

Ability to handle large or complex instruction set.

Somewhat difficult Easier

Ability to support OS and diagnostic features.

Very difficult Easy




Design process Somewhat complicated Orderly and systematic.

Applications Mostly RISC microprocessors.

Mainframes ,some microprocessors.

Instruction size Usually under 100 instructions.

Usually over 100 instructions.

ROM size - 2 k to 10 k by 20-400 micro instructions.

Chip area efficiency Uses least area. Uses most area.

MEMORY LOCATIONS AND ADDRESS

Both instructions and data are stored in the memory of a computer. The main memory consists of millions of storage cells, each of which can store a binary digit or bit having the value o or 1. Group of n bits is referred to as a word of information and n is called the word length. Modem computers have word lengths that typically range from 16 to 64 bits. A unit of 8 bits is called a byte.

Fig. Main Memory Snapshot.

Accessing the main memory to store or retrieve a single word of information required distinct names or addresses for each word location. It is customary to use numbers from 0 through 2k - 1, for some suitable value of k, as the addresses of successive locations in the memory. The 2k addresses constitute the address space of the computer and the memory can have up to 2k addressable locations. Eg.24 bit address generates an address space of 224 locations




224 = 16 megabytes where 1 MB 220.

Characters Characters can be letters of the alphabet, decimal digits, punctuation marks and so on. They are represented by codes that are usually 6 to 8 bits long. General code used is ASCII — American Standard Code for Information Interchange.

Instructions A main memory word can also represent instruction. One part of the word specifies the operation to be performed and other parts may be used to specify operand addresses.

Bytes are grouped into words. Thus a 16 bit machine will have 16 bit registers and instructions for manipulating 16 bit words and so on.

Memory Operations

Both program instructions and data operands are stored in the memory. To execute an instruction, the processor control circuits must cause the word containing the instruction to be transferred from the memory to the processor. Operands and results must also be moved between the memory and the processor. Two basic operations involving the memory are needed, namely Load and Store. The Load operation transfers a copy of the contents of a specific memory location to the processor. The memory contents remain unchanged.

To start a load operation. 1. The processor sends the address of the desired location to the memory. 2. The control unit generates the read control signal to memory. 3. The memory reads the data stored at that address and sends them to the processor. Similarly, the store operation transfers an item of information from the processor to a specific memory location, destroying the former contents of that location.




ADDRESSING MODES The operation field of an instruction specifies the operation to be performed. This operation must be performed on some data stored in the computer register or memory words .The way the operands are chosen during the program execution depends on the addressing modes of the instruction. ‘The addressing mode specifies the rule for interpret or modifying the address field of the instruction before the operand is actually referenced. The purpose of addressing modes are • To give the programming versatility to the user by providing such facilities as pointers to memory, counters for loop control, indexing of data and program relocation. • To reduce the number of bits in the addressing field of an instruction. In order to understand the various addressing modes we need to understand the operation cycle of a computer. The control unit divides the instruction cycle in to three phases. • Fetch the instruction from memory • Decode the instruction • Execute the instruction The Program counter that keeps track of the instruction in the program stored in the memory .PC holds the address of the instruction to be executed and is incremented each time an instruction is fetched from the memory. ‘The decoding is done at step 2. Determine the operation to be performed, the addressing mode of the instruction and the location of the operands. The computer then executes an instruction and returns to step 1 to fetch the next instruction in the sequence. In some computers the addressing mode of the instruction is specified with a distinct binary code, just like operation code is specified. Some computers use a single binary code that designates both the operation and the mode of instruction.

The op code specifies the operation to be performed. The mode field is used to locate the .operands needed for the operation. There may or may not be an address field in the instruction. If there is an address field it may be designated as a memory address or a processor register. The general subject of specifying where the operands are is called addressing. a. immediate Addressing b. Direct Addressing c. Register Addressing d. Relative Addressing e. Indirect Addressing f. Register Indirect Mode g. Multilevel Indirect addressing h. Indexed Address Mode




i. Base Register Addressing Mode j. Auto Increment (or) Auto decrement Mode k. Implied Addressing l. Stack Addressing a) Immediate Addressing In this mode the operands are specified in the instructions itself. In other words the immediate mode instruction has operand field rather than address field. The operand field contains the actual operand to be used in conjunction with the operation specified in the instruction. Immediate mode instructions are useful for initializing the register to a constant value. Specify an operand in the instruction itself called immediate operand because it is fetched from memory at the same time, the instructor itself is fetched.

Advantages Does not require an extra memory reference to fetch the operand. Disadvantages Restricts the operand to a number that fit in an address field E.g. MVI A, 10 ADD 5 add 5 to contents of accumulator Application : Used for handling constants b) Direct Addressing To fetch an operand, address of the operand in the memory is given in the instruction. This form is called direct addressing. Application: Used for handling Static Data ADD B A =A +M[B]




Disadvantage: Limited addresses Space c) Register Addressing The operands are specified as a part of the processor registers The particular register is selected from the register field in the instruction. A k- bit field specifies (2 power k) registers. In this form, the address field contains the number of register in which the operand is stored. Register R EA = R

Advantages (i) Registers are faster than main memory (ii) Because there are few of them, only a few bits needed to address them. (iii) Memory traffic may be reduced. Application : When the operand is in register. Disadvantages (i) Decision must be made as to which operands and which intermediate results are to be kept in the limited number of registers and which are kept in main memory. Eg. MOV A,B MOV A,C ADD B,C d) Relative Addressing Mode




In this addressing mode the contents of Program Counter is added to the address part of the instruction in order to obtain the EA. When the address part of the instruction is added to the contents of the PC the result produces the EA whose position is relative to the next instruction. e) Indirect Addressing Direct addressing is a scheme in which the address specifies which memory word or register contains the operands. Indirect addressing is a scheme in which the address specifies which memory word or register contains not the operand but the address of the operand. In this mode the address field of an instruction gives the address where the EA is stored in the memory. Control fetches the instruction from the memory and uses its address part to access memory again to read the EA. A few addressing modes require that the address field of the instruction to be added to the contents of the specified register in the CPU. The EA address in these modes can be obtained by the following computation: Ex: ADD (B) EA = (B) Add contents of cell pointed to by contents of B to accumulator Application: To implement pointers in high level languages. I) register indirect Mode In this mode the instruction specifies the register in the CPU whose contents give the address of the operand in the memory. In other words the selected register contains the address of an operand rather than the operand itself. Before using the register indirect mode instruction the programmer must ensures that the memory address of the operand is placed in the processor register with the previous instruction. A reference to this register is then equivalent specifying a memory address. EA =(R) The advantage of the register indirect mode instruction is that instruction uses fewer bits to select a register than would have a memory address directly. Large address space Interruption the address field of the been required to specify Pointer is used to locate a memory word that itself points to another memory word and so on. g) Multilevel indirect addressing Pointer is used to locate a memory word that itself points to another memory word




and so on. h) Indexed Addressing Mode In this mode the contents of the index register is added to the address part of the instruction to get the EA of the operand. The index register is a special purpose CPU register that contains the index value. The address part of the instruction determines the starting address of the data array in the memory. Each operand in the array is stored in the memory relative to the starting address of the array. The distance between the starting address of the array and the location of the operand in the array is the index value present in the index register. Any operand in the array can be accessed with the same instruction provided that the index register contains the correct index value. The index register can be incremented to facilitate access to the consecutive operands. Some computers dictate one CPU register to function as index register. This register is involved implicitly when the index mode instruction is used. USE: • The indexed mode is used to access the array type data structure.

I) Base Register Addressing Mode: In this mode the contents of the base register is added to the address part of the instruction to obtain the EA. This is similar to indexed addressing mode except that the register now is called Base register instead of index register. The difference between the two modes is that the way they are used rather than in the way they are computed. An index register is assumed to hold an index number that is relative to the address part of the instruction. A base register is used to hold a base address and the address part of an instruction gives the displacement relative to this base address. USE: The base register addressing mode is used in the computer to facilitate the relocation of the program in memory. When program and data are moved from one segment of memory to another as required in the multiple program segments, the address value of the instruction must reflect this change of position, with a base register the displacement value, of the instruction do not have to be changed. Only the value of the base register required to updating to reflect the beginning of new memory segment. • Base register addressing mode is used to access the, record type data structure. j) Auto Increment (or) Auto Decrement Mode This is similar to register indirect mode except that the register is




incremented or decremented after (or before) its value is used to access memory. When the address stored in the register refers to .a table of data in the memory it is necessary to increment or decrement the register after every access to the table. This can be activated by increment or decrement instructions. EFFECTIVE ADDRESS (EA) is defined as the address obtained from the computation dictated by the given addressing mode. The EA is the address of the operand in a computational type instruction.

k) Implied Addressing Mode In this mode the operands are specified implicitly, in the definition of the instruction. “Complement Accumulator” .Here the operand in the accumulator register is implied in the definition of the instruction. All register reference instructions that use accumulator are implied mode instructions. ZERO ADDRESS instructions in the stack organized computer are implied mode instructions, because the operands are implied to be top of the stack.

l) Stack Addressing A stack consists of data items (words, char, bits etc.) stored in consecutive order in the memory. The first item pushed onto the stack is said to be at the bottom of the stack. The item most recently pushed onto the stack is said to be the top of the stack. Associated with each stack is a register or memory word that contains the address of the top of the stack called stack pointer.

Computers that are stack oriented have an instruction to push the contents of a memory location or a register on to the stack. Such an instruction must both copy the item and decrement the stack pointer. Similarly an instruction to pop the top of the stack into a register or memory location must make a new copy in the proper place and increment the stack pointer.




STACKS AND QUEUES A computer program often needs to perform a particular subtask using the familiar subroutine structure. In order to organize the control and information linkage between the main program and the subroutine, a data structure called a stack is used. A stack is a list of data elements, usually words or bytes, with the accessing restriction that elements can be added or removed at one end of the list only. This end is called the top of the stack, and the other end is called the bottom. The structure is sometimes referred to as a pushdown stack. Stack is last-in-first-out (LIFO) mechanism; the last data item placed on the stack is the first one removed when retrieval begins. The terms push and pop are used to describe placing a new item on the stack and removing the top item from the stack, respectively. Data stored in the memory of a computer can be organized as a stack, with successive elements occupying successive memory locations. Assume that the first element is placed in location BOTTOM, and when new elements are pushed onto the stack, they are placed in successively lower address locations. A processor register is used to keep track of the address of the element of the stack that is at the top at any




given time. This register is called the stack pointer (SP). It could -be one of the general-purpose registers or a register dedicated to this function. If the memory is byte addressable memory with a 32-bit word length, the push operation can be implemented as Subtract #4,SP

Move NEWITEM,(SP) Where the Subtract instruction subtracts the source operand 4 from the destination operand contained in SP and places the result in SP. These two instructions move the word from location NEWITEM on the Top of the stack, decrementing the stack pointer by 4 before the move the pop operation can be implemented as Move (SP), ITEM

Add #4,SP




Fig Stack Operation QUEUE Another useful data structure that is similar to the stack is called a queue. Data are stored in and retrieved from a queue on a first-in—first-out (FIFO) basis. Thus, if we assume that the queue grows in the direction of increasing addresses in the memory, which is a common practice, new data are added at the back (high-address end) and retrieved from the front (low-address end) of the queue. There are two important differences between how a stack and a queue are implemented.




Fig. Queue Operations.

One end of the stack is fixed (the bottom), while the other end rises and falls as data are pushed and popped. A single pointer is needed to point to the top of the stack at any given time. On the other hand, both ends of a queue move to higher addresses as data are added at the back and removed from the front. So two pointers are needed to keep track of the two ends of the queue. Another difference between a stack and a queue is that, without further control, a queue would continuously move through the memory of a computer in the direction of higher addresses. One way to limit the queue to a fixed region in memory is to use a circular buffer. As in the case of a stack, care must be taken to detect when the region assigned to the data structure is either completely full or completely empty. Instruction Set: CISC and RISC

CISC: Complex Instructional Set Computers

RISC: Reduced Instructional Set Computers

� Simple instructions require a small number of basic steps to execute.

� Complex instructions involve a large number of steps.

� For a processor that has only simple instructions,a large number of

instructions may be needed to perform a given programming task.This

could lead to a large value for N and a small value for S.

� On the other hand, if individual instructions perform more complex

operations, fewer instructions will be needed, leading to a lower value of

N and a larger value of S. It is not obvious if one choice is better than

the other.

� Processors with simple instructions are called Reduced Instruction Set

Computers (RISC) and processors with more complex instructions are

referred to as Complex Instruction Set Computers (CISC)

� The decision for choosing the instruction set is done with the use of




pipelining. Because the effective value of S is close 1.

Compiler

A compiler translates a high-level language program into a sequence

of machine instructions. To reduce N, we need to have a suitable machine

instruction set and a compiler that makes good use of it.

An optimizing compiler takes advantage of various features of the

target processor to reduce the product N x S, which is the total number of

clock cycles needed to execute a program. The number of cycles is

dependent not only on the choice of instructions, but also on the order in

which they appear in the program. The compiler may rearrange program

instructions to achieve better performance without changing the logic of the

program.

Complier and processor must be closely linked in their architecture. They

should be designed at the same time.

Unit Summary

In this unit, we have presented an overview of the organization of the

computer’s CPU. Commercially available machines use many variations of

the organization presented here. The particular organization involves

tradeoffs between speed of execution and cost of implementation. Other

factors also come into play such as the technology used, the flexibility for

modification, and the need for special capabilities in the set of computer.

Micro programmed control provides considerable flexibility in implementing

instruction sets. We described two different approaches to the design of

machine instruction sets - the CISC and RISC approaches.




Key terms

Instruction Set Processor (ISP)

Program Counter (PC) Instruction Register (IR) Memory-Function-Completed (MFC) Generating Zin Control Word (CW) Nano programming

Objective type questions

1. When a program is in its execution process it resides in a. Computer b. CPU c. Main Memory d. Registers 2. The internal Clock of the CPU produces pulses at a fixed rate to _________ a computer operations. a. accomodate b. arrange c. Synchronize d. present 3. The speed of computer depend on a. user speed b. RAM c. Processor speed d. Internet connection speed 4. the measurement unit of computer clock speed is a. Milisecond b. second c. binary numbers d. megahertz 5. IR stands for a. International relation b. 2- Internet resources c. 3- Internal Resources d. 4- Instruction Register 6. IBR a. Instruction batch register




b. instruction buffer register c. instruction buffer remover d. none of them 7. The contents of the instructions register which specify itself are at a. the end of the instruction cycle b. the beginning of the instruction cycle c. the middle of the instruction cycle d. none of them 8..Memory capacity may be expressed in a. bits b. microseconds c. cycles d. megabytes 9. Data and instructions are put into primary storage by a. the ALU b. control unit c. secondary storage d. memory 10. Which of the following extracts instructions from memory and then decodes and executes them? a. Control unit b. RAM c. Data bus d. ROM

PART – A

1. What are the limitations of super scalar device?

2. Define pipeline speedup.

3. What is a processor clock?

4. Write down the control sequence for Move (R1), R2.

5. What is the function of a TLB (translation look-aside buffer)?

6. What is the WMFC step needed when reading from or writing to the main

memory?

7. Define register file.

8. Define the hardware organization of two-stage pipeline?

9. What is the role of cache memory in pipeline?

10. Name the methods for generating the control signals.




11. Define hardwired control.

12. Discuss the principle of operation of a micro programmed control.

13. Differentiate micro programmed control from hardwired control.

14. Define parallelism in microinstruction.

15. What are the types of microinstructions available?

16. Differentiate horizontal microinstruction and vertical microinstruction.

17. What is MFC?

18. What are the major characteristics of a pipeline?

19. What is a pipeline hazard?

20. What is data hazard?

21. What is instruction or control hazard?

22. Define structural hazards.

23. What is side effect?

24. What do you mean by branch penalty?

25. What is branch folding?

26. What do you mean by delayed branching?

27. What are the two types of branch prediction techniques available?

28. What is the ideal speedup expected in a pipelined architecture with n

stages. Justify your answer.

29. Draw the structure of two stage instruction pipeline.

PART – B

1. Give the organization of typical hardwired control unit and explain the

functions performed by the various blocks. (16)

2. Discuss the various hazards that might arise in a pipeline. What are the

remedies commonly adopted to overcome/minimize these hazards. (16)

3. Explain in detail about instruction execution characteristics. (16)

4. With a neat block diagram, explain in detail about micro programmed control

unit and explain its operations. (16)

5. a. Explain the execution of an instruction with diagram. (8)

b. Explain the multiple bus organization in detail. (8)

6. a. Explain the function of a six segment pipeline showing the time it takes to

process eight tasks. (10)




b. Highlight the solutions of instruction hazards. (6)

7. a. Explain the instruction cycle highlighting the sub-cycles and sequence of

steps to be followed. (8)

b. Explain the branch prediction techniques in detail. (8)

Documents

Computer Architecture – Unit 2 : Control and Central ...chettinadtech.ac.in/storage/11-12-12/11-12-12-11-01-26-1239-sakthi...to make various functional units operate in parallel