Computer Architecture

Lecture 6

by

Engineer A. Lecturer Aymen Hasan AlAwady

1/12/2013

University of Kufa - Informatics Center for Research and Rehabilitation

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Bus Timing. Cont.

Review Example:MVI A,32H (means load 32h in the register (A))2000H 3EH2001H 32H

1.Illustrate the bus timing ?2.Calculate the time required to execute the opcode and memory read if the clock frequency is 2MHz.

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0011 11100011 0010

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Bus Timing. Cont.

Clock frequency= 2 MHzT-state= clock period (1/f) = 0.5 µsExecution time of Opcode fetch: (4T)= 2 µsExecution time of Memory read: (3T)= 1.5 µsSo, Execution time of Instruction: (7T)= 3.5 µs

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1. Memory interfacing

• There needs to be a lot of interaction between the microprocessor and the memory for the exchange of information during program execution.• Memory has its requirements on control signals and

their timing.• The microprocessor has its requirements as well.

(Read and write from and on it)

• The interfacing operation is simply the process of designing a circuit to match these requirements.

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1.2 Memory structure & its requirements

• The way of interfacing the above two chips to the microprocessor is the same. • However, the ROM does not have a WR signal which is for

input buffer and RD for output buffer.

EPROM4096×8

AddressLines

DateLines

CS

RDOutput Buffer

ROM

R/W Memory2048×8

AddressLines

Data Lines

CS

RDOutput Buffer

RAMWRInput Buffer

Data Lines

A10

A0

A11

A0

Internal decoder

Internal decoder

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1.3 Interfacing Memory• Accessing memory can be summarized into the following

three steps:• Select the chip.• Identify the memory register.• Enable the appropriate buffer.

• Translating this to microprocessor domain:• The microprocessor places a 16-bit address on the

address bus. • Part of the address bus will select the chip and the

other part will go through the address decoder to select the register.

• The signals IO/M and RD combined indicate that a memory read operation is in progress (MEMR ) and it can be used to enable the RD line on the memory chip. 7

Timing of memory read cycle8

Timing of memory write cycle

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1.4 Address decoding

• The result of ‘address decoding’ is the identification of a register for a given address.

• A large part of the address bus is usually connected directly to the address inputs of the memory chip.

• This portion is decoded internally within the chip.• • What concerns us is the other part that must be

decoded externally to select the chip.• This can be done either using logic gates or a

decoder.10

Putting all of the concepts together: Back to the Overall Picture

•

A15-A8

LatchAD7-AD0

D7- D0

A7- A0

8085

ALE

IO/MRDWR

1K ByteMemory

Chip

WRRD

CS

A9- A0

A15- A10Chip Selection

Circuit

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A13

A12

A14A15

Address Decoding using NAND

A13

A12

A14

E1 E2 E3

O

3-to-8Decoder

A15

Address Decoding using 3-to-8 Decoder

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Address Decoding types

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1.5 Interrupt signals1.5 Interrupt signals• An interrupt is a hardware-initiated subroutine CALL.• When interrupt pin is activated, an ISR will be called, interrupting the program that is currently executing.

ISR: interrupt Service Register, a type of register in a Programmable Interrupt Controller

PinPin Subroutine LocationSubroutine Location

TRAP 0024

RST 5.5 002C

RST 6.5 0034

RST 7.5 003C

INTR *

Note: * the address of the ISR is determined by the external hardware.

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1.5.1 Interrupt signals1.5.1 Interrupt signals

• INTR input is enabled when EI (Embedded instruction) is executed.

• The status of the RST 7.5, RST 6.5 and RST 5.5 pins are determined by both EI instruction and the condition of the mask bits in the interrupt mask register.

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Interrupt VectorsInterrupt Vectors

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A circuit that causes an RST4 instruction (E7) to be executed in response to INTR.A circuit that causes an RST4 instruction (E7) to be executed in response to INTR.

• When INTR is asserted, 8085 response with INTA pulse.

• During INTA pulse, 8085 expect to see an instruction applied to its data bus.

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1.6 RESET signal1.6 RESET signal

• Following are the two kind of RESET signals:• RESET IN: an active low input signal, Program

Counter (PC) will be set to 0 and thus MPU will reset.

• RESET OUT: an output reset signal to indicate that the μp was reset (i.e. RESET IN=0). It also used to reset external devices.

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RESET signalRESET signal

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1.7 Direct Memory Access (DMA)1.7 Direct Memory Access (DMA)

• DMA is an IO technique where external IO device requests the use of the MPU buses.

• Allows external IO devices to gain high speed access to the memory.• Example of IO devices that use DMA: disk memory

system. • HOLD and HLDA are used for DMA. • If HOLD=1, 8085 will place it address, data and control

pins at their high-impedance.• A DMA acknowledgement is signaled by HLDA=1.

Reading assignment (Report)1. Topic (Challenges in memory interfacing)2. Write as minimum 3 pages in clear English and give your

conclusions and ideas about any potential solutions.3. Font 12 pt Times New Roman.4. DO NOT COPY AND PASTE (plagiarism).5. List your references.6. Write down your name and group clearly.7. Submit your paper on aymen@uokufa.edu.iq in MS Word

doc(x) format.8. Dead-line is the end Monday 9/12/2013.

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