© 2013 IEEE

Proceedings of the 14th IEEE Workshop on Control and Modeling for Power Electronics (COMPEL 2013), Salt Lake City, USA,June 23-26, 2013

Comparative Evaluation of SiC and Si PV Inverter Systems Based on Power Density and Efficiency asIndicators of Initial Cost and Operating Revenue

R. Burkart,J. W. Kolar

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Comparative Evaluation of SiC and Si PVInverter Systems Based on Power Density and

Efficiency as Indicators of Initial Cost andOperating Revenue

Ralph M. Burkart and Johann W. KolarPower Electronic Systems Laboratory

ETH Zurich, Physikstrasse 3Zurich, 8092, Switzerland

burkart@lem.ee.ethz.ch

Abstract—In this paper, two three-level three-phase all Si PVinverter topologies are compared to a standard two-level three-phase topology employing SiC-based power transistors. In acomparative evaluation based on multi-objective component mod-eling, the performance trade-offs between achievable efficiencyand power density are systematically analyzed for all systems.On the one hand, this is to investigate the potential of SiC todecrease the system complexity while achieving similar or betterperformance. The analysis shows that a similar power densityand efficiency can be obtained with the SiC two-level systemwhile requiring only one tenth of the chip area when comparedto the three-level Si inverters. On the other hand, in a next step,using power density and efficiency as indicators for initial invertercost and operational revenue, the trade-off analysis will allow todetermine the economically optimal system dimensioning.

Index Terms—Photovoltaic systems, SiC semiconductors, Costbenefit analysis, Reliability.

I. INTRODUCTION

The prolonged research activities undertaken at severalsemiconductor manufacturers has recently resulted in first

commercially available and mature SiC-based power transis-tors, such as MOSFETs, JFETs and BJTs [1], [2], [3]. In lit-erature, the advantages of SiC- over standard Si-based deviceshave been discussed for several years and have unanimouslyfound to be the superior blocking voltage capabilities andthe significantly decreased switching and conduction losses(exemplarily [4], [5]).

In recent years, the rapidly emerging field of photovoltaic(PV) power converters has been proposed as a major field ofapplication where the cost premium of SiC power transistorscan be justified by substantial performance gains. Analyzingthe respective literature for three-phase PV inverters, such as[7], [8], [9], [10], [11], it becomes apparent that divergentopinions exist on how to exploit best the performance advan-tages offered by SiC. In [7], it is recommended to use the low-loss potential of SiC exclusively to maximize the converterefficiency rather than the power density. It is argued that theaccumulated operational revenue due to more power fed intothe grid will be higher than the savings on smaller passivecomponents. In contrast, [8] suggests to focus on increasingthe power density. This can be achieved by employing higherswitching frequencies and switches with high rated blocking

(b)(a) (c)

3LI+3LBC (Si) 2LVSI+2LBC (SiC)

abc

a

b

c

P

N 0 0

DC,1CDC,1C DC,2C

DCL

DC,2C abc

P

N

DCL

DC,1C DC,2C

0

3LT+3LBC (Si)

4T

6D

1T

2T

21

DCL21

DCL21

DCL21

Fig. 1: Topologies considered for the comparative analysis between Si- and SiC-based semiconductors in PV inverters. (a) Three-level I-type topologywith input three-level DC/DC boost converter (3LI+3LBC) employing Si IGBTs and diodes. (b) Three-level T-type topology with input three-level DC/DCboost converter (3LT+3LBC) employing Si IGBTs and diodes. (c) Two-level voltage source inverter topology with input two-level DC/DC boost converter(2LVSI+2LBC) employing SiC JFETs and diodes (highlighted grey).

978-1-4673-4916-1/13/$31.00 ©2013 IEEE

a

b

c3

InverterP

N

EMI Filter

0

Transformer

L1

L2

L3

boostL DML

DMC

CMC

PVu

LVu = / 3√

dC

dR

400 V

Fig. 2: Generic topology of the considered three-phase PV inverter with boost inductors and output LC EMI filter. A ∆-Y transformer connects the 400 Vlow voltage secondary side (non-public industrial grid) to a European 50 Hz medium voltage grid. With minor adoptions in the filter due to different applicableEMI emission limits [6], the same topology could also be used in a (grounded) public low voltage grid.

voltages of 1700 V. The latter enables omitting the DC/DCboost converter stage which is normally required in 400 VAC grid applications. Finally, [9], [10], [11] pursue a mixedstrategy of increasing both efficiency and power density (bymeans of higher switching frequencies). Switching frequenciesof up to 144 kHz are reported.

The main shortcoming of the aforementioned contributionsis the lack of a systematic analysis of the optimal mixbetween efficiency improvement and power density increase.Moreover, except in [11], the impact of increased switchingfrequencies and faster switching speeds on important convertercomponents, such as the EMI filter, heat sink, PCB or housingis mostly neglected or only qualitatively discussed.

In this paper, the potential of SiC power transistors is in-vestigated by means of comparing two commonly used, high-efficient but rather complex three-level three-phase topologiesemploying standard Si devices (Fig. 1(a),(b)) to a simpler,more industry-friendly and potentially more reliable two-level topology which is equipped with superior SiC devices(Fig. 1(c)). All relevant converter components including theEMI filter are considered. On the one hand, the comparisonis performed in order to examine the potential of SiC todecrease the system complexity while achieving similar orbetter performance. On the other hand, the trade-offs betweenachievable efficiency and power density are systematicallyanalyzed. Since the power density can be seen as an indicatorfor the initial inverter cost and the efficiency as an indicatorfor the operational revenue of the inverter, in a next step, thisanalysis can be used to determine the economically optimalinverter dimensioning.

II. SYSTEM SPECIFICATIONS

The generic system topology for the comparative analysisof the selected topologies shown in Fig. 1 is depicted in Fig.2. The PV inverters with boost inductors and output LC EMIfilter are connected to a European 50 Hz medium voltage grid.

The RMS line-to-line voltage on the secondary side of the∆-Y transformer, which is a non-public industrial grid, isassumed to be 400 V with worst case deviations of ±10 %.The same topology could also be used in a public low voltagegrid. This would require minor adoptions in the EMI filterdue to different EMI emission limits [6]. With focus on afuture implementation, the rated system power is chosen to bePr = 10 kW. Based on the discussion in [12], the consideredMPP voltage range is assumed to be

uPV = [450 V, 820 V] , (1)

which enables, in conjunction with a DC/DC boost input stage,a temperature range of the solar generator of approximately−20 to 70 C and the use of 600 V and 1200 V rated semi-conductors.

A standard sinusoidal PWM modulation scheme with third-harmonic injection has been assumed throughout this work.The boost converters employ the same switching frequency asthe respective inverter stage. The three-level boost convertersoperate with an interleaved switching scheme and duty cycleslower than D < 0.5, yielding a doubling of the switchingfrequency seen by the two DC inductors 1/2LDC. Taking intoaccount that only half the DC voltages are applied, the requiredtotal inductance LDC is one quarter of the respective value forthe two-level boost inductor.

III. SEMICONDUCTORS

A. Semiconductor Selection

The semiconductors considered in this work are listed inTab. I. All devices are available in the TO-247 packagewhich facilitates comprehensive switching loss measurementsof the selected semiconductors. Paralleling of the devices isnot intended, however employment of different devices forthe inverter stages and boost converters are considered. Forsimplicity reasons, the discrete diodes of the 3LI+3LBC and

Tab. I: Considered semiconductors and corresponding topologies.

Device Material Description Topology

IKW30, 50, 75N60T Si 600 V T&FS IGBTs with anti-parallel diode 3LI+3LBC & 3LT+3LBCIKW25, 40N120H3 Si 1200 V Highspeed T&FS IGBTs with anti-parallel diode 3LT+3LBCIJW120R100T1 SiC 1200 V 100 mΩ normally-on JFET with integrated body diode 2LVSI+2LBCIDW20, 30S120 SiC 1200 V Schottky diode 2LVSI+2LBC

Fig. 4: Switching loss measurement test bench implementing a single phasebridge of the inverter stage of each topology.

3LT+3LBC topology are implemented using the anti-paralleldiodes of the respective 600 V IGBTs.

B. Switching Loss MeasurementsA reliable system dimensioning requires accurate perfor-

mance data of the employed components and materials. How-ever, the datasheet values for the switching losses are often in-complete. Moreover, the switching losses are to a wide degreeapplication and layout dependent. This holds especially truefor the 3LT inverter topology where 600 V devices commutatewith 1200 V rated devices [14]. Further motivated by the factthat the main intention of this work is the analysis of theimpact of using different power transistors (featuring widely

DSu

Di

Tp

100 V/div.

3 A/div.

2.5 kVA/div.

t 25 ns/div.

DSu

Di

Tp

100 V/div.

3 A/div.

2.5 kVA/div.

t 25 ns/div.

2,offT

2,onT

JFET 1200V vs. JFET 1200V (body diode) 2LVSI+2LBC

Fig. 5: Measured turn-off and turn-on switching loss energies Eoff, Eonrespectively, for the commutation between one of the selected SiC JFETsand the internal body diode of the opposed JFET in the inverter stage of the2LVSI+2LBC topology (ID = 13 A, UDS = 600 V, Tj = 25 C). It can beseen that the turn-off switching transition is close to zero voltage switching(ZVS).

varying switching performances), extensive measurements ofthe switching losses were conducted. For this purpose, thetest bench shown in Fig. 4 has been built which implementsa single phase bridge of each of the investigated topologies.For simplicity reasons, it is assumed that the switching lossenergies in the boost converter stages are similar to the losses

swU = 400V swU = 600V swU = 800V

0 5 10 15 20 250.00

0.05

0.10

0.15

0.20

0 5 10 15 20 250.0

0.2

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0 5 10 15 20 250.00

0.02

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0.06

0.08

0.10

JFET 1200V vs. JFET 1200V (body diode) 2LVSI+2LBC

mJ)

(

on

Eoff

E

off (

D)

Eon (

D)

E

mJ)

(

mJ)

(

mJ)

(

A)(DI

ossE (400V) C oss

E (600V) C ossE (800V) C

A)(DI

A)(DI

A)(DI

Fig. 3: Measured switching loss energies for the selected SiC JFETs employed in the 2LVSI+2LBC inverter stage. For commutating currents ID . 13 A theturn-off losses Eoff largely correspond to the energy stored in the output capacitor Coss of the device. For this operating range, the switching transitions areclose to zero-voltage switching (ZVS, see also Fig. 5) [13]. The internal body diode features a similar switching performance as SiC Schottky diodes knownfor their nearly vanishing reverse recovery current characteristics. It can be seen from the respective figures that most of the diode turn-off losses Eoff(D) aredue to the charging of Coss, whose energy is released again at turn-on.

Tab. II: Employed components and materials and respective dimensioning rules and constraints. Tj,max denotes the maximum admissible semiconductor junctiontemperature. The worst case ambient temperature is assumed to be Tamb,max = 40 C. ∆iLDC and ∆uCDC,1 are worst case high-frequency peak-to-peak currentand voltage deviations.

Implementation Dimensioning constraints

Cooling system Custom Al heat sink with forced air cooling,CSPI =9 W/K dm3 [12] Tj,max = 125 C @ Tamb,max = 40 C

LDC Metglas 2605S3A amorphous alloy & foil winding ∆iLDC = 30 %TL,max = 100 C @ Tamb,max = 40 C

CDC,1 EPCOS MKP DC B3277 film 1100 V ∆uCDC,1 = 2 %

CDC,2 2× EPCOS B43501 aluminium electrolytic 500 V Current handling capability, BDEW standard [15]

Lboost Metglas 2605S3A amorphous alloy & foil windingLDM Laminated Si steel & foil winding BDEW standard [15], CISPR 11 Class A EMI [6]CDM EPCOS X2 MKP B3292 E/F 305 V AC TL,max = 100 C @ Tamb,max = 40 CCCM EPCOS MKP B3279 400 V AC

in the inverter stages when employing the same switches.The switching loss energies were measured as a function of

the commutating drain current ID and drain source blockingvoltage UDS as well as the semiconductor junction temperatureTj. For the 600 V rated IGBTs employed in the 3LI+3LBCtopology, good agreement was found with the datasheet values.In contrast, the losses measured for the 3LT+3LBC inverterstage significantly vary from the datasheet values as expected,since 1200 V components commutate with 600 V components.The chip area dependency of the switching loss energies wasgenerally found to be small. Measurement results for theSiC JFETs operating in a half bridge arrangement of the2LVSI+2LBC inverter stage are shown in Fig. 3 and Fig. 5.In contrast to the investigated Si IGBTs, the switching lossenergies of the SiC JFETs are nearly independent from thetemperature but exhibit a strong non-linear dependence fromthe current.

IV. SYSTEM DIMENSIONING

In this section, the dimensioning procedure of the invertersystems is discussed. For the given semiconductors presentedin Sec. III and different switching frequencies, the achievableefficiency and the required inverter size needs to be estimated.The considered components beside the semiconductors arethe cooling system, the passive components in the DC linkas well as the AC filter components. The required analyticalloss, volume and thermal models are largely taken from [12],[16]. A summary of the employed materials and componentsas well as the respective dimensioning rules and constraintsare given in Tab. II. The dimensioning methodology assumescontinuous variables and thus allows for arbitrarily sizedcomponents or the employment of a non-integer amount. Thedimensioning criteria will be discussed in brief, while moredetailed information can be found in [12], [16]:

• Semiconductors and cooling system: based on a thermalmodel, the cooling system is dimensioned such that forthe worst case T ∗

j = Tj,max = 125 C, given Tamb =40 C, where T ∗

j denotes the highest occurring junctiontemperature [14], [17]. For the semiconductor losses, themethods of [16] were adopted as averaging methods (e.g.

[18]) would lead to significant errors due to the stronglynon-linear dependency of the switching loss energiesof the SiC JFETs (Fig. 3). As opposed to [12], thesemiconductor loss models were extended so as to includethe influence of the junction temperature.

• DC passives: the DC inductances are chosen such thatthe peak to peak ripple currents are limited to 30 % ofthe fundamental current. The volume is optimized underconsideration of the worst case temperature TL,max =100 C and the flux density saturation. The film capacitorsexhibit a worst case high-frequency peak to peak voltageripple of ∆uCDC,1 = 2 % whereas the ELCO capacitorsare designed so as to meet the required current handlingcapability. Furthermore, the DC-link capacitance needsto be chosen sufficiently high in order to fulfil the fault-ride-through requirements according to [15].

• Lboost and LC filter: the AC filter elements are chosenso as to comply with the CISPR 11 EMI Class A limits[6] and the medium voltage grid harmonics requirementsdefined in [15]. A single filter stage after the boost induc-tors proved sufficient to achieve the identified requiredattenuation values [19]. After computing the requiredinductance values, the respective coils are, in the samemanner as the DC coils, optimized with respect to thevolume.

• Constant losses: Constant losses independent from thetopology and switching frequency of Paux = 5 W for theauxiliary supply and DSP unit are accounted for.

V. PERFORMANCE COMPARISON

This section presents the results of the comparative evalua-tion of the topologies shown in Fig. 1. The trade-offs betweentotal volume and European efficiency [20] is graphicallydepicted in Fig. 8, whereas Fig. 6 and Fig. 7 give moredetailed information on the loss and volume breakdown forthe employed components.

For the considered switching frequency range fsw =[4, 24] kHz it can be seen that the 2LVSI+2LBC topologyachieves the highest efficiencies of all considered topologies.This is exclusively due to the low switching and conduction

96.5 97.0 97.5 98.0 98.5 99.00

1

2

3

4

5

ηEURO

dm

)3(

)(%

V tot

75 mm (2LVSI+2LBC)=SiCA 2

659 mm (3LI+3LBC)=SiA 2

710 mm (3LT+3LBC)=SiA 2

812

4

8

1612

4

816 12

2024

20

24 20

24

swf (kHz)x

16

2LVSI+2LBC

3LI+3LBC

3LT+3LBC

Fig. 8: Trade-off analysis between European efficiency ηEURO and totalinverter volume Vtot, parameterized by the switching frequency fsw. UCDC,1 =600 V, UCDC,2 = 650 V. Constant chip areas ASi and ASiC have beenassumed (independent from the switching frequency) for all topologies. Theindicated values each represent the sum of the chip areas of all semiconductorsemployed in the topologies: the combinations IKW50N60T (3LI+3LBC),IKW50N60T/IKW40N120H3 (3LT+3LBC) and IJW120R100T1/IDW20S120(2LVSI+2LBC) were found to be the optimal selections guaranteeing thelowest overall losses. The nearly equal efficiencies of the 2LVSI+2LBC for4 and 8 kHz are a result of the balanced sum of switching losses and lossesin the passives (see Fig. 6).

losses of the employed SiC devices. In contrast, the 3-levelSi topologies are suitable for higher power densities due tosmall EMI filters and DC passives. An interesting area forfurther investigations lies in between where all topologiesachieve a similar performance (Vtot ≈ 3 dm3, ηEURO ≈ 98.2 %).Here, it can be concluded that with SiC a similar performance

regarding efficiency as well as size of the passives can beachieved while offering a simpler and more standard topology.Moreover, the SiC 2LVSI+BC topology requires only onetenth of the chip area when compared to the Si systems.Eventually, for frequencies around 20 kHz, the total volumeof all topologies reaches a minimum and starts to graduallyincrease again with even higher frequencies. This is due toseveral reasons:

• The total capacitor size is nearly constant (Fig. 7) dueto the bulk volume associated with the DC-link capacitorCDC,2. Its volume does not change as the required cur-rent handling capability is constant over frequency. Thecapacitor volume thus represents a virtual lower limit ofthe achievable volume.

• The required AC filter inductance and capacitance valuesdo not proportionally scale with 1/fsw as a result of thefixed emission limits defined in the considered standards[6], [15].

• High-frequency losses in the inductors (proximity losses,losses due skin effect, high-frequency core losses) in-crease with rising frequency and eventually limit thevolume reduction due to lower required inductance valuesconsiderably.

• Increased switching frequencies yield higher switchinglosses and thus a larger heatsink. This ultimately out-weighs the volume savings on the remaining passivecomponents.

Due to the above discussed effects, the investigation of higher

75

150

225

300

0

2LVSI+BC3LI+3LBC 3LT+3LBC

x (kHz)swf

x

EURO,CP

EURO,constP

EURO,PP

EURO,LPEURO,CP

W)(PEURO,x

52

13

48

2215

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9

38

22

30

53

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37

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46 61

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5479

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155186

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3011

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95

101 101

1230

24

119144

1228

25

101

4 16128 2420 4 16128 2420 4 16128 2420

W)

(P E

UR

O,x

Fig. 6: Breakdown of the losses for the employed components and for different switching frequencies fsw. PEURO,C and PEURO,L are the total losses inthe capacitors and inductors, respectively. Pconst = Paux + Pfan, where Pfan are the (load independent and hence constant) fan losses of the cooling system.PEURO,C represent the total conduction losses and PEURO,P the total switching losses. All depicted losses are weighted according to the European efficiencyweighting formula.

1

2

3

4

0

2LVSI+BC3LI+3LBC 3LT+3LBC

x (kHz)swf

x

sinkVLVCV

Vx dm )3(

V x

0.34

0.48

2.06

0.39

0.46

1.51

0.44

0.36

1.28

0.31

1.18

0.49 0.54

0.28

1.14 1.12

0.26

0.60 0.41

0.46

1.51

0.47

0.36

1.28 1.18

0.31

0.540.35

0.48

2.06

0.60

0.28

1.14

0.26

1.12

0.670.39

0.36

2.57

0.42

0.33

2.24 2.05

0.30

0.460.36

0.49

4.21

0.50

0.30

1.90

0.29

1.87

0.54

4 16128 2420 4 16128 2420 4 16128 2420

5

dm

)3(

Fig. 7: Volume breakdown of of the employed components for different switching frequencies fsw. VC is the total capacitor volume, VL the total inductorvolume and Vsink the volume of the required heatsink.

switching frequencies seems only be meaningful if differentcore materials (e.g. ferrites), alternative winding geometries(e.g. solid round or Litz wire) as well as multi-stage filtertopologies are taken into account.

In a next step, the trade-off analysis shown in Fig. 8 willallow to determine the initial costs (depending on the volumeand component mix, by means of cost models as presented in[21]) and the operational revenues (depending on the efficiencyand feed-in tariffs). This will further facilitate the identificationof the optimal topology and switching frequency from aneconomical point of view.

VI. CONCLUSION

Numerous contributions have shown a potential for signifi-cant performance gains in the field of PV inverters by meansof employing advanced SiC-based power transistors. Whereasthe opinions on how to exploit best the superior performanceof SiC devices diverge, this paper proposes to increase theconverter reliability by simplifying the employed topology onthe one hand, and to systematically investigate the trade-offbetween efficiency and achievable power density on the otherhand.

The trade-off analysis based on switching loss measure-ments and multi-objective modeling has shown that the two-level all SiC system can achieve a similar performance re-garding efficiency and volume of the passives as the advancedthree-level all Si topologies. Moreover, the required SiC chiparea is approximately ten times smaller than the respectivetotal Si chip areas. This can serve as an indication for theeconomical benefit of using SiC in PV inverters despite highersemiconductor cost.

The obtained trade-off analysis can be used to determine themeaningful range of application of Si and SiC for PV inverterswith nominal power between 10 and 50 kW. In a next step, thedesigns with the highest economical benefit will be identified.This can be achieved by using cost models allowing to estimatethe initial inverter costs depending on the inverter bill ofmaterial, combined with estimations of the operational revenuedepending on the inverter efficiency. Ultimately, the selectedcandidate systems will be implemented to verify the theoreticalinvestigations. Additional work should focus in more detailon the inductor model and filter topology. Alternative corematerials, winding geometries and the use of multi-stage EMIfilters have to be checked for their ability to further decreasethe power density at higher switching frequencies.

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[2] W. Bergner, F. Bjoerk, D. Domes, and G. Deboy, “Infineon’s 1200VSiC JFET – The New Way of Efficient and Reliable High VoltagesSwitching,” Infineon Technologies, Tech. Rep., 2012.

[3] S. Araujo, L. Menezes, T. Hjort, and P. Zacharias, “The Renaissance ofthe BJT as a Highly Efficient Power Device Based on SiC Material,” inProc. PCIM Europe, may 2012.

[4] B. Ozpineci, L. Tolbert, S. Islam, and M. Hasanuzzaman, “Effects ofSilicon Carbide (SiC) Power Devices on HEV PWM Inverter Losses,”in Proc. IECON, vol. 2, pp. 1061–1066, 2001.

[5] J. Richmond et al., “An Overview of Cree Silicon Carbide PowerDevices,” in Power Electronics in Transportation, pp. 37–42, oct. 2004.

[6] Industrial, Scientific and Medical (ISM) Radio-Frequency Equipment –Electromagnetic Disturbance – Characteristics Limits and Methods ofMeasurement, CISPR 11, 2009.

[7] B. Burger, D. Kranzer, and O. Stalter, “Cost Reduction of PV-Inverterswith SiC-DMOSFETs,” in Proc. CIPS, pp. 1–6, jun. 2008.

[8] S. Araujo, C. Noding, B. Sahan, and P. Zacharias, “Exploiting theBenefits of SiC by Using 1700 V Switches in Single-Stage InverterTopologies Applied to Photovoltaic Systems,” in Proc. PCIM Europe,may 2011.

[9] D. Kranzer, C. Wilhelm, F. Reiners, and B. Burger, “Application ofNormally-off SiC-JFETs in Photovoltaic Inverters,” in Proc. EPE, pp.1–6, sept. 2009.

[10] C. Wilhelm, D. Kranzer, and B. Burger, “Development of a HighlyCompact and Efficient Solar Inverter with Silicon Carbide Transistors,”in Proc. CIPS, march 2010.

[11] R. Mallwitz, C. Althof, S. Buchhold, and E. Kiel, “First 99% PV Inverterwith SiC JFETs on the Market – Future Role of SiC,” in Proc. PCIMEurope, may 2012.

[12] R. M. Burkart, J. W. Kolar, and G. Griepentrog, “ComprehensiveComparative Evaluation of Single- and Multi-Stage Three-Phase PowerConverters for Photovoltaic Applications,” in Proc. INTELEC, pp. 1 –8,oct. 2012.

[13] R. A. Friedemann, F. Krismer, and J. Kolar, “Design of a MinimumWeight Dual Active Bridge Converter for an Airborne Wind TurbineSystem,” in Proc. APEC, pp. 509–516, 2012.

[14] M. Schweizer, I. Lizama, T. Friedli, and J. Kolar, “Comparison ofthe Chip Area Usage of 2-level and 3-level Voltage Source ConverterTopologies,” in Proc. IECON, pp. 391–396, nov. 2010.

[15] Technical Guideline Generating Plants Connected to the Medium-Voltage Network, BDEW Std., 2008.

[16] M. Schweizer, T. Friedli, and J. Kolar, “Comparison and Implementationof a 3-Level NPC Voltage Link Back-to-Back Converter with SiC andSi Diodes,” in Proc. APEC, pp. 1527–1533, 2010.

[17] J. W. Kolar et al., “Performance Trends and Limitations of PowerElectronic Systems,” in Proc. CIPS, pp. 1 –20, march 2010.

[18] J. Kolar, H. Ertl, and F. C. Zach, “Influence of the Modulation Methodon the Conduction and Switching Losses of a PWM Converter System,”IEEE Trans. Industry Applications, vol. 27, no. 6, pp. 1063–1075, 1991.

[19] K. Raggl, T. Nussbaumer, and J. Kolar, “Model Based Optimization ofEMC Input Filters,” in Proc. COMPEL, pp. 1–6, aug. 2008.

[20] B. Bletterie et al., “Redefinition of the European Efficiency – Finding theCompromise Between Simplicity and Accuracy,” in Proc. EU PVSEC,pp. 2735 – 2742, sep. 2008.

[21] R. M. Burkart and J. W. Kolar, “Component Cost Models for Multi-Objective Optimizations of Switched-Mode Power Converters,” in Proc.ECCE, accepted for publication. 2013.