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International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)
Volume 3 Issue 6, June 2014
2030
ISSN: 2278 – 1323 All Rights Reserved © 2014 IJARCET
Comparative Study on CMOS Full
Adder Circuits
Priyanka Rathore and Bhavna Jharia
Abstract― The Presented paper focuses on the comparison of seven full adders. The comparison is
based on the power consumption & area of full adders. It also highlights on comparison of different full adder circuits which are made of various logic styles. Used in designing paper suggests the best technique of designing on the basis of performance.
Index Terms― Full adder, Power consumption, Delay XOR &XNOR.
Introduction
Energy efficiency is one of the most required
features for recent electronics system designed
for high performance and small circuits .In
another way the ever increasing electronic circuit
demands low power small circuit equipments
which can be carried easily for example mobile
&laptops. Everywhere adder is the core element of complex arithmetic circuits like addition
multiplication division & exponentiation .There
are standard execution with different logic styles
that have been used earlier to design full adder
cells. By choosing appropriate (W\L) ratio we
can minimize the power dissipation without
decreasing the supply of voltage .To conclude
some of the performance criteria are considered
in the design and evolution of adder cell and
some are utilized for the ease of design
robustness silicon area ,delay & power
consumption . The paper studies full adder circuit which is made of different techniques. It
express number of transistors, area & power
consumption by circuit and how to minimize
number of transistors, area & power
consumption through a full adder circuit.
Priyanka Rathore ,PG Student ,Department of electronics &
communication Engineering /R.G.P.V University/U.E.
College, Ujjain, Ujjain,India/8878758487
Bhavna Jharia ,Associate professor &Head DEC,UEC, Ujjain
Ujjain ,India
The Boolean expression for the sum &carry bits
are as shown bellow.
Sum = (A B) Cin
Cout = A.B + Cin (A B)
Various Types of Full adder circuits:
1. HPSC Full Adder― The simultaneous
generation of XOR and XNOR outputs by pass
logic is beneficially exploited to a new
complementary CMOS stage to create full-swing
and balanced outputs so that adder cells can be
cascaded without buffer insertion [1].
Module I: XOR/XNOR -The XOR and XNOR
functions are to synthesize the XOR function and
to generate the XNOR function through an
inverter. This type of design has the
disadvantage of delaying one of the Y and Y‟
outputs. The switching speed is increased by
eliminating the inverter from the critical path [2].
Module II: XOR-The cross back 6-transistor
circuit can also be used. However, it suffers from
insufficient driving power due to the pass
transistors.
Module III: MUX-In Module III small no. of
transistors is generating „Cout‟ signal but in this
circuit one problem is threshold voltage drop full
swing signal is generate using by 4 transistor
circuit .This circuit is not provide enough driving
power .The new circuit is constructed by
complementary CMOS logic style.
Logic expression:
Cout =A.B + C (A B)
International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)
Volume 3 Issue 6, June 2014
2031
ISSN: 2278 – 1323 All Rights Reserved © 2014 IJARCET
Fig.1: Schematic diagram of the HPSC full
adder
As pass transistor logic has been known to
implement XOR function more efficiently than
the complementary CMOS, Module I and
Module I1 are implemented using pass-transistor
logic. For Module III, a new circuit structure is
created which gives rise to the performance gain
over those circuits to be compared [1] .The two complementary feedback transistors restore the
weak logic caused by pass transistors. They
restore the non full-swing output by either
pulling it up through PMOS to the power supply
or down through NMOS to ground so that
sufficient drive is provided to the successive
modules. In addition, since there is no direct path
between power-supply and ground, short circuit
current has been eliminated. The available XOR
and XNOR outputs from Module I to allow a single inverter to attached at the last stage. The
output inverter guarantees sufficient drive to the
cascaded cell. [3]
Cout ̍ = [AB + Cin (A B)]’
This circuit has inherited the advantages of
complementary CMOS, which has been proven
in to be superior in performance to all pass
transistor logic styles for all logic gates except
XOR at high supply voltage.
2. Hybrid Full adder― The full adder is
designed with hybrid logic styles. Its works at
ultra-low supply voltage. The pass logic circuit that generates the intermediate XOR and XNOR.
These outputs have been improved to overcome
switching delay problem [4]. The increase in the
transistor count of its complementary CMOS
output stage is compensated by its area efficient
layout. As shown in Fig. 2, the hybrid full adder
circuit can be analyzed in three sub modules. The
logic expressions
Y =A B
Y = (A B) ̍
Sum=Y Cin
Cout =A.B + Cin .Y
Module I: XOR/XNOR - The functions of
exclusive OR and exclusive NOR (XOR/XNOR)
are to synthesize the XOR function to generate
the XNOR function through an inverter. This
type of circuit has the disadvantage of delaying
the Y and Y‟ outputs [4] in a increase spurious
switching and glitches .The pass transistor circuit
with only six transistors is used to generate the
balanced XOR & XNOR. The inverter is used
for generating complement signal when the
switching speed is increased by eliminating the inverter from the critical path.
Module II: XOR-There are various choices for
Module 2. In Module 2, logic expression is
similar to that of Module I and the cross back 6-
transistor circuit is used .In M II there is
insufficient driving power due to the pass
transistors [7].
International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)
Volume 3 Issue 6, June 2014
2032
ISSN: 2278 – 1323 All Rights Reserved © 2014 IJARCET
Module III: MUX - In Module III small no. of
transistors are generating Cout signal but in this
circuit there problem of threshold voltage drop.
Full swing signal is generated by using 4
transistor circuit .This circuit does not provide
enough driving power .The new circuit is constructed by complementary CMOS logic
style [8].
Logic expression:
Cout = A.B+C (A B)
Fig 2: Schematic Diagram of hybrid full adder
3. Hybrid CMOS Full adder― This full adder is
based on a new XOR–XNOR circuit. This output stage advantage is good driving capability for
enabling cascading of adders without the need of
buffer [9]. This full adder is energy efficient and
outperforms several standard full adders without
trading off driving capability and reliability. The
new full-adder circuit successfully works in a
low voltage with excellent signal integrity and
driving capability [5].
Fig.3: Schematic Diagram of the hybrid cmos
full Adder.
The centralized full adders, XOR and XNOR
circuits are presented to generate the signals H
and H‟. These signals are passed on to module II
and III along with the carry from the previous
stage and the other inputs A and B to produce the
Sum and Cout. This circuit is shown in fig. 3.
Module I:-The module I uses XOR–XNOR
circuit. The XOR-XNOR circuit produces
balanced full-swing outputs. For a high speed
International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)
Volume 3 Issue 6, June 2014
2033
ISSN: 2278 – 1323 All Rights Reserved © 2014 IJARCET
operation the cross-coupled PMOS pull-up
transistors providing the intermediate signals
quickly. The two modules rely heavily on the
intermediate signal H and H „to produces two
signals H and H‟ .The delay response of module
I is critical [2].
Module II-The XOR –XNOR functions are
generated by an inverter. This circuit provides
good driving capability. In this circuit is free by
threshold loss and has the lowest PDP amongst
all circuits that are used for module II [5].
Module III-It employs the proposed hybrid-
CMOS output stage with a static inverter at the
output. This circuit has a lower PDP as compared to the other circuits. The static inverter
provides good driving capabilities as the inputs
are decoupled from the output the circuit is
provide low power consumption. [3].
4. CPL Full adder― In a CPL eliminated
PMOS transistor NMOS pass transistor use for
logic realization .The NMOS transistor use positive feedback .This type of circuit speed is
high [1].
Using by this phenomenon reduce power
consumption & reduce width of transistor. The
CPL adder is balanced circuit with respect to
generation of sum &carries out [6].
The number of transistors is more than
comparative other design. This is due
requirement of seven inverters to generate
complement signals [6]. This circuit design is very complex. It improves speed &minimizes
area.
Fig.4: Schematic Diagram of the CPL Full
Adder.
5. New 14T Full adder― The new XOR –XNOR
cells are also presented [2].This new cell circuit
works in certain bounds when the power supply
voltage is scaled down .It is known very well. The full adder circuit is best design by using
XOR-XNOR gates. Since the sum can be
expressed as an XOR function of all its inputs
and the „carry‟ as a multiplexer function
controlled by the XOR function. In a pass
transistor NMOS or PMOS the input is fed to the
source terminal & output is take drain terminal.
A pass network is an interconnection of a
number of pass transistors to achieve a particular
International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)
Volume 3 Issue 6, June 2014
2034
ISSN: 2278 – 1323 All Rights Reserved © 2014 IJARCET
switching function. The propagation of the signal
through the transistor is controlled by a signal
applied to its gate. In the case of an NMOS
transistor, logic „1‟ at the gate passes the input
from source to drain and logic „0‟ opens the
source to drain path. A PMOS transistor exhibits similar behavior with a control signal of logic
level 0 [11].
Fig. 5: Schematic Diagram of the New 14T Full
Adder
6. DPL Full adder― Two new full-adders cicuit
is made designing by DPL logic styles [12] and
SR-CPL [13]. The logic structures are presented
in fig 6 & 7. A full adder circuit designing is
using by DPL logic style. To made by XOR –
XNOR gate & multiplexer is based on pass transistor logic &we obtain by MUX sum output.
SR-CPL logic style is constructed by XOR-
XNOR gates [15].In both situations the and/or
gates have been built using a powerless &
groundless pass transistor respectively, and a
pass-transistor based multiplexer to get the
„Co‟output [12].
Fig. 6: Schematic Diagram of the DPL Full
Adder
International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)
Volume 3 Issue 6, June 2014
2035
ISSN: 2278 – 1323 All Rights Reserved © 2014 IJARCET
7. SRCPL― SR-CPL logic style is constructed
by XOR-XNOR gates .In both situation the
and/or gates have been built using a powerless
&groundless pass transistor respectively, and a
pass-transistor based multiplexer to get the „Co‟
output [14].
Fig. 7: Schematic Diagram of the SRCPL Full
Adder
Table:
Conclusion― The paper concludes that CPL is the best suitable design for full adder since it an
NMOS pass transistor network is used for logic
realization and eliminate the PMOS transistor.
Due to positive feedback and use of NMOS
transistors, the circuit is inherently fast. This
property is used to reduce the width of the
transistors to reduce power consumption without
much speed degradation. The proposed hybrid-
CMOS is output stage with a static inverter at the
output. This circuit has a lower PDP as
compared to the other existing designs. The static inverter provides good driving capabilities
as the inputs are decoupled from the output.
After the analysis and comparison of seven full
adders it is found that the DPL technique is the
best one. The SRCPL technique stands second to
the DPL technique.
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6 DPL 90nm 28 38.87 491.3
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International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)
Volume 3 Issue 6, June 2014
2036
ISSN: 2278 – 1323 All Rights Reserved © 2014 IJARCET
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Author Profile
Priyanka Rathore received B.E. degree in 2007 Electronics & communication
engineering from Ujjain engg. College, Ujjain
Madhya Pradesh and now a time M.E. in digital
communication from U.E.C. Ujjain (2011-2013)
This my review paper on VLSI Technology.