Comparative Analysis for Different Models of Carry Select Adders

7/25/2019 Comparative Analysis for Different Models of Carry Select Adders

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International Journal of Advanced R

Vol. 3, Issue 1, January 2016

Comparative

of C

M.Soundharya,Department o

ABSTRACT

In this Era, the signal processiidely used. In the digital signal proce

adder is the basic building block of acircuits. Today the requirements for m

delay, area, and power of adder circuit

efficiency of whole system which

technology to the next level. Even thou

Select Adder (CSLA) occupies more ar

used instead of ripple carry adde

propagation delay. In other models Bina

Converter (BEC) based Carry Select A

used which uses less number of logic re

conventional CSLA. But these CSLAs

efficient because it rejects one su

calculation. So the delay was not mo

reduced. In order to overcome this

reduced logic CSLA is used. But by

Diffusion Input (GDI) Technique can g

than this recently proposed reduced logiroposed technique provides low power

less propagation delay. By using this

CSLA the number of transistors req

circuit also minimized. So an efficient

can be achieved through this technique.

I. INTRODUCTION Todays modern electronics requir

with high speed, low power, less ar

circuits. The design with reduced

power will be very useful for portabl

devices. Reducing the delay of basic

will increase the efficiency of the e

But achieving these constraints are

task. So based on the applications thesare modified to get an efficient de

signal processing system has so man

the efficient adder design is an import

There are several designs for the a

Ripple Carry Adder (RCA) uses the si

but it has the main drawback of Carry

Delay [2]. The delay will be linearly i

the bit width of the numbers which ar

taken for the addition process. But

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All Rights Reserved 2016 IJARTET

nalysis for different

rry Select Adders

.E Student & R.Arunkumar, Assistant Professor f Electronics and Communication Engineering,

arpagam College of Engineering,

Coimbatore

g system is

ssing system,

ll the majornimizing the

improve the

drives the

h the Carry

a, it is been

r to avoid

y to Excess-I

der was also

sources than

re not more

after the

e effectively

problem the

using Gate

ve less delay

c CSLA. Theonsumption,

GDI based

ired for the

adder design

s the design

a for VLSI

delay, area,

and mobile

dder circuit

tire system.

not an easy

e constraintsign. Digital

adders. So

ant concern.

dder circuit.

mple design

Propagation

creases with

going to be

y using the

carry select adder the propag

effectively reduced. Even though i

the design is not more attractive be

usage of dual RCAs, which mean

will be obtained with the penaltyto overcome this drawback the BE

used. It replaces one RCA with one

Hence the area will be saved.

CSLA uses less number of logic r

the routing delay is slightly h

conventional CSLA. The another

adder circuit design is Common

(CBL) which uses less number of

and consumes low power but it h

Propagation Delay (CPD). The del

CSLA is proportional to the bi

numbers [3] which are going to bethe CPD of this adder CBL base

was proposed. SQRT CSLAs are i

large bit-width [5], [6] adders with

CBL based SQRT CSLA has long

BEC based SQRT CSLA. FromConventional and BEC based C

dependence and redundant logic

identified. The reduced logic CSL

drawbacks of Conventional an

CSLAs. The logic formulation o

CSLA is done based on the data

The reduced logic SQRT CS

the ability to give optimize

and power than this recen

reduced logic CSLA.

II. EXISTING SYST

A. Ripple Carry Adder

Ripple carry adder is designe

the full adders in serious. The fu

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odels

tion delay is

has less delay,

ause of the

s that the speed

f area. In orderbased CSLA is

add-one circuit.

he BEC based

esources [2] but

igher than the

one model for

Boolean Logic

logic resources

as longer Carry

y of CBL based

t width of the

add. To reduced SQRT CSLA

mplemented for

less delay. This

r delay than the

the analysis ofSLAs, the data

operations are

overcomes the

d BEC based

f reduced logic

dependence.

LA can have

delay, area,

tly proposed

M

d by cascading

ll adder here is


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responsible for adding two numbers w

The carry out of first stage is given as

of the next stage. Ripple Carry Adder uses the com

Even though it uses the simple adder

unrestricted bit length numbers, it i

widely used because of its Carry Propa

(CPD).

Figure 1: Ripple Carry Ad

The worst case delay of RCA is given

t = (n -1) tc + ts

Where,

tc Delay for Carry

ts Delay for Sum

From the above equation it is clear th

of Ripple Carry adder linearly increase

width of the numbers.

B. Conventional Carry Select Adder

In order to reduce the propagatio

Carry Select Adder is widely used

circuit of any arithmetic unit. The

Adder contains the two main units suc

and Carry Generation Unit (SCG) and

Carry selection Unit (SCS). Amon

units, the Sum and Carry Generation u

more logic resources of CSLA. So t

SCG unit is the main concern to red

resources. The SCG unit of four bit CS

two Ripple Carry Adders (RCA). T

Carry selection unit of four bit CSLmultiplexers. It performs two addition

one assuming Carry-in zero, and the o

is one. After the calculations of two a

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th carry [2].

the carry in

act Design.

esign to add

s not more

gation Delay

er

y

at, the delay

with the bit

n delay, the

s the adder

arry Select

as the Sum

the Sum and

these two

it consumes

e design of

ce the logic

LA contains

e Sum and

contains as in parallel,

ther carry-in

dditions one

sum is selected according to th

multiplexer.

Figure 2: Conventional Carry

Even though it reduces the pr

the design is not attractive due to t

RCAs. Because if we use dual RCA

adder design will increase thi

drawback of conventional CSLA.

Figure 3: Conventional

In the above diagram, it is

conventional CSLA has two RCAs.

performs the logical operations in

as Half Sum Generation (HS

Generation (HCG), Full Sum Ge

and Full Ca rry Generation (FCG).

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e carry in the

Select Adder

pagation delay,

e usage of dual

s the area of the

is the main

SLA

shown that a

The n bit RCA

four stages such

), Half Carry

neration (FSG),


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Figure 4: Logical operations of o

The logical expressions of the two

Adders of the Conventional CSLA is gi

S00(i) = A(i)B(i) C0

0(i)=A(i).

S10(i) = S0

0(i) C10(i-1)

C10(i)= C0

0(i)+S0

0(i).C1

0(i-1)C

0out = C1

0

S01(i ) =A(i)B(i) C01(i)=A(i).B

S11(i) = S0

1(i)C1

1(i-1)

C11(i)=C1

0(i)+S0

1(i).C1

1(i-1)C

1out=C1

1(n

C. BEC Based CSLA

In order to reduce the area and

adder circuit the BEC based CSLA i

BEC based CSLA design is sa

Conventional CSLA design. But the o

instead of using two RCAs it replac

with one add-one circuit [3], [7].

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e RCA

ipple Carry

ven as

(i) (1a)

(1b)

n-1) (1c)

(i) (2a)

(2b)

-1) (2c)

ower of the

s used. The

e as the

ly change is

s one RCA

Figure 5: BEC Based CS

From the above figure 5, RCA calc

and carry. The BEC unit receives t

generated by the RCA and proexcess-I code. The most signific

represents carry and the least

represent the sum. The logical ex

RCA are same as the expressions

CSLA. The expressions for BEC u

S11(i) = ~[S0

1(i)] C1

1(0) = S1

0(0)

S11(i) = S0

1(i) C10(i-1)

C11(i) = S1

0(i) . C1

1(i-1)

C1out = C10(n-1) C1

1(n-1)

For 1< i


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Carry Select (CS) unit The carry gene

constructed by two CGs (CG0 and C

the n bit operands (A & B) are given athe HSG unit. The HSG unit genera

and half carry. Both CG0 and CG1 rec

and carry generated by HSG. The C

units have the optimized designs for

carry bits. The Carry Selection unit

carry among the two carries based o

signal. According to the selected ca

unit generates the full sum word. T

design structures for CG0 and CG1 un

as in the following

The designs of HSG unit, CS unit, and

given as

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ation unit is

1). Initially

the input toes half sum

ive the sum

0 and CG1

fixed input

selects the

the control

ry the FSG

e optimized

its are given

FSG unit are

The logical expressions of reduced

S0(i)=A(i)xorB(i)and C0(i)=A(i).B(i

C0

1(i)=C01(i-1).s0(i)+C0(i) for (C

01(

C1

1(i)=C11(i-1).s0(i)+C0(i) for (C

11(

C(i) = C01(i) if Cin = 0

C(i) =C1

1(i) if Cin =1

Cout = C(n-1)

S(0) = S0(0) Cin S(i) = S0(i)

III. GDI BASED CARRY SEL

The main objective of the Gis to improve the speed, power, and

of the Carry select adder [1] when

existing ones.

Module 1 and module 2 are the

that generate the sum signal (SUgenerates the output carry signa

module is designed individually su

adder circuit is optimized in terms

and area.

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ogic CSLA are

)...(4a)

0)==0)

(4b)

)==1)

(4c)

(i-1)

CT ADDER:

I based CSLAtransistor count

compared to the

NOR modules

) and module 3l (Cout). Each

h that the entire

of power, delay,


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SIMULATION RESULTS:

OUTPUT WAVEFORM OF CSLA:

The above waveform gives the out

select adder. For this output wa

synthesis report and RTL diagrams are

in order to analyse the power, del

parameters of the adder circuit.

Conventional CSLA synthesis report

that the power used by the adder circui

and the number of logical devices

circuit is high. From the BEC B

synthesis report we can know that the

by the circuit is 10.294 and the logi

used in the circuit is very less when

the previous conventional CSLA. But

slightly higher than the conventibecause of the routing delay.

SYNTHESIS REPORT OF CONV

CSLA :

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ut of carry

veform the

given below

y and area

From the

e can know

t is 9.069 ns

used in the

ased CSLA

power used

al resources

compared to

the delay is

onal CSLA

NTIONAL

SYNTHESIS REPORT OF BEC

CSLA:

RTL DIAGRAM OF CONVENT

GATE LEVEL DIAGRAM OF

CONVENTIONAL CSLA :

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BASED

IONAL CSLA:

ONE LUT IN


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RTL DIAGRAM OF BEC BASED C

GATE LEVEL DIAGRAM OF O

BEC BASED CSLA:

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SLA :

E LUT IN

OUTPUT WAVEFORM OLOGIC CSLA:

SYNTHESIS REPORT OF RED

CSLA :

GATE LEVEL DIAGRAM OF

REDUCED LOGIC CSLA:

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REDUCED

UCED LOGIC

ONE LUT IN


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From the synthesis report of reduced

it is known that the power used by the

is 7.716 ns which is very much less th

used by conventional and BEC Based

the logic resources also much more

the previous Conventional and BEC Ba

GATE LEVEL DIAGRAM FOR O

REDUCED LOGIC CSLA:

REFERENCES

[1]. Arkadiy Morgenshtein, Ale

Israel A. Wagner, Gate Di

(GDI): A Power Efficient

Digital Combinatorial Circ

Transactions on very lIntegration Systems, Vol.10,

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ogic CSLA,

adder circuit

n the power

SLAs. And

educed than

sed CSLAs.

E LUT IN

ander Fish,

fusion Input

Method for

its, IEEE

arge scaleo.5, 2002.

[2]. Padma Devi, Ashima Gir

Singh, Improved Carry S

reduced area andConsumption, Internatio

Computer Applications,

2010.

[3]. K.Allipeera, S. Ahme

Efficient 64-bit Carry Sel

less delay and reduced ar

International Journal of

Research applications,

2012.

[4] R.Uma, Vidya Vijayan,

Sharon Paul, Area

Comparison of Adde

International Journal of

Communication systeVol.3, No.1, 2012.

[5]. M.Chithra, G.Omkares

Carry Select Adder havin

Delay, International Jour

Research in Electrical,

Instrumentation Engineeri

7, 2013.

[6]. Damarla Paradhasaradhi,

An Area Efficient Enhan

Select Adder, Internati

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Vol.3, Issue 6, 2013.

[7]. K.Mariya Priyadarshini

Kiran, N.Tejasri, T.C.VDesign of Area and Speed

Root Carry Select Ad

Adders, International

Scientific & Technology

Issue.6, 2014.

[8]. Kalapriya.K, KSN Raju,

Adder using BEC and RC

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Documents

Comparative Analysis for Different Models of Carry Select Adders