GIF-4201/GEL-7016 (Micro-électronique)

Combinational and Sequential CMOS Logic

Design, simulation, and layout

Mehdi Noormohammadi Khiarak, Gabriel Gagnon-Turcotte and

Benoit Gosselin

Department of Electrical & Computer Engineering

Laval University, Quebec City, Canada

January 2018

ii

Version history

Version Description Authors Date

1 Original version

Mehdi Noormohammadi

Khiarak, Gabriel Gagnon-

turcotte, and Benoit

Gosselin

Jan. 2018

iii

Contents

Introduction ..................................................................................................................................... 1

Objectives of This Lab .................................................................................................................... 1

Part one: .......................................................................................................................................... 2

DC and Transient Characteristics of the NAND, NOR, and adder ................................................ 2

Creating the schematic view ....................................................................................................... 2

Creating the symbol view from the schematic view ................................................................... 3

Creating a testbench .................................................................................................................... 3

DC characteristics of the CMOS NAND .................................................................................... 5

Switching characteristic of the NAND gate................................................................................ 6

Creating the schematic of the flip-flop ..................................................................................... 18

Creating a testbench .................................................................................................................. 18

Taping out your flip-flop layout for fabrication ....................................................................... 22

Part two: Design of a 4-bit asynchronous ripple counter .............................................................. 24

Ripple Counter .......................................................................................................................... 24

Checkout form .......................................................................................................................... 24

Rapport .......................................................................................................................................... 27

1

Introduction

The digital logic gates can generally be classified into combinational and sequential logic

circuits. Combinational logic circuits such as an adder, which created by basic logic gates such

as NOT, NAND, and NOR, at any time the output depends on the current input regardless of the

previous inputs. Whereas sequential logic circuits composed of not only logic gates, but also

memories such as flip flops and registers and their outputs depends on the current inputs and

previous value of which. This second Lab will cover the design, simulation, and layout of

combinational and sequential CMOS logic gates including NAND, NOR, half-adder, full adder,

Flip-Flop, and counter. In the first part, you will create a schematic view and symbol view of

CMOS NAND, NOR, half adder, and full adder. Then, you will characterize the gates in terms of

delay (speed) and DC characteristics through creating a test bench the same as you have already

done for an inverter in the lab 1. You will do the layout of the circuits and report the post-layout

simulation results as well as DRC and LVS. In the second part, you will implement a flip-flop by

NAND and NOT gates that you have already designed and then you will use the implemented

flip-flops to create a 4-bit asynchronous ripple counter. This second Lab will cover all steps for

simulating, implementing the physical design, extracting the physical circuit parameters, post-

layout simulating the physical circuit and generating a GDS-II format for submitting the chip for

fabrication. The Lab session are held in the computer Lab PLT-0105 at the Department of

Electrical and Computer Engineering, Laval University.

Objectives of This Lab

You will learn how to simulate and design a NAND, NOR, a D-flip flop, and an asynchronous

counter using the CMOS 180 nm TSMC design kit. You will be able to practice on layout and

post-layout simulation of practical circuits such as full adder and flip-flops. The proposed time-

table for this Lab is shown below. Note that you have to deliver the items listed for the

current week after each Lab session.

Week Deliverables

First week Implementation of the schematic of the NAND and

NOR, and adders and then simulate them using a

testbench;

Placement of cells and pins in Layout XL;

Post layout simulation

Second week Implementation of D flip-flop.

Implementation of 4-bit asynchronous counter

Layout

Post layout simulation

Report the lab2

2

Part one:

DC and Transient Characteristics of the NAND, NOR, and adder

In this part, you will create a schematic view and a symbol view of three inputs NAND and two

inputs NOR gates. Then, you will create a test bench to simulate your gates and answer

questions. First you will follow the instructions for the NAND gate and then you will repeat the

same procedure for the NOR gate.

Creating the schematic view

After running Cadence, create a new library and a new cell having the following properties.

Table 1. Parameters of new library and cell.

Parameter Value

Library Name Lab2

Attached Technology File cmosp18

Cell Name NAND

View Name Schematic

Tool Composer-schematic

Open your schematic view, and add the symbol views of an nfet and a pfet cell from the

cmosp18 library. Make sure the MOSFETs have the following properties:

Table 2. Parameters of transistors.

Nfet Pfet

Name M0-M2 Name M3-M5

Width 3 µm Width 2 µm

Length 180 nm Length 180 nm

Then, add pins to your schematic with following properties:

Table 3. List of pins in the schematic.

Pin name Direction

A, B, C Input

OUT Output

vdd inputoutput

vss inputoutput

3

Wire up the transistors and the pins as shown in Fig. 1 (a). Your NAND schematic is now ready.

To save your schematic, click on “design-> check and save”

Creating the symbol view from the schematic view

To make a symbol from a schematic view, select design -> create cellview -> from cellview in

the Virtuoso schematic editor with your schematic of the NAND opened. Click Ok after the

“cellview from cellview” dialog box appears. Rearrange pins in the “symbol generation options”

dialog box as follow and click Ok.

Table 4. Pin position of the schematic.

Pin position Pin name

left pin A,B,C

right pin OUT

top pin vdd

bottom pin vss

A symbol of the NAND has been created. The default symbol is a rectangle. Edit your symbol

accordingly to the symbol shown in Fig. 1(b).

Tip: In order to create the symbol of the NAND, separate the pins from the default symbol.

Then, delete the rectangle. After that, use Add -> shape -> line and arc to draw a triangle and

the arc, and then, Add -> shape -> circle to draw a circle. Finally, connect the pins to the

triangle and to the circle.

Creating a testbench

Create a new schematic in library Lab2 and name it “testbench”. Open the schematic view of this

new cell, and add your NAND symbol into it. Connect a dc source at the input of the inverter,

and a capacitor of 1 pF at the output. Use the “capacitor” element from the cmosp18 library for

this 1-pF capacitor. Add “vdd” and “vss” symbols from library “analoglib” and connect them to

the vdd and vss pins of the NAND symbol. In order to implement a dc supply voltage source,

connect the vss node to a “tiedown” cell taken from library cmosp18, and connect the vdd

symbol to a dc voltage source, like in Fig. 2. Connect three DC sources to the inputs, note that

the high logic level is determined by 1.8V while the low-logic level by ground so that when you

want to put “1” logic level to the NAND input, you should set the input source to 1.8V. Double-

click on the inputs and output wires and name them “A”, “B”, “C” and “OUT” respectively, as

shown in Fig. 2. The final schematic of your testbench must look like the one in Fig. 2. Double-

click on the input and output wires and name them “Vin” “Vout” respectively, as shown in Fig.

2. Add “vdd” and “vss” symbols from library “analoglib” and connect them to the vdd and vss

pins of the inverter symbol. In order to implement a dc supply voltage source, connect the vss

4

(a)

(b)

Fig. 1. (a) Wire up components in schematic view b) Make a symbol of NAND.

node to a “tiedown” cell taken from library cmosp18, and connect the vdd symbol to a dc voltage

source, like in Fig. 2. The final schematic of your testbench must look like the one in Fig. 2. We

will use this schematic to simulate the NAND characteristics.

5

NAND gate part Power supply

Fig. 2: Testbench schematic.

Q1: Complete the following truth table by DC simulation:

Table 5. NAND gate truth table

A B C OUT

L L L

L L H

L H L

L H H

H L L

H L H

H H L

H H H

DC characteristics of the CMOS NAND

Perform a DC sweep analysis to obtain the voltage transfer curve (VTC) of the NAND: sweep

one of the inputs while keeping two other inputs at high logic level (1.8V). For example, connect

6

the inputs B and C to a constant 1.8V while sweeping the input A from 0V to 1.8V by

performing a “dc” Analysis and observe the output. In Virtuoso Analog design environment, go

to Outputs -> to be plotted -> select on schematic. Select the input and output voltages of the

inverter by clicking on the input and output wires in the schematic. Click the “Run Simulation”

button (the green light) or go to Simulation -> Run.

Q2. Report the VTC curve of the NAND. (Tip: use window -> hardcopy in the waveform

window to print the curve).

Q3: Determine the NAND gate threshold voltage from the curve for the sweeping of the different

inputs.

Q4. Report VIL,VIH, VOL, and VOH. Note that VIL and VIH is defined the point on the curve at

which the slope of the VTC is -1 or for non-inverting gate the slope is one (as shown in the

following figure).

Noise margin and voltage mapping

Switching characteristic of the NAND gate

Perform a transient analysis for the NAND gate that you designed in the previous part to obtain

its dynamic performance. Apply an output load of 1pF and replace the previous input DC voltage

source (vdc) with a “vpulse” source. Keep two inputs at high logic level (1.8V) and connect

“vpulse” to the third input. Fill out the Vpulse parameters according to Table 6.

7

Table 6: Parameters of the Vpulse source simulating the clock signal.

Voltage 1 Voltage 2 Delay time Rise time Fall time Pulse width Period

0 V 1.8 V 0 50 ps 50 ps 10 ns 20 ns

Q5: Set the stop time of the transient analysis to 2us and accomplish the table 7. Note that the

propagation delay is defined the difference between the input signal which reaches 50% of its

final value and the output which approaches to its 50% final value.

Table 7. Switching characteristic of the NAND gate.

A B C Rise time

(tLH)

Fall time

(tHL)

Propagation delay

(tp)

Pulse width

of the

vpulse

Period of

the vpulse

H H vpulse 1u 2µs

H vpulse H 1u 2µs

vpulse H H 1u 2µs

Q6. Plot Vout(t) and Vin(t) for each status of the previous table.

Q7: Explain why the rise, fall, and propagation delay changes as the different inputs connected to

the vpulse.

Q8. Plot the NAND gate dynamic power and calculate its average power. Connect the inputs A

and B to high logic level while C to the vpulse. To plot the power after running the simulation,

go to ADE and select the calculator as shown in Fig.3. After the calculator is opened, select “it”

from the calculator and then select the “vdd” terminal. Afterward, multiply it by vdd (1.8V) as

shown in Fig. 4 and plot the figure. You can use the special function of the calculator to calculate

the average value.

8

Fig.3 Calculator in the ADE

Fig.4. Calculator for the power calculation and plot.

Q9. Obtain the average and the dynamic power of the NAND and report them.

9

NAND gate Layout and post layout simulation:

The layout and post-layout simulation procedure is the same as Lab1 and we will avoid more

explanations on the layout. Just for the reminder, you can follow the following steps for the

layout.

Step 1: Create a new layout view from the schematic of the NAND. Launch the Layout editor by

selecting “Tools -> Design Synthesis -> Layout XL” in the Schematic editor. Select “Create

new” in the “Startup Option” window that popped-up and click OK. Click OK on the “Create

New File” dialog box. It opens a Virtuoso Layout XL window linked to your schematic.

Arrange the following settings into the Layout editor and into the CIW window before moving

forward.

Setting Actions

Increase the grid resolution Select “Options -> Display” and use the following

parameters:

Set the “Minor Spacing” to: 0.01;

Set the “Major Spacing” to: 0.1 then click

OK.

Increase the number of

undo

In the CIW window, select “options -> user

performances”. Then, change the undo limit to 10,

and click OK.

Step 2: In the Virtuoso Layout XL editor, select “Design -> Gen From Source”. The “Layout

Generation Options” pops-up.

Step 3: The “Layout Generation Options” window let you assign a layer for each pin. The

default layer for the I/O pins is metal2, while it is metal1 for the power rails Vdd! and Vss!.

Make sure that the “Layer/Master” option is set to metal2-dg and the “Create” option is enabled.

Also, select “Label” for the field “Pin Label Shape”. This will add a label to each of the

generated I/O pins. Then, click “Apply”.

Step 4: Since the power rails are usually implemented in metal1, the pins for Vss! and Vdd!

must be changed to the metal1 layer. In order to do that, select the Vdd! and Vss! pins like in

Fig. 5, change the “layer/master” to metal1-dg, and click the “Update” button. Then, click OK.

The layouts of your individual cells and pins are generated in the Layout editor. Each standard

cell is represented by a red rectangle in the layout. In fact, these rectangles delimit the boundary

of the layouts of the cells. The pins might be hard to find in the layout view. To get some clue of

where the generated pins have been placed by default in the layout, select “Edit -> Select ->

Select All” or use “ctrl-a” hot key. This will highlight all components in the layout.

10

Step 5: In addition to generate pins, the previous step also creates a purple rectangle within the

“prbound-dg” layer. This layer doesn’t have any physical significance, but its purpose is to

delimit the boundary of the layout of the whole chip.

Q10: Generate the layout components automatically from the schematic of your NAND gate

using the command “Generate from source”. Then, take a screen shot of the generated layout and

put it in your report (as shown in Fig.5).

Fig.5. NAND gate component layout.

Fig.6. NAND gate layout

The complete NAND gate layout is shown in Fig.6. Note that during the layout, you should

check DRC to make sure that the layout meets the design rule requirements.

11

Q11: Report the completed layout, extracted Layout, DRC, LVS results.

Q12: Perform a post-layout simulation for the NAND gate and complete the table 8 and 9. Then,

compare the results obtained from the post layout simulation with the schematic.

Table 8. NAND gate truth table

A B C OUT

L L L

L L H

L H L

L H H

H L L

H L H

H H L

H H H

Table 9. Switching characteristic of the post-layout simulated NAND gate.

A B C Rise time

(tLH)

Fall time

(tHL)

Propagation delay

(tp)

Pulse width

of the

vpulse

Period of

the vpulse

H H vpulse 1u 2µs

H vpulse H 1u 2µs

vpulse H H 1u 2µs

12

NOR gate:

The schematic, layout, and post layout simulation of NOR gate is the same as the NAND gate.

This basic gate will be necessary to implement a half and a full adder in the next section. Table

10 illustrate the transistors size of the NOR gate shown in Fig. 7.

Table 10. Parameters of transistors.

Nfet Pfet

Name M0-M1 Name M2-M3

Width 1 µm Width 4 µm

Length 180 nm Length 180 nm

Fig. 7. NOR gate schematic and circuit symbol.

13

Q13: Complete the following truth table by simulation:

A B OUT

L L

L H

H L

H H

Q14. Report the VTC curve of the NOR. Keep one of the input at zero logic level and sweep

another input from 0 to 1.8V.

Q15: Determine the NOR gate threshold voltage from the curve for the sweeping of the different

inputs.

Q16. Report VIL,VIH, VOL, and VOH.

Q17: Set the stop time of the transient analysis to 2us and accomplish Table 11. Note that the

propagation delay is defined the difference between the input signal which reaches 50% of its

final value and the output which approaches to its 50% final value.

Table 11. Switching characteristic of the NOR gate.

A B Rise time

(tLH)

Fall time

(tHL)

Propagation delay

(tp)

Pulse width

of the

vpulse

Period of

the vpulse

L vpulse 1u 2µs

vpulse L 1u 2µs

Q18. Plot Vout(t) and Vin(t) for each status of the previous table.

Q19: Explain why the rise, fall, and propagation delay changes as the different inputs connected

to the vpulse.

Q20. Plot the NAND gate dynamic power and calculate its average power. Connect the inputs A

to low logic level while B to the vpulse.

Q21. Obtain the average and the dynamic power of the inverter and report them.

14

NOR gate Layout and post layout simulation:

The layout and the post-layout simulation procedure is the same as the NAND and NOT gate. A

sample layout of the NOR gate is shown in Fig.8. Note that drawing layout of circuits is not

unique.

Fig.8. NOR gate layout

Q22: Report the layout, the extracted Layout, DRC, LVS results.

15

Q23: Perform a post-layout simulation for the NOR gate and complete Table 12. Then, compare

the results obtained from the post layout simulation and the schematic.

A B OUT

L L

L H

H L

H H

Table 12. Switching characteristic of the post-layout simulated NAND gate.

A B Rise time

(tLH)

Fall time

(tHL)

Propagation delay

(tp)

Pulse width

of the

vpulse

Period of

the vpulse

L vpulse 1u 2µs

vpulse L 1u 2µs

16

Adder design:

The half adder is an example of a simple combinational logic gate and is a major

component of an Arithmetic Logic Unit (ALU) of a CPU. The half adder adds two

one-bit binary numbers (AB), the output is sum of the two bits (S) and the carry

(C). A full adder is constructed using two half adders, and it adds three input bits to

produce a sum bit and a carry bit. An N-bit binary adder can be created by

cascading full adders. The schematic and the symbol and of a half adder is shown

in Fig.9.

HAA

B

S

C

AB

S

C

Fig.9. schematic and symbol of the half adder

Q24: report the schematic and test bench of the half adder circuit.

Q25: fill out the following truth table using the simulation for the half adder.

Inputs Outputs

A B C S

L L

L H

H L

H H

17

Q26: report the input and output waveform by connection Vpulse to A and B. try

to make a delay for one of the input Vpulse to create all possible logic levels.

HAA

B

S

CHA

A

B

S

C

Co

S

A

B

Ci

Fig.10. full adder circuit schematic

Using the half adder module, NOR, and NOT, construct a full adder shown in

Fig.10.

Q27: report the schematic and test bench of the full adder circuit.

Q28: To verify the operation of the full adder, fill out the table below and report

the circuit schematic.

Inputs Outputs

A B Ci Co S

L L L

L L H

L H L

L H H

H L L

H L H

H H L

H H H

Q29: report the input and output waveform. Just report for few possible states.

18

Part2:

D Flip-Flop Design:

Flip flops (FF) are sequential logics (data storage elements) which store logic states. The flip

flops output state is updated at the clock signal edge either by rising edge or by falling edge

which depends on the FF type. FFs are controlled by a clock signal and one or two data input

signals, typically two outputs are available namely, Q and Q_b where Q_b is the inversion of Q.

There are several variations of FFs including JK and SR type FFs. However, the most common

FF used in digital integrated circuits is the D-type FF (DFF). In a DFF, the value of input D is

transferred to the output Q at the rising (or falling) clock edge and held there until the next rising

(or falling) edge.

Creating the schematic of the flip-flop

After opening Cadence, create a new library and add a new cell to this library with the following

properties;

Parameter Value

Library Name Lab2

Attached Technology File cmosp18

Cell Name D flip_flop

View Name Schematic

Tool Composer-schematic

The schematic of the D flip-flop with SET and REST is shown in Fig. 11. Save your schematic

by selecting “design -> check and save”, and ask your TA to verify your schematic before

moving forward to next sections.

Creating a testbench

Create a new schematic cell view in your “Lab2” library and name it “testbench”. Open the new

schematic cell view and add the symbol of your flip-flop into it. Connect DC sources (sources

Vdc from the cmosp18 library) to input pins S, R, and D of the flip-flop in order to simulate

logic levels (For the case of an input logic 1, put Vdc = 1.8 V, whereas for an input logic 0 put

Vdc = 0V), and connect 10-fF capacitors at output pins Q and Q_b. Put labels on the input and

output wires and name them similarly to symbol pins (Fig. 2). Connect a Vpulse source to the

“CLK” pin to simulate a clock signal and set its parameters according to Table 13.

19

S

CLK

R

D

Q

Q_b

D

CLK

S

R

Q

Q_b

DFF

Fig11. D flip-flop with set and reset (SET and RSEST are active low)

Table 13: Parameters of the Vpulse source simulating the clock signal.

Voltage 1 Voltage 2 Delay time Rise time Fall time Pulse width Period

0 V 1.8 V 0 50 ps 50 ps 10 ns 20 ns

Q30: On which edge of the clock does the output of the flip-flop gets updated?

Q3:1 By applying different logic values to the inputs of the flip-flop, complete the truth

Table 14 and put it in your report.

Table 14: Truth table of the flip-flop.

S R D Clk Q Q_b

0 0 0

… … … … … …

Q32: Explain the behaviour of the circuit when the R and S pins voltage goes low.

20

Q33: Perform a transient analysis with the following parameters (see bellow). Then, show

the input and output waveforms in separated graphs, and print them into your report (Tip:

After the simulation has completed, the waveforms are all displayed in the same graph. In

order to see each waveform in a separate graph, select “axes -> to strip” from the

Waveform window).

Configuration of transient analysis for Q33.

Stop time = 300ns

Parameters of the source connected to D

Vpulse source

Voltage

1

Voltage

2

Delay

time

Rise

time

Fall

time

Pulse

width

Period

0 V 1.8 V 0 50ps 50ps 60ns 120ns

Parameters of the source connected to S

Vpulse source

Voltage

1

Voltage

2

Delay

time

Rise

time

Fall

time

Pulse

width

Period

0 V 1.8 V 0 50ps 50ps 40ns 80ns

Parameters of the source connected to R

Vpulse source

Voltage

1

Voltage

2

Delay

time

Rise

time

Fall

time

Pulse

width

Period

0 V 1.8 V 160ns 50ps 50ps 60ns 300ns

Parameters of the source connected to CLK

Vpulse source

Voltage

1

Voltage

2

Delay

time

Rise

time

Fall

time

Pulse

width

Period

21

0 V 1.8 V 0 50ps 50ps 10ns 20ns

Q34: According to the waveforms obtained in Q6 explain the operation of the circuit.

Q35: Generate the layout components automatically from the schematic of your flip-flop

using the command “Generate from source”. Then, take a screen shot of the generated

layout and put it in your report.

Q36: Perform cells and pins placement according to the steps detailed above. Take a

screenshot of your completed placement and put it in your report.

Q37: Do the routing of the layout manually like you did in Lab1 and show the complete

layout of the flip-flop in your report. You are allowed to use metal layers up to metal5.

Performing several DRC checks during the implementation of the routing is a good

practice. Otherwise, DRC errors accumulate and render the task of fixing them difficult.

Q38: Run a DRC on your flip-flop layout by using Calibre. Then, take a screenshot of the

generated DRC report and put it in your report.

Q39: Run a LVS on the layout of your flip-flop using Calibre. Then, take a screenshot of

the LVS summary and put it in your report. If your LVS has violations, fix all mismatches.

Q40: Obtain the parasitic extraction of the flip-flop for different types of extracted

parameters: a) for the default extracted circuit b) with parasitic capacitors and c) with

parasitic resistors. Take a screenshot of each extracted view and put them in your report.

Q41: Perform a transient analysis (for the post-layout simulation) with following

parameters.

Q42: Print the inputs and outputs waveforms of the flip-flop into your report and explain

the circuit operation by referring to them. (To see each waveform in a separate graph, go to

“axes -> to strip” from waveform window).

Q43: Is there any differences between the waveforms obtained in Q42 and the waveforms

obtained in Q33? Explain any difference.

22

Taping out your flip-flop layout for fabrication

The last step consists in exporting the layout into a GDS-II format that can be submitted to a chip

foundry for fabrication. The layout of the flip-flop will be exported into a file with a “.gds”

extension. To export your layout into a gds file, select “File -> Export -> Stream” from the

command interpreter window (CIW). The “Virtuoso Stream Out” window opens (Fig. 12). Fill in

the fields as follow: Click the “Library Browser” button and select the layout view of your flip-

flop into your Lab3 library and click the “Close” button.

Fig. 12: Virtuoso Stream Out window.

Leave other fields unchanged. Make sure that the field “Error Message File” contains the string

“PIPO.LOG”. Click on the “User-Defined Data”. The “Stream Out User-Defined Data” window

opens (Fig. 13).

23

Fig. 13: Stream Out User-Defined Data window.

In the “Layer Map Table” field type in

/CMC/kits/cmosp18.5.2/cmosp18.strmMapTable”.

Make sure to select “geometry” for the field “Convert Pin to”. Leave other fields unchanged.

Click OK to close the “Stream Out User-Defined Data” window. Click Ok on the “Virtuoso

Stream Out” window. A message will pop up (Fig. 14) showing that the stream out file has been

generated successfully.

Fig. 14: Successful Stream Out Popup Message.

Q20: Generate your flip-flop gds file and upload it along with your report into Pixel (use an

archive including both files).

24

Part two: Design of a 4-bit asynchronous ripple counter

In this last part of the Lab, you will design a 4-bit synchronous counter (Fig. 15) from the

schematic to the tape out of the chip, like you did for the flip-flop in the previous part. The 4-bit

asynchronous counter has synchronous reset and set (input pins RST and SET). The synchronous

reset allows clearing the count to “0000”.

First, you will implement the schematic of the counter. Then, you will generate the layout from

the schematic using Layout XL and you will implement the routing manually. Finally, you will

simulate the counter under different conditions to assess its performance.

Ripple Counter

A ripple counter is an asynchronous counter where only the first flip-flop is clocked by an

external clock. All subsequent flip-flops are clocked by the output of the preceding flip-

flop. Asynchronous counters are also called ripple-counters because of the way the clock pulse

ripples it way through the flip-flops.

D

CLK

S

R

Q

Q_b

DFF

D

CLK

S

R

Q

Q_b

DFF

D

CLK

S

R

Q

Q_b

DFF

D

CLK

S

R

Q

Q_b

DFF

A B C D

RST

SET

In

Fig .15: Schematic of the 4-bit counter.

Q21: Is this counter is an up counter or a down counter? Explain your answer.

Q21: modify the counter to count up maximum 1001 and start over again.

Checkout form

Similarly to the implementation of the flip-flop in the previous section, implement the layout of

the ripple counter by following the steps listed bellow. Include this checkout form and all

requested items in your report.

1. Design the schematic of the counter.

25

Indications: Reuse the schematic of your D flip-flop. Print the schematic of the

implemented counter and put it in your report.

2. Generate a symbol of the counter from the schematic and create a testbench.

Indications: Print the schematic of the testbench and put it in your report.

3. Perform a transient analysis on the counter using spectre.

Indications: Use a stop time of 2 µs for the transient analysis. Use a Vpulse source with a

frequency of 1 MHz and rise and fall times of 500ps for clock signal. Report signals A, B,

C, and D in your report and explain the behavior of the counter by referring to these

signals.

4. Generate the layout of the counter from the schematic using Layout XL.

Indications: Reuse the layout of the D flip-flop implemented in previous section. Ask

your TA to guide you through the proper configurations to reuse your layout into

Layout XL if necessary.

You are allowed to use metal layers up to metal5. Apply all placement and routing

methods that you learned up to now. The two groups with the smallest reported chip

area will receive a bonus of five percent to the final mark.

5. Run the DRC and the LVS on your layout using Calibre.

Indications: Correct all DRC errors and make sure your layout passes LVS. Ask your TA to

verify your LVS results before moving forward to next sections.

6. Extract the parasitic components of your layout.

Indications: Print the extracted circuits and put it in your report.

7. Print the layout of your counter and put it in your report.

Indications: Indicate the size of your layout using the ruler (hot key “k”).

8. Perform a post-layout simulation of the counter for different clock frequencies.

Indications: Measure the rise time, fall time and propagation delay of the counter

according to parameters given bellow and fill in Table 4 with your results. Compare your

results with the results obtained in 3. Increase the clock frequency of the counter until

noticeable differences occur at the counter output.

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Simulation parameters: Simulate the circuit for clock frequencies of 1, 10, 50 and 100

MHz and for load capacitors of 10-fF connected at the four outputs. Refer to your

reference book for the definitions of the rise time, fall time and propagation delay.

9. Perform a post-layout simulation of the counter for different output loads.

Indications: Measure the rise time, fall time and propagation delay of the counter

according to parameters given bellow and fill in Table 5 with your results.

Simulation parameters: Simulate the circuit for a clock frequency of 10 MHz and for

different output loads of 10, 20, 300 and 4000-fF connected at A, B, C and D. Refer to

your reference book for the definitions of the rise time, fall time and propagation delay.

Q22: Which one of the rise time or the fall time is higher in general? Explain your answer.

Table 4: Measurements of the rise time, fall time and propagation delay at different output nodes

with 10-fF capacitive loads and for different clock frequencies.

Rise Time (ps) Fall Time (ps) Propagation Delay (ps)

fclock

(MHz) D C B A D C B A D C B A

1

10

50

100

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Table. 5: Measurements of the rise time, fall time and propagation delay at different output nodes

for different capacitive loads and for a clock frequency of 10MHz.

Rise Time (ns) Fall Time (ns) Propagation Delay (ns)

Cload (fF) D C B A D C B A D C B A

10

20

300

4000

Rapport

Votre rapport doit contenir les sections suivantes :

o Une introduction

o Vos réponses aux questions

o Toutes les courbes et les images d’écran demandées

o Une conclusion

Utiliser la dernière page de cet énoncé comme première page de votre rapport. Veuillez déposer

le rapport dans la boîte prévue à cet effet avant la date limite.

28

GIF-4201/GEL-7601 (Micro-électronique)

Combinational and Sequential CMOS Logics

Nom Matricule

1.

2.

Signature de l’assistant :

Date :