Solid-State Electronics 78 (2012) 62–67

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Solid-State Electronics

journal homepage: www.elsevier .com/locate /sse

CoInGaAs as a novel self-aligned metallic source/drain material for implant-lessIn0.53Ga0.47As n-MOSFETs

Ivana a,b, Eugene Y.-J. Kong a, Sujith Subramanian a,b, Qian Zhou a, Jisheng Pan c, Yee-Chia Yeo a,b,⇑a Department of Electrical and Computer Engineering, National University of Singapore (NUS), Singapore 117576, Singaporeb NUS Graduate School of Integrative Sciences and Engineering, National University of Singapore (NUS), Singapore 117576, Singaporec Institute of Materials Research and Engineering, A⁄STAR (Agency for Science, Technology and Research), 3 Research Link, Singapore 117602, Singapore

a r t i c l e i n f o a b s t r a c t

Article history:Available online 29 June 2012

The review of this paper was arranged byProf. A. Zaslavsky

Keywords:CobaltInGaAsContact metallizationSelf-aligned

0038-1101/$ - see front matter � 2012 Elsevier Ltd. Ahttp://dx.doi.org/10.1016/j.sse.2012.05.030

⇑ Corresponding author at: Department of ElectricaNational University of Singapore, 10 Kent Ridge CSingapore. Tel.: +65 6516 2298; fax: +65 6779 1103.

E-mail addresses: eleyeoyc@nus.edu.sg, yeo@ieee.oURL: http://www.eng.nus.edu.sg/eleyeoyc (Y.-C. Y

CoInGaAs, a new self-aligned silicide-like source/drain (S/D) metallic contact, was demonstrated onIn0.53Ga0.47As n-MOSFET. Co reacts with In0.53Ga0.47As at temperatures as low as 350 �C, forming metallicmaterial comprising regions rich in cobalt gallium and cobalt arsenide. The CoInGaAs formed exhibitsSchottky characteristic on p-type In0.53Ga0.47As, and is thus suitable for S/D material. It also exhibitsohmic behavior on n-type In0.53Ga0.47As (doping concentration of �5 � 1019 cm�3) with contact resis-tance and specific contact resistivity of �1.12 kX lm and �6.25 � 10�4 O cm2, respectively. The integra-tion of CoInGaAs as metallic S/D material in In0.53Ga0.47As n-MOSFET produces reasonably well-behavedoutput characteristics.

� 2012 Elsevier Ltd. All rights reserved.

1. Introduction

Indium gallium arsenide (InxGa1�xAs or InGaAs) has higher elec-tron mobility than silicon (Si) and is an attractive channel materialfor replacement of Si in future n-channel metal oxide semiconduc-tor field effect transistors (n-MOSFETs) [1–12]. In many reports ofInGaAs channel n-MOSFETs, the metal contacts formed on then+-doped source/drain (S/D) regions are non-self-aligned to thegate [13–16], i.e. a gap exists between the metal contact andthe gate. Therefore, the n+-doped region between the metal contactand the channel contributes substantially to the total series resis-tance. It is therefore desirable to reduce the spacing between thecontact and the gate. In fact, it is even more desirable to eliminatethe contact-to-gate spacing, or to adopt a self-aligned contactmetallization scheme.

Self-aligned contact metallization such as the self-aligned silici-dation process is commonly used in Si complementary metal–oxide–semiconductor (CMOS) technology [17–28]. For InGaAsn-MOSFETs, a self-aligned silicidation-like contact metallizationwould depend on selective reaction of a deposited metal withthe underlying InGaAs S/D material, forming a metallic material.The metallic material formed should exhibit ohmic behavior on

ll rights reserved.

l and Computer Engineering,rescent, Singapore 119260,

rg (Y.-C. Yeo).eo).

n-InGaAs and preferably Schottky behavior on p-InGaAs. It cantherefore be used not only as contact material but also possiblyas a S/D material itself. In addition, an etchant is needed for the re-moval of the unreacted metal without removing the metallic mate-rial formed. Recently, a self-aligned contact metallization processinvolving reaction of Ni with InGaAs to form Ni-InGaAs was dem-onstrated [29–35]. In this work, we explore Co as a new alternativemetal for self-aligned contact metallization on InGaAs n-MOSFETs.

In this paper, we report the demonstration of CoInGaAs as acontact metallization material and the integration of CoInGaAsself-aligned contact technology on an implant-less InGaAs n-MOS-FET. The process involves reacting cobalt (Co) with In0.53Ga0.47As attemperatures as low as 350 �C to form CoInGaAs. The CoInGaAsmetallic layer forms a Schottky contact on p-type In0.53Ga0.47Asand an ohmic contact on n-type In0.53Ga0.47As. This makes it possi-ble to use CoInGaAs as a metallic S/D material. Device characteris-tics of InGaAs n-MOSFET with CoInGaAs metallic S/D will bediscussed.

2. CoInGaAs contact metallization module: CoInGaAs formationand contact resistance extraction

2.1. CoInGaAs formation

The starting substrates are 2-in. p-type InP (100) substrates(doping concentration of �1 � 1019 cm�3) with an epitaxiallygrown 500-nm-thick p-type In0.53Ga0.47As (with a doping concen-tration of �2 � 1016 cm�3) layer. Following native oxide removal

Fig. 1. TEM images of CoInGaAs formed by annealing 20 nm of Co on In0.53Ga0.47Asat (a) 300 �C, (b) 350 �C, and (c) 400 �C. Most of the as-deposited Co remainedunreacted with In0.53Ga0.47As at 300 �C. In contrast, at 350 �C, all the Co wasconsumed, forming a CoInGaAs layer. Energy Dispersive X-ray Spectroscopy (EDX)was performed at various spots in the CoInGaAs film formed at 350 �C, indicated bythe spots labeled 1 to 4. After annealing Co on In0.53Ga0.47As at 400 �C, a very non-uniform CoInGaAs layer with a rough interface was formed.

Spot 1 Spot 2 Spot 3 Spot 40

20

40

60

80

100

Ato

mic

Per

cent

age

(at%

)

Co

In

Ga

As

350 °C CoInGaAs

Fig. 2. EDX reveals the elemental atomic percentage found in localized spots atvarious parts of the CoInGaAs film formed at 350 �C, as indicated in Fig. 1b. The EDXspot size is �10 nm. It is observed that the CoInGaAs film comprises a Co- and Ga-rich layer on top of a Co- and As-rich layer.

20 30 40 50 60 70 80 90

400 °CCoInGaAs

♦♦

♦

♦

Δ Δ

ΔX

RD

Int

ensi

ty (

a.u.

)

2θ (θ (degree)

350 °CCoInGaAs

♦ Cobalt GalliumΔ Cobalt Arsenide

Δ

Fig. 3. Grazing angle XRD spectra of CoInGaAs samples formed at 350 �C and400 �C, indicating the presence of CoGa and CoAs phases.

200 250 300 350

10

12

14

16

18

20

22

Shee

t R

esis

tanc

e R

sh (

Ω/

)

Annealing Temperature ( °C)

Annealing time = 60 s

Fig. 4. Sheet resistance Rsh measured after annealing 20 nm of Co on In0.53Ga0.47Asat various temperatures ranging from 200 �C to 350 �C for 60 s. The Rsh of thesample annealed at 350 �C is that of the CoInGaAs film. The dashed line indicatesthe Rsh of as-deposited Co.

Ivana et al. / Solid-State Electronics 78 (2012) 62–67 63

in dilute hydrofluoric acid solution,�20 nm of Co was deposited bysputtering. The Co-on-In0.53Ga0.47As sample was then cut intosmaller pieces. The pieces were annealed for 60 s in a Rapid Ther-mal Processing (RTP) tool at different temperatures ranging from200 �C to 400 �C.

The transmission electron microscope (TEM) images for�20 nm of Co deposited on In0.53Ga0.47As and annealed at varioustemperatures for 60 s are presented in Fig. 1. For the sampleannealed at 300 �C (Fig. 1a), a change at the interface between Coand In0.53Ga0.47As was observed. Energy-dispersive X-ray spectros-copy (EDX) confirmed that the region near the surface consists ofunreacted Co. Immediately below the unreacted Co, EDX measure-ments gave 35.2 at.%, 11.4 at.%, 5.9 at.% and 47.5 at.% for Co, In, Ga,and As, respectively. Co appears to have diffused into the In0.53-

Ga0.47As substrate where a reaction might have occurred.When the anneal temperature is 350 �C (Fig. 1b), the reaction is

complete, and the thickness of CoInGaAs formed is �60 nm. TheCoInGaAs formed appears to have a more uniform thickness ascompared to the sample formed at 300 �C, though the CoInGaAs–In0.53Ga0.47As interface is rough. EDX analysis was taken at

localized spots (indicated in Fig. 1b) across the CoInGaAs film,and summarized in Fig. 2. We observed a region rich in Co and

64 Ivana et al. / Solid-State Electronics 78 (2012) 62–67

Ga (�36 at.% Co and �46 at.% Ga) at the top (Spot 1), followed by aregion rich in Co and As (�39 at.% Co and �50 at.% As) (Spot 2). Theabsence of a layer of pure Co indicates that the Co has been fullyconsumed in the reaction. For the sample annealed at 400 �C(Fig. 1c), the metallic film formed has an extremely rough interfacewith the In0.53Ga0.47As substrate.

X-ray Diffraction (XRD) detects the formation of Cobalt Gallium(CoGa) and Cobalt Arsenide (CoAs) binary phases in the CoInGaAsfilm, as shown in Fig. 3. It can be inferred that Cobalt Gallium phasemade up the Co- and Ga-rich layer (Spot 1 in Fig. 1b) below whichCobalt Arsenide phase constituted the Co- and As-rich region (Spot2 in Fig. 1b). This is similar to the reaction between Co and GaAs,where the formation of CoGa on CoAs occurs at 500 �C [36,37]. In

As-deposited 350 4001.0

1.1

1.2

1.3

Con

tact

Res

ista

nce

Rc (

kΩ⋅μ

m)

Anneal Temperature (°C)

(a) (

(c) (

Fig. 5. (a) Top-view optical microscope image of TLM structure with various contact spacresistivity. (b) I–V curves obtained from a TLM structure with CoInGaAs metal contacts foRc and (d) specific contact resistivity of Co and CoInGaAs formed on n+-In0.53Ga0.47As.

this work, the CoGa and CoAs binary phases were formed at a tem-perature as low as 350 �C.

The sheet resistance (Rsh) values of the annealed samples areplotted in Fig. 4. As-deposited Co has a Rsh value of 10.4 X/square (X/h), as indicated by the dashed line. Upon annealingat 200 �C, Rsh remains unchanged. Considering the earlier TEMobservation of partial or incomplete reaction at 300 �C, it is verylikely that little or no reaction took place at 200 or 250 �C. Theincrease in sheet resistance at 300 �C marks the onset of reac-tion. The sheet resistance decreases upon complete reaction at350 �C. The drop in sheet resistance upon the completion ofreaction is related to the �3 times increase in thickness of thelayer formed.

-1.0 -0.5 0.0 0.5 1.0

-40

-20

0

20

40TLM with

350 °C CoInGaAs metal pads

Cur

rent

(m

A)

Applied Voltage (V)

Contact spacing (μm):20, 50, 100, 150, 200, 250

6.0

6.2

6.4

6.6

6.8

7.0

Spec

ific

Con

tact

Res

isti

vity

(× 1

0−4

Ω⋅c

m2 )

As-deposited 350 400

Anneal Temperature (°C)

b)

d)

ing. This structure was used for extraction of contact resistance and specific contactrmed at 350 �C, showing ohmic behavior on n+-In0.53Ga0.47As. (c) Contact resistance

Fig. 6. Process flow for forming In0.53Ga0.47As n-MOSFET with self-aligned CoInGaAs metallic S/D. The schematics show the key process steps, including Co deposition,reaction with InGaAs, and selective Co removal.

100

101

102

A/c

m2 )

Ivana et al. / Solid-State Electronics 78 (2012) 62–67 65

2.2. Contact resistance extraction

The ohmic behavior and the contact resistance of CoInGaAs onn+-In0.53Ga0.47As were investigated using transfer length method(TLM) test structures. N-type In0.53Ga0.47As with doping concentra-tion ND of �5 � 1019 cm�3 was used as the starting substrate where�15 nm of SiO2 was deposited on the surface. Mesas were definedby wet etching of In0.53Ga0.47As. Contact holes were then patternedon the mesas to expose regions where metal pads would beformed. A short dip in buffered oxide etch was performed to re-move SiO2 right before Co deposition followed by lift-off process.Metal pads with various inter-pad spacing were formed on the n-type In0.53Ga0.47As mesas. A top-view optical microscope imageof the fabricated TLM test structure is depicted in Fig. 5a.

The current–voltage (I–V) characteristics were obtained fromtwo adjacent metal pads with various contact spacings. From theplot of total resistance as a function of contact spacing, the contactresistance and specific contact resistivity were extracted. Fig. 5bshows the I–V characteristics of a TLM structure with CoInGaAsmetal contacts formed at 350 �C. The ohmic behavior of the CoInG-

Fig. 7. Cross-sectional TEM images of In0.53Ga0.47As MOSFET with CoInGaAsmetallic S/D formed using 350 �C 60 s anneal. Annealing 10 nm of Co formed 28–35 nm of CoInGaAs. The inset shows a zoomed-in view of the TaN/Al2O3/In0.53Ga0.47As gate stack. The physical thickness of the Al2O3 gate dielectric is�6 nm.

aAs contact on n+-In0.53Ga0.47As is evident. Fig. 5c and d plot thecontact resistance and specific contact resistivity measured fromTLM structures before and after CoInGaAs formation. The lowestcontact resistance and specific contact resistivity of �1.12 kX lmand �6.25 � 10�4 O cm2 respectively, were obtained with 350 �Cannealing.

3. Device integration and characterization

The process flow for integrating CoInGaAs S/D in an implant-less In0.53Ga0.47As MOSFETs is shown in Fig. 6 (top left). Schematics

-0.5 0.0 0.510-4

10-3

10-2

10-1

Cur

rent

Den

sity

J (

Applied Voltage (V)

Fig. 8. CoInGaAs/p-In0.53Ga0.47As junction shows rectifying behavior. Voltage isapplied to the CoInGaAs, with the InP substrate grounded.

0 1 210-4

10-3

10-2

10-1

10 0

10 1

10 2

LG

=2 μm

VDS

=1.2 V

Gm

(μS/

μm)

Dra

in C

urre

nt I D

S(μ

A/μ

m)

Gate Voltage VGS (V)

VDS

=0.1V

0

5

10

15

20

25

30

35

0.0 0.5 1.0 1.5 2.00

10

20

30

40

50

60

Dra

in C

urre

nt I

DS

(μA

/μm

)

Drain Voltage VDS (V)

VGS

-VT = 0 to 2.5 V

in steps of 0.5 V

LG

= 2 μm

(a) (b)

Fig. 9. (a) IDS–VGS curves of a In0.53Ga0.47As n-MsOSFET with self-aligned CoInGaAs S/D. Gm is referred to the right axis. (b) IDS–VDS plot for the same In0.53Ga0.47As n-MOSFET.Gate overdrive VGS–VT is varied from 0 to 2.5 V in steps of 0.5 V.

66 Ivana et al. / Solid-State Electronics 78 (2012) 62–67

of the device cross sections were used to illustrate the key processsteps. The starting substrates comprise p-type In0.53Ga0.47As grownon 2-in. p-type bulk InP wafers. Pre-gate cleaning was performedto remove native oxide on the surface of In0.53Ga0.47As using HCl,NH4OH, and (NH4)2S in sequence. It was then immediately trans-ferred into an atomic layer deposition (ALD) chamber for deposi-tion of �6 nm Al2O3. Post-deposition annealing (PDA) was thenperformed at 400 �C for 60 s. Next, 100 nm of tantalum nitride(TaN) gate electrode was deposited by sputtering. The gate stackwas formed by optical lithography followed by chlorine-basedplasma etching.

A 60 s dip in dilute hydrofluoric acid (HF) solution was per-formed to remove the remaining Al2O3 right before a blanket depo-sition 10 nm of Co all over the patterned wafer. Rapid thermalanneal was performed at 350 �C for 60 s to form CoInGaAs in thesource and drain. A cross-sectional TEM image of the fabricatedIn0.53Ga0.47As n-MOSFET with CoInGaAs metallic S/D is shown inFig. 7. The CoInGaAs is self-aligned to the gate stack. The physicalthickness of the Al2O3 gate dielectric is �6 nm, as shown in theinset of Fig. 7. A continuous CoInGaAs film was formed in the S/Dregions and the thickness is in the range of 28–35 nm. Nounreacted Co remains at the surface of the S/D regions afterannealing. The unreacted Co at the sidewalls of the gate wasremoved using dilute nitric acid (HNO3). Device characterizationwas then performed.

To test the Schottky behavior of CoInGaAs on p-type In0.53-

Ga0.47As, voltage is applied to the CoInGaAs metallic source layerwhile the gold back contact for InP was grounded. The CoInGaAs/p-In0.53Ga0.47As structure demonstrates rectifying behavior, asshown in Fig. 8. This suggests that CoInGaAs can be used as asuitable S/D material. The reverse current at the positive voltageregime contributes to the off-state leakage current of the transis-tor. An increase in reverse current is observed with increasing ap-plied voltage. This could be due to tunneling across the junctionand could be assisted by the presence of traps at the CoInGaAs/In0.53Ga0.47As junction. The reverse current could be suppressedby optimizing the formation process such that the interface be-tween CoInGaAs and InGaAs is smoother, or by having an n-dopedregion [38] or wider band gap material beneath the CoInGaAs film.

Fig. 9a shows the IDS–VGS transfer characteristics of a transistorwith gate length of 2 lm and gate width of 100 lm. Drain voltageVDS of 0.1 and 1.2 V were applied. A threshold voltage (VT) of 0.57 V

was obtained using linear extrapolation of the IDS–VGS curve (atVDS = 0.1 V) at the maximum transconductance Gm. A peak Gm valueof 22.4 lS/lm at VDS = 1.2 V was obtained. The high off-statecurrent at VDS = 1.2 V is due to the reverse leakage of the metal/semiconductor junction as described earlier. Fig. 9b plots theIDS–VDS characteristics of the transistor at various gate overdrives(VGS–VT) ranging from 0 to 2.5 V in steps of 0.5 V. The low outputcharacteristics may be caused by a rather high S/D series resistanceobtained in this work. The high S/D series resistance is possiblycaused by the high contact resistance which will need to beoptimized in the future.

4. Conclusion

An implant-less In0.53Ga0.47As n-MOSFET with self-alignedCoInGaAs metallic S/D was demonstrated for the first time. Co re-acts with In0.53Ga0.47As at temperatures as low as 350 �C to form ametallic CoInGaAs material. CoInGaAs forms an ohmic contact onn-InGaAs. The CoInGaAs film formed at 350 �C has a sheet resis-tance of 14 X/h. Contact resistance and specific contact resistivityof �1.12 kX lm and 6.25 � 10�4 O cm2, respectively, wereobtained from TLM structures with n-well doping concentrationof �5 � 1019 cm�3. CoInGaAs forms rectifying contact on p-In0.53-

Ga0.47As. In0.53Ga0.47As n-MOSFET with CoInGaAs S/D showsreasonably well-behaved output characteristics. The off-state leak-age is dominated by the reverse leakage current of the CoInGaAs/p-In0.53Ga0.47As contact.

Acknowledgment

This work is supported by research grants from NationalResearch Foundation (NRF), Singapore, under Award Nos. NRF-RF2008-09 and NRF-CRP6-2010-04.

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