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n well. P substrate. wafer. CMOS Mask Layers. Why we need design rules. Masks are tooling for manufacturing. Manufacturing processes have inherent limitations in accuracy. Design rules specify geometry of masks which will provide reasonable yields. - PowerPoint PPT Presentation
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P substrate
CMOS Mask Layers
wafer
n well
5
Why we need design rules
• Masks are tooling for manufacturing.• Manufacturing processes have inherent
limitations in accuracy.• Design rules specify geometry of masks which
will provide reasonable yields.• Design rules are determined by experience.
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Manufacturing problems
• Photoresist shrinkage, tearing.• Variations in material deposition.• Variations in temperature.• Variations in oxide thickness.• Impurities.• Variations between lots.• Variations across a wafer.
1. Mask misalignment
2. Dust
3. Process parameters (e.g., lateral diffusion)
4. Rough surfaces
0.3
0.14
both materialsmask misaligned
Contact: 0.44 x 0.44
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Transistor problems
• Varaiations in threshold voltage:– oxide thickness;– ion implanatation;– poly variations.
• Changes in source/drain diffusion overlap.• Variations in substrate.
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Wiring problems
• Diffusion: changes in doping -> variations in resistance, capacitance.
• Poly, metal: variations in height, width -> variations in resistance, capacitance.
• Shorts and opens:
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Oxide problems
• Variations in height.• Lack of planarity -> step coverage.
metal 1metal 2
metal 2
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Via problems
• Via may not be cut all the way through.• Undesize via has too much resistance.• Via may be too large and create short.
Rule for various layers – of IC fabrication(0.3 µ)1.Well2.Active3.Poly4.Select5.Poly Contact6.Active Contact7.Metal-18.Via9.Metal-210.Via211.Metal-3
Rules for Well – 0.3 µMinimum width 3.5 µ
Minimum spacing between5.4 µwells at different potential
Minimum spacing between1.8 µwells at same potential
Active Layers
Description Microns
Minimum width 0.9u
Minimum spacing 0.9u
Source/drain active to well edge 1.8u
Substrate/well contact active to well edge 0.9u
Minimum spacing betweenactive of different implant 0 or 1.2u
Poly Layer
Description Microns
Minimum width 0.6u
Minimum spacing 0.9u
Minimum gate extension of active 0.6u
Minimum active extension of poly 0.9u
Minimum field poly to active 0.3u
Select
Description Microns
Minimum select spacing tochannel of transistor 0.9u
Minimum select overlap of active 0.6u
Minimum select overlap of contact 0.3u
Minimum select width and spacing 0.6u
Poly Contact
Description Microns
Exact contact size 0.6u x 0.6u
Minimum poly overlap 0.3u
Minumum contact spacing 0.9u
Minimum spacing togate of transistor 0.6u
Minimum spacing to other poly 1.5u
Minimum spacing to active(single contact) 0.6u
Minimum spacing to active(multiple contacts) 0.9u
Active contact
Description Microns
Exact contact size 0.6u x 0.6u
Minimum active overlap 0.3u
Minimum contact spacing 0.9u
Minimum spacing to gate of transistor 0.6u
Minimum spacing to diffusion active 1.5u
Minimum spacing to field poly(single contact) 0.6u
Minimum spacing to field poly(multiple contacts) 0.9u
Minimum spacing to poly contact 1.2u
Metal 1 Layer
Description Microns
Minimum width 0.9u
Minimum spacing 0.9u
Minimum overlap of any contact 0.3u
Via 1 LAyer
Description Microns
Exact size 0.6u x 0.6u
Minimum spacing 0.9u
Minimum overlap by Metal-1 0.3u
Minimum spacing to contact 0.6u
Metal 2 Layer
Description Microns
Minimum width 0.9u
Minimum spacing 0.9u
Minimum overlap of via1 0.3u
Via 2
Description Microns
Exact size 0.6u x 0.6u
Minimum spacing 0.9u
Minimum overlap by Metal-2 0.3u
Minimum spacing Via-1 0.6u
Metal 3 layer
Description Microns
Minimum width 1.5u
Minimum spacing 0.9u
Minimum overlap of Via-2 0.6u
http://www.youtube.com/watch?v=ceRXbojj7aQ
http://www.mosis.org/New/Technical/Designrules/dr-scmos72.html
