Fabrication Process

Wafer preparation

Metallurgical grade silicon-electronic grade silicon(99.99% pure)Single crystalline structure obtained by melting and then cooling ---

Czochralski method Ingot cut into wafers using diamond sawWafers are than polished to mirror finish

Silicon Wafer creation

CMOS Inverter

0: Introduction 8

Inverter Cross-section

Typically use p-type substrate for nMOS transistorsRequires n-well for body of pMOS transistors

n+

p substrate

p+

n well

A

YGND VDD

n+ p+

SiO2

n+ diffusion

p+ diffusion

polysilicon

metal1

nMOS transistor pMOS transistor

0: Introduction 9

Well and Substrate Taps

Substrate must be tied to GND and n-well to VDD

Use heavily doped well and substrate contacts / taps

n+

p substrate

p+

n well

A

YGND VDD

n+p+

substrate tap well tap

n+ p+

0: Introduction 10

Inverter Top View

GND VDD

Y

A

substrate tap well tapnMOS transistor pMOS transistor

0: Introduction 11

Detailed Mask Views

Six masksn-wellPolysiliconn+ diffusionp+ diffusionContactMetal

Metal

Polysilicon

Contact

n+ Diffusion

p+ Diffusion

n well

Fabrication Process

Blank Wafer

Oxidation

Photolithography

N-well formation

Polysilicon gate formation

n+ diffusion

pp+ diffusion

metalization

0: Introduction 13

Fabrication Steps

Start with blank wafer (typically p-type where NMOS is created)

p substrate

Oxidation

Grow Sio2 on top of Si wafer

Wet oxidation– (900°-1000°c), 2:1 mixture of H2and O2 (pyrogenic oxidation)

Dry oxidation-(1200°c) O2

p substrate

SiO2

PhotoresistPhoto resist

Photoresist is a light-sensitive organic polymerProperty changes when exposed to light

Two types of photo resists (positive or negative)Positive resists can be removed if exposed to UV lightNegative resists cannot be removed if exposed to UV light

p substrate

SiO2

Photoresist

LithographyExpose photoresist to Ultra-violate (UV) light through the n-well

maskStrip off exposed photo resist with chemicals

p substrate

SiO2

Photoresist

n-well mask

Etch

Etch oxide with hydrofluoric acid (HF)Only attacks oxide where resist has been exposedN-well pattern is transferred from the mask to Sio2 surface; creates

an opening to the silicon surface

p substrate

SiO2

Photoresist

Strip Photoresist

Strip off remaining photoresistUse mixture of acids called piranah etch

Necessary so resist doesn’t melt in next step

p substrate

SiO2

N-wellN-well is formed with diffusion or ion implantationDiffusion

Place wafer in furnace with arsenic-rich gasHeat until As atoms diffuse into exposed Si

Ion ImplanatationBlast wafer with beam of As ions Ions blocked by SiO2, only enter exposed Si

SiO2 shields (or masks) areas which remain p-type

n well

SiO2

Strip Oxide

Strip off the remaining oxide using HFSubsequent steps involve similar series of steps

p substraten well

Polysilicon

Deposit very thin layer of gate oxide< 20 Å (6-7 atomic layers)

Chemical Vapor Deposition (CVD) of silicon layerPlace wafer in furnace with Silane gas (SiH4)Forms many small crystals called polysiliconHeavily doped to be good conductor

Thin gate oxidePolysilicon

p substraten well

0: Introduction 22

Polysilicon Patterning

Use same lithography process to pattern polysilicon

Polysilicon

p substrate

Thin gate oxidePolysilicon

n well

Self-Aligned Process

Use gate-oxide/poly silicon and masking to expose where n+ dopants should be diffused or implanted

p substraten well

0: Introduction 24

N-diffusion/implantation

Pattern oxide and form n+ regionsN-diffusion forms nMOS source, drain, and n-well contactPolysilicon is better than metal for self-aligned gates because it doesn’t

melt during later processing

p substraten well

n+ Diffusion

0: Introduction 25

N-diffusion cont.Historically dopants were diffusedUsually high energy ion-implantation used todayBut n+ regions are still called diffusion

n wellp substrate

n+n+ n+

0: Introduction 26

N-diffusion cont.

Strip off oxide to complete patterning stepSource and drain are separated by channel under the gate self

aligned process

n wellp substrate

n+n+ n+

0: Introduction 27

P-Diffusion

Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate contact

p+ Diffusion

p substraten well

n+n+ n+p+p+p+

0: Introduction 28

ContactsNow we need to wire together the devicesCover chip with thick field oxide (FO)Etch oxide where contact cuts are needed

p substrate

Thick field oxide

n well

n+n+ n+p+p+p+

Contact

Contacts

0: Introduction 30

Metalization

Sputter on aluminum over whole waferGold is used in newer technologyPattern to remove excess metal, leaving wires

p substrate

Metal

Thick field oxide

n well

n+n+ n+p+p+p+

Metal

Metalization cross section

Over glass and pad openings(Passivation)

A protective glass layer is added over the surfaceThe protective layer consists of:

A layer of SiO2

Followed by a layer of silicon nitrideThe SiN layer acts as a diffusion barrier against contaminants

(passivation)OpeningConnection to I/O pads, test probesBumping

p substrate

p substrate

SiO2

p substrate

SiO2

Photoresist

p substrate

SiO2

Photoresist

N-well Fabrication overview

p substrate

SiO2

Photoresist

p substrate

SiO2

n well

SiO2

p substraten well

Thin gate oxidePolysilicon

p substraten well

p substrate

Thin gate oxidePolysilicon

n well

p substraten well

p substraten well

n wellp substrate

n+n+ n+

n wellp substrate

n+n+ n+

p substraten well

n+n+ n+p+p+p+

p substrate

Thick field oxide

n well

n+n+ n+p+p+p+

p substrate

Metal

Thick field oxide

n well

n+n+ n+p+p+p+

CMOS fabrication process overview 8-37

Twin-Tub (Twin-Well) CMOS Process

Fabrication ProcessCrystal growth

Wafers

Pattering:-Repeated steps of Lithography Diffusion and Etching

Testing

Packaging

Dicer:- Cut the Patterned wafers into dice

LithographyThe lithographic sequence is repeated for each physical layer used to

construct the IC. The sequence is always the same:Photo-resist applicationPrinting (exposure)DevelopmentEtching

PhotomaskreticleSteppermoves reticle

Types of printing:Projection printingContact printingProximity printing

Light sourceMercury lamp – 436nm or 365 nmLasers-248nm (deep UV)Argon fluoride laser-193nm

Silicon oxidationWet oxidation– (900°-1000°c), 2:1 mixture of H2and O2 (pyrogenic

oxidation)Dry oxidation-(1200°c) O2 Atomic Layer deposition- process in which a thin chemical layer

(material A) is attached to a surface and then a chemical (material B) is introduced to produce a thin layer of the required layer (i.e., Si02).

The process is then repeated and the required layer is built up layer by layer.

Contacts and Metalization

Contact- cut mask

Metal mask

Metal 2

Another layer of LTO CVD oxide is addedVia openings are createdMetal 2 is deposited and patterned

n-well

p-type

n+ p+

Via metal 1metal 2

Circuit Under DesignVDD VDD

Vin Vout

M1

M2

M3

M4

Vout2

Circuit Layout

gnd

vdd

Start Material

Starting wafer: n-type withdoping level = 1013/cm3

* Cross-sections will be shown along vertical line A-A’

A

A’

N-well Construction

(1) Oxidize wafer(2) Deposit silicon nitride(3) Deposit photoresist

N-well Construction

(4) Expose resist using n-wellmask

N-well Construction

(5) Develop resist(6) Etch nitride and(7) Grow thick oxide

N-well Construction

(8) Implant n-dopants (phosphorus)(up to 1.5 m deep)

P-well Construction

Repeat previous steps

Grow Gate Oxide

0.055 m thin

Grow Thick Field Oxide

Uses Active Area mask

Is followed by threshold-adjusting implants

0.9 m thick

Polysilicon layer

Source-Drain Implants

n+ source-drain implant(using n+ select mask)

Source-Drain Implants

p+ source-drain implant(using p+ select mask)

Contact-Hole Definition

(1) Deposit inter-level dielectric (SiO2) — 0.75 m

(2) Define contact opening using contact mask

Aluminum-1 Layer

Aluminum evaporated (0.8 m thick)

followed by other metal layers and glass

Advanced Metalization