Clock Talk LIVE Schedule – Presentation will begin shortly...O-Cloud Compliant Software (SW) Functions Refers to infrastructure element(s) based on standard servers, using accelerators,

Clock Talk LIVE Schedule – Presentation will begin shortly

Tuesday, Sept 15th IEEE 1588 Timing Solutions for Non-Telecom Applications

Tuesday, Sept 29th Clock Jitter Demystified and Jitter Requirements for 56/112 SerDes

Tuesday, Oct 13th Design Considerations When Selecting a XO/VCXO Clock Reference for 56G/112G SerDes

Tuesday, Oct 27th Stop Guessing, Use Silicon Labs Timing Tools to Build Your Clock Tree

Tuesday, Nov 10th Optimize Timing Solutions for High-Speed FPGA and Application Processor Designs

Tuesday, Nov 17th PCIe Gen 4/5/6 Specifications and Jitter Measurement Explained

Tuesday, Dec 1st Timing Solutions for 5G O-RAN Systems

Tuesday, Jan 12th AEC-Q100 Timing Products for Automotive Applications

Tuesday, Jan 26th Timing Solutions for Open-Compute Systems

1

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WELCOME SILICON LABS LIVE

Internet Infrastructure andIndustrial Automation Tech Talks

2

WELCOME

Timing Solutions for 5G O-RAN SystemsMark Schrepferman | Senior Product ManagerDavid Spencer | Senior Product Manager

O-RAN Overview

AccuTimeTM IEEE 1588 Servo and Stack Software

Implementing O-RAN Solutions

Agenda

4

Network Evolution Trends and O-RAN

5

LTE evolves to 5G Non-Standalone (NSA) to Standalone (SA)

RAN and transport network functions disaggregate and virtualize

O-RAN Alliance “Mission is to re-shape the RAN industry towards more intelligent, open, virtualized and fully interoperable mobile networks.” Accomplished through open standards and specifications for hardware, software, testing and integration.

Backhaul

Backhaul FronthaulCPRI

Backhaul FronthauleCPRIMidhaul

4G RAN

4G RAN

5G RAN

5GC

EPC

RRH

eNodeBBBU + RRH

BBU

RUCU DU

3GPP functionalSplits

NSA

SA

EPC

EPC = Evolved Packet Core5GC = 5G CoreNSA = Non-StandaloneSA = Standalone

Timing in the Network

6

Image Xilinx

NSA

SA

• O-RAN 5G scenarios specifies functional splits or how the fronthaul interface partitions the stack layers between the DU and RU

• RU trade offs are lower size, weight and power Vs. more complex link and higher bandwidth • O-RAN selected split 7-2 as the standard to balance the tradeoffs, but allows variation

LTE uses CPRI for radio connection Ethernet synchronization requirement only 1.5 µs


7

Image Xilinx

Front haul is CPRI with dedicated syncEasy to meet tight timing requirements

5G networks are moving towards Ethernet-based front haul and advanced features Drives tighter synchronization requirements – down to 65 ns


8

Image XilinxApplication Node

Alignment Location

LTE-TDD / 5G3 µs

(± 1.5 µsto UTC)

BH/MH

Carrier Aggregation(non-contiguous)

260 ns FH

Carrier Aggregation(contiguous)

130 ns FH

Distributed MIMO & TX Diversity 65 ns FH

Front haul is eCPRI over EthernetMuch harder to meet timing requirements

O-RAN 5G Network Requirements

9

3GPP defined error ± 1500 ns phase error ± 50 ppb frequency error

G.8271.1 defines network budget limits for a full timing support network

3GPP: ≤ 260 ns

802.1 CM:≤ 100 ns (Cat B)

RU

T-BC

PRTC/T-GM

T-TSCT-BC

T-TSCT-BC

DU

T-BC

CU

PRTC/T-GM

Local

Remote Sync

Midhaul Fronthaul

Local Sync

Air Interface

O-RAN Configuration LLS-C2802.1 CM Case 1.1 Category B

Local Synchronization

S M

S M

S

S MS

S

M

M

± 1500 ns (ITU G.8271 Accuracy Level 4)

± 1325 ns (O-RAN WG4 Table 9-3)

S

± 100 ns

M

Notes (from O-RAN WG4 table 9-3):1: with T-TSC Class B in RU2: with enhanced T-TSC in RU

|TE| ≤ 95 ns1

|TE| ≤ 140 ns2

TE ≤ ± 130 ns (Cat B)

3GPP: ± 50 ppb

PRTC: Primary Reference Time Clock (ITU-T G.8272, G.8272.1)T-GM: Telecom Grand Master (ITU-T G.8273.1)T-BC: Telecom Boundary Clock (ITU-T G.8273.2)T-TSC: Telecom Slave Clock (ITU-T G.8273.2)CU: Control Unit (O-RAN)DU: Distributed Unit (O-RAN)RU: Radio Unit (O-RAN)|TE|: Absolute Time Error (eCPRI spec)TE: Time Error (eCPRI spec)

Interfaces O1, A1, E2, E1, F1

Communication planes Management Plane (MP, non-real time) Control Plane (CP, real time) User Plane (UP, RF modulation data) Synchronization Plane (SP)

O-RAN Interfaces and Communication Planes

10

Image: O-RAN Alliance

C & U-Plane protocol structure S-Plane protocol structure

ORAN-WG4.CUS.0-v02.00

https://docs.o-ran-sc.org/en/latest/architecture/architecture.html

Goal Offer flexible deployment options and provisioning

models of virtualized network elements into the cloud.

O-Cloud Compliant Software (SW) Functions Refers to infrastructure element(s) based on

standard servers, using accelerators, that use software that is decoupled from the hardware.

O-RAN Compliant Hardware (HW) Decoupled from the software. Uses standard interfaces. Reduces overall costs for deployment and

maintenance. Improves interoperability.

O-RAN Deployment Scenarios

11


O-RAN Compliant HW

O-RAN Compliant HW

O-RAN Compliant HW

O-RAN Compliant HW

O-RAN Compliant HW

O-RAN Compliant HW

https://static1.squarespace.com/static/5ad774cce74940d7115044b0/t/5e95a0a306c6ab2d1cbca4d3/1586864301196/O-RAN+Use+Cases+and+Deployment+Scenarios+Whitepaper+February+2020.pdf

Goal of O-RAN is to future proof the network through cloudification and BBU resource pooling

O-Cloud refers to infrastructure element(s) based on standard servers, using accelerators, that use software that is decoupled from the hardware.

O-RAN Compliant Hardware (HW) Decoupled from the software Uses standard interfaces Reduces overall costs for deployment and

maintenance Improve interoperability


12


O-RAN Compliant HW

O-RAN Compliant HW

O-RAN Compliant HW

O-RAN Compliant HW

O-RAN Compliant HW

O-RAN Compliant HW


Goal of O-RAN is to future proof the network through cloudification and BBU resource pooling

O-Cloud refers to infrastructure element(s) based on standard servers, using accelerators, that use software that is decoupled from the hardware.

O-RAN Compliant Hardware (HW) Decoupled from the software Uses standard interfaces Reduces overall costs for deployment and

maintenance Improve interoperability


13


O-RAN Compliant HW

O-RAN Compliant HW

O-RAN Compliant HW

O-RAN Compliant HW

O-RAN Compliant HW

O-RAN Compliant HW


O-RAN Fronthaul Synchronization Configurations Overview

14

Four configurations: C1: DU-RU point-point, no FH switches C2: DU-RU through FH switches C3: PRTC closer to the edge C4: Local PRTC

Synchronization can be local as shown in C1, C2, C4, or from the network (remote) from the CU

Fronthaul network Is mostly G.8275.1 (Full Timing Support) Can support G.8275.2 (Partial Timing

Support) with PTP-unaware switches with high-performance servo in the RU

LLS – C1

DU RU

T-TSC

CU Midhaul

T-BC

Direct Ethernet Link

LLS – C3

DU RU

T-TSCT-BCs

CU Midhaul

T-BC

T-GMFronthaul

LLS – C4

DU RUFronthaul

T-TSCT-BC

CU Midhaul

T-BC

LLS – C2

DU RUFronthaul

T-TSC

T-BC

CU Midhaul

T-BC

PRTC/T-GM

PRTC/T-GM

Local Sync

Remote Sync

PRTC/T-GM

PRTC/T-GM Remote

Sync

Local Sync

RU

T-TSC

RU

T-TSC

PRTC/T-GM Remote

Sync

PRTC: Primary Reference Time Clock (ITU-T G.8272, G.8272.1)T-GM: Telecom Grand Master (ITU-T G.8273.1)T-BC: Telecom Boundary Clock (ITU-T G.8273.2)T-TSC: Telecom Slave Clock (ITU-T G.8273.2)CU: Control Unit (O-RAN)DU: Distributed Unit (O-RAN)RU: Radio Unit (O-RAN)LLS: Lower Layer Split (O-RAN)

O-RAN S-Plane LLS-C2 Synchronization Implementation

15

T-BC

FronthaulSwitch

PTP/SyncE

≥ 1 switches in fabric topology

S M

Distribution Unit – DU, T-BC Radio Unit – RU, T-TSC

Synchronization Flow

SyncE_rxDSPLLA + RF PLL

DSPLLB

OCXO/TCXO

MS

Sync

E_rx

General Purpose Clocks

(SyncE or PTP steered)

SYSCLK/1PPS (PTP Steered and

Stabilized by SyncE)

SyncE Clock-tx(SyncE steered)

Midhaul

PTP FCW(DCO)

IEEE 1588/PTP PLL

PHY

Sync

E_tx

Midhaul

RadioSysc

lk

1PPS

ToDARM CPU

PTP Servo + Stack Software

SyncE PLL

RFClocks


DSPLLB

OCXO/TCXO

IEEE 1588/PTP PLL

T-GM

PRTC

PHY S

Sync

E_rx

PTP FCW(DCO)

Sysc

lk

1PPS

ToDARM CPU


PHY

Ref ClockSyncE

PTPGNSS


(PTP steered and Stabilized by SyncE )



RF Clocks (PTP steered and


(Remote)


16

DSPLLA + RF PLL

OCXO/TCXO

M


ToD CLK

Distribution Unit – DU, T-BC

Midhaul

Radio Unit – RU, T-TSC

PLL

PHYMidhaul

RadioToD

Clk

ToDARM CPU


OCXO/TCXO

IEEE 1588/PTP PLL


PHY S

Sync

E_rx

PTP FCW(DCO)

Sysc

lk

1PPS

ToDARM CPU


PHY

Ref ClockSyncE

PTPGNSS

1PPS

1PPS

GNSS(Local)GNSS(Local)

ToD







RFClocks

T-BC

FronthaulSwitch

PTP/SyncE


S M


17


DSPLLB

OCXO/TCXO

MS

Sync

E_rx


(SyncE or PTP controlled)



SyncE Clock-tx(SyncE Controlled)

Distribution Unit – DU, T-BC

Midhaul

PTP FCW(DCO)

Radio Unit – RU, T-TSC

IEEE 1588/PTP PLL

PHY

Sync

E_tx

Midhaul

RadioSysc

lk

1PPS

ToDARM CPU


SyncE PLL

RFClocks

DSPLLA + RF PLL

OCXO/TCXO

IEEE 1588/PTP PLL


T-GM

PRTC

PHY S

PTP FCW(DCO)

Sysc

lk

1PPS

ToDARM CPU


PHY

Ref ClockSyncE

PTPGNSS

SyncE_rx

Sync

E_rx







(Remote)


18

T-BC

FronthaulSwitch


M M


T-GM

PRTC



DSPLLB

OCXO/TCXO

SSy

ncE_

rx






PTP FCW(DCO)

IEEE 1588/PTP PLL

PHY

Sync

E_tx

Midhaul

RadioSysc

lk

1PPS

ToDARM CPU


SyncE PLL

RFClocks

DSPLLA + RF PLL

OCXO/TCXO

IEEE 1588/PTP PLL

PHY





S

Sync

E_rx

PTP FCW(DCO)

Sysc

lk

1PPS

ToDARM CPU


PHY

Ref ClockSyncE

PTPGNSS

M

SyncE_rx




19



1PPS

Synchronization Flow Synchronization Flow

ToD

1PPS

GNSS(Local)GNSS(Local)Any

AllowedConfig

FronthaulSwitch


DSPLLB

OCXO/TCXO

S

Sync

E_rx



SYSCLK/1PPS (PTP Steered

and Stabilized by SyncE)


Midhaul

PTP FCW(DCO)

IEEE 1588/PTP PLL

PHYSy

ncE_

txMidhaul

RadioSysc

lk

1PPS

ToDARM CPU


SyncE PLL

RFClocks

DSPLLA + RF PLL

OCXO/TCXO

PLL

PHY

ToD CLK

ToD

CLK

ToDARM CPUPHY

Ref ClockSyncE

PTPGNSS

RF Clocks

T-GM

PRTC

(Remote)

No PTP or SyncE thru FH network

O-RAN Overview



Agenda

20

Boundary Clock Performance for O-RAN

21

M S

Sync

Sync Sync Sync

Delay Request Delay Request Delay Request Delay Request

Network Limit

EquipmentLimitGNSS

Parameter Measurement Class A Class B Class C Class D

Max |TE| Unfiltered 100 ns 70 ns 30 ns -

Max |TEL| Low pass - - - 5 ns

cTE Averaged 50 ns 20 ns 10 ns -

dTEL (MTIE) Low pass 40 ns 40 ns 10 ns -

dTEL (TDEV) Low pass 4 ns 4 ns 2 ns -

dTEH High pass 70 ns 70 ns - -

Full-featured IEEE 1588 solution for Silicon Labs Network Synchronizers PTP Stack Time/frequency-recovery servo

Support for integrated (pizza box) and timing card / line card distributed systems

Core + driver model simplifies porting to target hardware

Ability to use AccuTime servo with existing stack implementation

1+1 redundant timing card support

Reference designs for common target platforms

AccuTime IEEE 1588 Servo and Stack Software Introduction

22

AccuTime Features

23

Feature Details

IEEE 1588 Profile Support GenericITU-T G.8265.1 (PTP unaware frequency network)ITU-T G.8275.1 (Full timing support)ITU-T G.8275.2 (Partial timing support)

PTP Node Types SlaveBoundary ClockGrandmaster

PTP Messaging Protocol EthernetUDP/IPv4UDP/IPv6

T-BC/T-TSC Operating Modes G.8273.2 – Classes A, B, C & DG.8273.4 PTS – PTP-only & PTP+SyncEG.8273.4 APTS

Supported Network Types Generic – PTP unaware high-PDV networkEngineered – managed PTP unaware network with lower-PDVG.8275.1 – No PDV point-to-point network

Servo Operating Modes Time recoveryFrequency Only

PTP Network Types UnawareBoundary clockEnd-to-end transparent clock

Measures effect of network traffic on IEEE 1588 performance

Ten PTP-unaware switches

AccuTime – Why a Good Servo is Important

24

Forward and reverse “disturbance traffic”

Flows “across” IEEE 1588 packets

Network load changes over time

Disturbance traffic induces Packet Delay Variation (PDV)

Which the servo must filter out to recover time

G.8261 Test Case 13Traffic Model 2

G.8261 Test Case 13 – Traffic Model 2

M S

IEEE 1588 Timing Flow

“Disturbance Traffic” Flow

G.8261: Performance Comparison

25

Linux ptp4l *

G.8261 Test Case 13Traffic Model 2

MTIE(Time Error)

TDEV(Noise) * open-source

software provided by some PLL

vendors as a PTP solution

Servo Performance is Critical for Partial Timing Support Networks

Timing Characteristic Measurement Recommendation Section Compliance Result Comments

Noise Generation – PTP

Absolute Time Error

Constant Time Error

Dynamic Time Error

Filtered Time Error

G.8273.2 – 7.1

G.8273.2 – 7.1

G.8273.2 – 7.1

G.8273.2 – 7.1

Passed

Passed

Passed

Passed

Absolute, Constant and Dynamic time error specs apply to Classes A, B & C. Filtered time error spec applies to Class D

Noise Generation – 1PPS

Absolute Time Error

Constant Time Error

Dynamic Time Error

Filtered Time Error

G.8273.2 – 7.1

G.8273.2 – 7.1

G.8273.2 – 7.1

G.8273.2 – 7.1

Passed

Passed

Passed

Passed

Noise Tolerance N/A G.8273.2 – 7.2 Passed

Noise Transfer – PTP PTP – PTP

PTP – 1PPS

G.8273.2 – 7.3

G.8273.2 – 7.3

Passed

Passed

Noise Transfer – SyncESyncE – PTP

SyncE – 1PPS

G.8273.2 – 7.3

G.8273.2 – 7.3

Passed

Passed

Transient ResponseSyncE – PTP

SyncE – 1PPS

G.8273.2 – 7.4.1.2

G.8273.2 – 7.4.1.2

Passed

Passed

Holdover Loss of PTP input G.8273.2 – 7.2.1 Passed

G.8273.2 Performance Summary

26

Si5518/54xx + AccuTime meets

G.8273.2 Class C & D performance

O-RAN Overview



Agenda

27

Si5389 Network Synchronizer Provides all IEEE 1588 and PHY clocks

Supports MPSoC ZCU102 and RFSoC ZCU111 (Gen1)

AccuTimeTM IEEE 1588 Software Stack software runs on host processor

Servo software internal to Si5389

Meets G.8273.2 Class C requirements of +/-10nS

Si5386 Wireless Clock (ZCU111 - only)

Provides eCPRI clocks for RF ADCs and DACs

Supports up to 5 independent clock domains

Implementing a O-RAN Solution – IEEE 1588 Reference Design

28

Silabs IEEE 1588/SyncE Reference Design on Xilinx Zynq Ultrascale+

29

Xilinx Zynq UltraScale+ ZCU102/111/216 Evaluation Kit

Silicon Labs Solution• Si5389 / Si5518 FMC• 4x 10Gbe optical transceivers• SD Memory card w SW + 1588 Stack SW• Fiber and SMA Cables

Turnkey solution simplifies evaluation with easy-to-follow instructions

Configurable solution for all Xilinx Zynq Ultrascale+ MPSoC & RFSoC devices Silicon Labs 1588 servo algorithm supports statistical packet selection

Dynamically adjusts to changing network load conditions to mitigate PDV effects needed to pass ITU-T G.8261 test case and remain standards compliant.

1588 Class C compliant solution (cTE < +/-10ns) Targeting Pizza Box Designs Telecom Boundary Clock (T-BC) or Telecom Time Slave Clock (T-TSC)

Si5518 FMC ZCU111

ZCU216

Si5518 FMC

Si5389 FMC

ZCU102

Si5389 FMC

ZCU216

Silicon Labs AccuTime Design Flow

30

Eval

uatio

nDe

sign

Si54xx/Si55xx PLL device Evaluate physical-layer

performance (output jitter etc.) using Silicon Labs EVB controlled by CBPro

Create desired configuration with CBPRo

Generate application-specific or customer-specific part number for ordering

Evaluate 1588 functionality with Silicon Labs reference design and Xilinx EVB

Sign software license agreement

Implement design with Silicon Labs code and vendor IP for Xilinx designs

Or Create design-specific

drivers and port SiliconLabs software for other architectures

Summary

31

The adoption of O-RAN for 5G introduces synchronization challenges … Very stringent DU-to-radio timing requirements Partial timing support back and mid haul networks Full timing support front haul network PTP profile interworking High-performance radio clock requirements

… And Silicon Labs is ready Si54xx Network Synchronizers for DU, Si55xx wireless clocks for RU High-performance wireless and wireline clocking AccuTime full-featured 1588 solution O-RAN compliant Full and partial timing support Industry leading time recovery servo – essential for back/midhaul support

3GPP: ≤ 260 ns

802.1 CM:≤ 100 ns (Cat B)

RU

T-BC

PRTC/T-GM

T-TSCT-BC

T-TSCT-BC

DU

T-BC

CU

PRTC/T-GM

Local

Remote Sync

Midhaul Fronthaul

Local Sync

Air Interface

O-RAN Configuration LLS-C2802.1 CM Case 1.1 Category B

Local Synchronization

S M

S M

S

S MS

S

M

M

± 1500 ns (ITU G.8271 Accuracy Level 4)

± 1325 ns (O-RAN Table 9-3)

S

±100 ns

M

Notes (from O-RAN table 9-3):1: with T-TSC Class B in RU2: with enhanced T-TSC in RU

|TE| ≤ 95 ns1

|TE| ≤ 140 ns2

TE ≤ ± 130 ns (Cat B)



Thank You!



Q&A

Clock Talk LIVE Schedule – Presentation will begin shortly

Tuesday, Sept 15th IEEE 1588 Timing Solutions for Non-Telecom Applications

Tuesday, Sept 29th Clock Jitter Demystified and Jitter Requirements for 56/112 SerDes

Tuesday, Oct 13th Design Considerations When Selecting a XO/VCXO Clock Reference for 56G/112G SerDes

Tuesday, Oct 27th Stop Guessing, Use Silicon Labs Timing Tools to Build Your Clock Tree

Tuesday, Nov 10th Optimize Timing Solutions for High-Speed FPGA and Application Processor Designs

Tuesday, Nov 17th PCIe Gen 4/5/6 Specifications and Jitter Measurement Explained

Tuesday, Dec 1st Timing Solutions for 5G O-RAN Systems

Tuesday, Jan 12th AEC-Q100 Timing Products for Automotive Applications

Tuesday, Jan 26th Timing Solutions for Open-Compute Systems

34

Register for the series and find past recorded sessions at:



Documents

Clock Talk LIVE Schedule – Presentation will begin shortly...O-Cloud Compliant Software (SW) Functions Refers to infrastructure element(s) based on standard servers, using accelerators,