Class_AB_PA_design report

University of South Florida

College of Engineering

Electrical Engineering MSEE Program

EEL6936: RF and Microwave Power Amplifier Design

Design Report of 15 W Class AB Power Amplifier (1GHz) using

Modelithics TriQuint HMT-QOR-QPD1009-001 in Keysight’s

Advanced Design System

Rahul Ekhande

U37492717

https://learn.usf.edu/webapps/blackboard/execute/courseMain?course_id=_458426_1

RF/MW PA Design Report

Abstract:

The Design of 15 W Class AB Power Amplifier (1GHz) using Modelithics TriQuint HMT-QOR-QPD1009-

001 in Keysight’s Advanced Design System (ADS). The goal parameters are to design Power Amplifier with

bandwidth 20% B.W, Input Return Loss to be less than 10% with gain flatness of +/- 1 dB along whole

bandwidth. The critical parameter is to have Pout (dB) to be more than 39 dB and Power Added Efficiency

(PAE) of 60%. Various design topologies with biasing point have been studied and optimized to get the given

specification using a nonlinear model for above transistor which is available from Modelithics. Stability of

Power Amplifier, Load Pull Analysis for Max. PAE, Power Sweep and Frequency Sweep using ADS were

studied and applied to design.



Contents Introduction: ..................................................................................................................................................... 6

Selection of Bias Point: ................................................................................................................................. 7

QPD1009-001 S- parameters analysis: ......................................................................................................... 8

Input matching network: .............................................................................................................................. 9

Load Pull Analysis: ....................................................................................................................................... 10

Output matching network: ......................................................................................................................... 11

Design Description: ......................................................................................................................................... 12

Power Amplifier: Block Diagram ................................................................................................................. 12

Power Amplifier: Final Schematic ............................................................................................................... 12

Design Layout: ............................................................................................................................................ 16

List of materials/components required: ..................................................................................................... 17

Results: ............................................................................................................................................................ 18

S-parameter and Stability: .......................................................................................................................... 18

Model Power Sweep Simulation: ................................................................................................................ 20

Gain Compression (3 dB): ....................................................................................................................... 21

Load Pull for Final Model with S22: ........................................................................................................ 22

Transistor details and Goals:....................................................................................................................... 23

Transistor and Board details: .................................................................................................................. 23

Goals and Achieved Results: ................................................................................................................... 23

Conclusion:...................................................................................................................................................... 24

References: ..................................................................................................................................................... 25



Figures: Figure 1: Design Flow ...................................................................................................................................... 6

Figure 2: Recommended Operation Condition and Used ................................................................................. 7

Figure 3:Output for recommended biasing ....................................................................................................... 7

Figure 4: Selected Biasing Point ....................................................................................................................... 7

Figure 5:QPD1009-001 S- parameters with max. gain ..................................................................................... 8

Figure 6: Ideal Stability and Input matching network ...................................................................................... 9

Figure 7: S- parameters and Stability factor (K) after Stability and Input matching network .......................... 9

Figure 8:: Shift in S11 after Stability network ................................................................................................. 10

Figure 9:Load-pull analysis showing max. PAE and max. Output power delivered ........................................ 10

Figure 10:: Optimal Load value for max. PAE and Max. Output power delivery ............................................ 11

Figure 11:(a)Ideal (b) Non-ideal (c) Layout model of Output matching network for max. PAE ..................... 11

Figure 12:Block Diagram for Class AB Power Amplifier design ...................................................................... 12

Figure 13:Final Schematic for Class PA using QPD1009-001 model in ADS .................................................... 12

Figure 14:Input DC Block ................................................................................................................................ 13

Figure 15:Input DC supply Capacitor bank ..................................................................................................... 13

Figure 16: Stability Network ........................................................................................................................... 14

Figure 17: Input Matching Network ............................................................................................................... 14

Figure 18: Output DC Block ............................................................................................................................. 15

Figure 19:Output DC supply Capacitor bank .................................................................................................. 15

Figure 20:Final design layout with Carrier ...................................................................................................... 16

Figure 21:Final S-parameters and Stability factor (K) - Broadband (DC to 4GHz) .......................................... 18

Figure 22: Final S-parameters and Stability factor (K) - Narrowband (0.9 GHz to 1.1GHz) ............................ 19

Figure 23:PAE%, S21(dB) and Pout vs RF_input_power ................................................................................. 20

Figure 24:PAE %, S21(dB) and Pout vs Frequency .......................................................................................... 20

Figure 25:3dB Gain Compression .................................................................................................................... 21

Figure 26:: Loadpull for Model ....................................................................................................................... 22



Tables:

Table 1: Project Goals ....................................................................................................................................... 6

Table 2: Bill of Materials (BOM) ................................................................................................................... 17

Table 3: Project Goals without PAE and Pout ............................................................................................... 19

Table 4: PAE S21 and Pout at design frequency and max. within narrowband ............................................. 21

Table 5: Transistor and Board Details ............................................................................................................ 23

Table 6: Goals vs Achieved results ................................................................................................................. 23



Introduction:

The aim of this project is the design of a single stage, class AB power amplifier using TriQuint HMT-QOR-

QPD1009-001 packaged GaN HEMT device for which a nonlinear model is available from Modelithics. The

topology of this power amplifier will include distributed and surface mount components for matching and bias

networks. The bias and operating information of the design is: Vds = 50V, Ids = 30mA, design frequency = 1

GHz. Modelithics CLR models are used for the passive devices supplied to the students for the design of the

power amplifier; the simulation software to be used will be Keysight’s Advanced Design System (ADS).

Refer to Table 1 below for the project goals and information. The process of going from the design phase to

the final layout and simulated data is presented in this project is depicted by the flow chart in Figure 1.

The goals to design a Class AB Power Amplifier is given below:

Table 1: Project Goals

The design flow for building this Power Amplifier is given below:

Figure 1: Design Flow

Goals

1 Type TriQuint HMT-QOR-QPD1009-001

2 Device Type SMT

3 Frequency (GHz) 1

4 Gain (dB) Not Specified

5 PAE (%) 60

6 P1dB (dBm) 39

7 Input Return Loss 10 dB

8 Output Return Loss Not Specified

9 DC Supply 50 V, -2.7 V

10 Board Type and Size 20 mil Rogers 4350

11 Carrier Carrier 1



Design Methods and Calculations: Selection of Bias Point: To design Class AB amplifier and make it capable to achieve goals outlines in above Table 1: Project Goals the given GaN HEMT model was biased near recommended operating voltages as

shown is below figure referred from Model datasheet [3].

Figure 2: Recommended Operation Condition and Used

Below are the Datasheet results [3] showing the model performance for recommended biasing at 1

GHz. As the used biasing is approximately same as that of recommended, the design is promising to

satisfy the required goals.

Figure 3:Output for recommended biasing

The schematic view of used model transistor and V-I characteristics with the selected operating

(biasing) point is shown below

Figure 4: Selected Biasing Point

Recommended Used

Vds +50 V +50 V

Vgs -2.8 V -2.7 V

Id 28 mA 30 mA



QPD1009-001 S- parameters analysis: The selected biasing conditions where used to extract the S parameters of the model transistor to

understand the availed max. gain and I/O impedance. Below are the S- parameters for the QPD1009-

001 model with stability factor plot from DC to 4 GHz.

Figure 5:QPD1009-001 S- parameters with max. gain

From the S- parameters, the max. available gain is 27.4 dB with the input and output impedance right

near the lower periphery of the smith chart. The transistor is unstable till 3 GHz, so the next step is

to design an input matching network (conjugate match) along with the stability network.

The input matching network is to aim for input return loss less than 10 dB and stability network

design aim will be to stabilize the transistor from DC to 4 GHz.



Input matching network: The transistor was conjugately matched with the help of ADS tool ‘Smith Chart’ using lumped

elements. The stability network was added to stabilized the transistor from DC to 4GHz. In stability

network, the shunt capacitor with the resistor R=20 was used to bypass the resistor at high frequency.

The biasing network was integrated in-between the stability network and input matching referring

the block diagram given by Modelithics.

Figure 6: Ideal Stability and Input matching network

Below are the S-parameters for the transistor after input matching and stability network.

Figure 7: S- parameters and Stability factor (K) after Stability and Input matching network



The max. gain and S21 have decreased considerably, but the gain has flattened. The transistor is now

stable from DC to 4 GHz. The input being perfectly matching by the matching circuit; the stability

circuit have shifted the match as shown in below figure. Next step of the design is to put this network

for Load pull analysis to find the output load at which the transistor gives max. PAE and max. Output

power.

Figure 8:: Shift in S11 after Stability network

Load Pull Analysis: After input matching and stability, the circuit was simulated for load-pull analysis to determine the

optimal load point for max. PAE and max. output power. Below figure shows the PAE and Output

power contours with it maximum value and 1dB and 2dB-down contour for power and 10% and

20%-down contour for efficiency. As shown in the above Figure 3, the max. PAE of 68% and max.

output power delivered of 41.46 dBm is approximately same. The next Figure 10 gives the optimal

load value for max. PAE and max. Output power.

Figure 9:Load-pull analysis showing max. PAE and max. Output power delivered



Figure 10:: Optimal Load value for max. PAE and Max. Output power delivery

Output matching network:

Figure 11:(a)Ideal (b) Non-ideal (c) Layout model of Output matching network for max. PAE

The output matching circuit is implemented using lumped elements and design by ADS Smith chart

tool.



Design Description: Power Amplifier: Block Diagram Below Figure 12is the block diagram for the design topology of Class AB power amplifier. The design

flow is given by Modelithics.

Figure 12:Block Diagram for Class AB Power Amplifier design

Power Amplifier: Final Schematic The schematic design shown below Error! Reference source not found.Figure 13 have followed the

topology provided by Modelithics. The matching networks go first (closest to the device terminals). The input

matching circuit used along with stability network for gain flatness, input return loss and PA stability from

DC to 4GHz. The bias line is connected after the matching circuits with the DC feed inductors closest to the

device. DC blocks are closest to the RF connectors to filter out DC right at input.

Figure 13:Final Schematic for Class PA using QPD1009-001 model in ADS

The schematic shown above is represented in blocks, representing the flow given by Block diagram. Insite of

each block is shown below along with its layout representation.



Figure 14:Input DC Block

Figure 15:Input DC supply Capacitor bank

Need for Capacitor Bank:

It is used for stability

It bypasses the RF input power reaching the DC supply



Figure 16: Stability Network

Figure 17: Input Matching Network



Figure 18: Output DC Block

Figure 19:Output DC supply Capacitor bank



Design Layout:

Figure 20:Final design layout with Carrier

Capacitor bank

HEMT model

RF in RF out

Stability

Network

Output

matching

matching

Input matching

DC Block DC Block DC Feed

DC Feed

Vdd -Vgg

Here is the layout design

shown on the carrier used

(Carrier 1).

The dimension of the design is

well within the board

limitation.

Final Dimension:

2.73 in x 1.74

in

1 pF

1 pF 1 pF

5.1 pF 5.1 pF

10 pF 10 pF

1 pF

40 pF

0.2 pF

1.2 pF

pF 49.9 Ω

20 Ω

51 nH 51 nH

2.2 pF

11 nH 2 nH



List of materials/components required:

Series No. Manufacturer Quantity Use

Capacitor

1pF CAP-ATC-0402-101 ATC 2 Capacitor bank

5.1pF CAP-ATC-0402-101 ATC 2 Capacitor bank

10 pF CAP-ATC-0402-101 ATC 2 Capacitor bank

100 nF CAP-ATC-0603-003 ATC 2 DC Block

1.2 pF CAP-ATC-0402-002 ATC 2 Stability

2.2 pF CAP-ATC-0402-101 ATC 1 O/P matching

40 pF CAP-ATC-0603-101 ATC 1 Stability

Inductor

51 nH IND-CLC-0603-102 Coilcraft 2 DC feed

11 nH IND-CLC-0402-201 Coilcraft 1 O/P stability

2 nH IND-CLC-0402-201 Coilcraft 1 I/P stability

Resistor

20Ω RES-KOA-0805-001 KOA 1 Stability

49.9 Ω RES-KOA-0805-001 KOA 1 Stability

Connectors

SMA connectors 2 RF I/O connection

Transistor

HMT-QOR-

QPD1009-001 Qorvo 1

Total Quantity 21

Table 2: Bill of Materials (BOM)



Results: S-parameter and Stability:

The broad-band and narrow-band S-Parameter simulation and stability performance are shown in Figures 21

and 22, respectively. The design dimensions are length = 2731.35 mils, width = 1745.25 mils. The S21 (18.66

dB) is at design frequency is just 0.5 dB less than the max. gain, along with this the gain flatness for 20%

bandwidth was achieved. The transistor is stable from DC to 4 GHz with stability factor K>2. Input return

loss and output return loss goals are satisfied (< 10 dB).

Below are the broadband (Figure 21) and narrowband (Figure 22) S- parameter plot of final model Class

AB PA. All S-parameter goals are satisfied which is shown in below Table 3.

Figure 21:Final S-parameters and Stability factor (K) - Broadband (DC to 4GHz)



Figure 22: Final S-parameters and Stability factor (K) - Narrowband (0.9 GHz to 1.1GHz)

Goals Results

Design Frequency 1GHz (20% Bandwidth) Satisfied

Min Power (dBm) 39 Next page

Max PAE (%) 60% Next page

Gain +/- 1 flat 18.66 dB(+/- 20% B.W)- Satisfied

I/P Return Loss >10 dB Satisfied O/P Return Loss Not Specified >10 dB for 20% bandwidth

Stability Stable Stable (DC to 4 GHz)

Table 3: Project Goals without PAE and Pout


Model Power Sweep Simulation:

Figure 23:PAE%, S21(dB) and Pout vs RF_input_power

Figure 24:PAE %, S21(dB) and Pout vs Frequency

Above Figure 23 gives the PAE %, S21(dB) and Pout vs RF input power sweep. The max input power the

transistor can handle is 27dBm, so the sweep is limited from 0 to 27 dBm. Maximum PAE of 67.33 % with

S21 of 19.24 dB and output power max Pout of 41.2 dBm was achieved. At given design frequency the

goals were achieved.

In Error! Reference source not found.Figure 24, the PAE %, S21(dB) and Pout vs RF frequency (900

MHz to 1100 MHz) is plotted, showing good agreement with Error! Reference source not found.. Table

4 given the extract of above figure showing the achieved results at design frequency and their maximum

values within the narrowband frequency range.

Design Frequency (1GHz) Maximum within narrowband

PAE (%) 67.33 69.81

S21 (dB) 18.66 19.24

Pout (dBm) 40.2 41.23

Table 4: PAE S21 and Pout at design frequency and max. within narrowband

Gain Compression (3 dB):

Figure 25:3dB Gain Compression

Above Figure 25Error! Reference source not found. shows the 3-dB gain compression with output

power, the output power of 39.61 dBm is achieved with gain of 16 dB.

Load Pull for Final Model with S22:

Figure 26:: Loadpull for Model

For above Figure 26, the final model was simulated using load pull analysis. The output smith

chart above shows how well the out matching circuit have matched with the 50-ohm termination

giving max PAE of 68.56 % and Pout load of 39.93 dBm

Transistor details and Goals: Transistor and Board details:

Device type TriQuint HMT-QOR-QPD1009-001 (SMT)

DC Supply Vds= 50 V and Vgs= -2.7 V

Board Type and Size 20 mil Rogers 4350

Carrier Carrier 1

Design Dimension 2.73 x 1.74 in2

Table 5: Transistor and Board Details

Goals and Achieved Results:

Goals Results

Design Frequency 1GHz (20% Bandwidth) Satisfied

Min Power (dBm) 39 Satisfied-40.2

Max PAE (%) 60% Satisfied- 67.33

Gain +/- 1 flat 18.66 dB(+/- 20% B.W)- Satisfied

I/P Return Loss >10 dB Satisfied O/P Return Loss Not Specified >10 dB for 20% bandwidth

Stability Stable Stable (DC to 4 GHz) Table 6: Goals vs Achieved results

Conclusion: In this report a Class AB Power Amplifier was designed using TriQuint HMT-QOR-QPD1009-001 GaN

HEMT amplifier. The Model of same is available in ADS provided by Modelithics was used. Biasing point

for the transistor was selected per the datasheet provided by Modelithics. The results achieved in the ADS

simulation are well above the design goals as shown in Table 6. The maximum PAE of 67.33 % and

Output power delivered Pout of 40.2 at design frequency of 1 GHz was achieved. S21 of 18.6 dB and

+/- 1 dB flatness was achieved across the 20 % bandwidth. The device is stable from DC to 4 GHz with

stability factor K> 2 across all frequencies. The closing the loop i.e. comparison between the measured

data and model data cannot be done as the fabrication of the device is under process.

References:

1. Tsang, Kai Shing. "Class-F Power Amplifier with Maximized PAE." (2010).Waveform Shaping

sub circuit at input and output for Harmonics suppression and Max. PAE

2. Modelithics TriQuint HMT-QOR-QPD1009-001 Datasheet from https://www.modelithics.com

3. Presentation on load pull simulation using ADS, http://www.agilent.com/

4. Webcast Series: RF power Amplifier Design series by Andy Howard

https://www.modelithics.com/

http://www.agilent.com/

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Class_AB_PA_design report