Class-D Audio Amplifier

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© 2007 Texas Instruments Inc,

Content developed in partnership with Tel-Aviv University

From MATLAB® and Simulink® to Real Time with TI DSPs

Class-D Audio Amplifier

Slide Slide 22© © 2007 Texas Instruments Inc, 2007 Texas Instruments Inc,

System Description

Input Stage

•Protection Circuit •Buffer •DC shift

TMS 320F2808

•Analog to PCM Conversion•PCM to PWM Conversion

Output Stage

(Amplifier)

•Switching Amplifier •H-Bridge•LPF

Audio Source


Audio Source

The System

5VPower Supply

12VPower Supply


Analog to Digital (PCM) Conversion

+3

+2.25

1.5

.75

0

PCMsamples

Samplingperiod

FFFh

000h

800h

C00h

400h

+2.625

+1.875

Original Analogsignal

1.125

-0.375

E00h

A00h

200h

600h

4095

1536

2048

3584

2560

3072

1024

512

0


PCM to Duty Cycle Conversion

FFFh

000h

800h

C00h

400h

E00h

A00h

200h

600h

4095

1536

2048

3584

2560

3072

1024

512

0

1023

384

512

896

640

768

256

128

0

3FFh

000h

200h

300h

100h

380h

280h

080h

180h

PCM ValuePCM Value Duty CycleDuty Cycle

Shift Right 2 bitsShift Right 2 bits


PWM

100 %

50 %

0 %

75 %

25 %

FFFh

C00h

800h

400h

0

50 %

94 %

94 %

75 %

75 %

25 %

25 % 6 %

6 %

PCMOriginal Analogsignal

PCMsamples

PCM PWM


t

V

TPWM

PWM

t

R L

C

PWM Analog


+ -Driver Driver

PVdd ( DC- Bus)

PWM1 PWM2

A

A

B

B

L L

PWM 50 %10%

90%

PWM

L+

PVdd

PVdd

L-

2 x PVdd

(L+) - (L-)

H-Bridge Power Topology


TMS 320F2808

Input Circuit FunctionalityInput Circuit Functionality

Input StageAudio Source

•Analog Signal •Amplitude Scaling•DC removal•Limits DSP Input Voltage 0 – 3.3 V•Protection Circuit •Buffer •DC shift•VRef for ADC

ADC

•Analog to Digital (PCM) Conversion:•0-3.3 V 0-0xFFF


Input CircuitInput Circuit

Reference Reference VoltageVoltage1.5 V1.5 V

Protection Protection CircuitCircuit DC/DC ConverterDC/DC Converter

DC RemovalDC Removal+Volume+Volume

Buffer+HPFBuffer+HPF

To eZDSP-F2808

P8-1

GND


TMS 320F2808

Output Circuit FunctionalityOutput Circuit Functionality

Output Stage

(Amplifier)

•Switching Amplifier •H-Bridge•LPF

CPU EPWM

•PCM to PWM Conversion•PWM Control


Output CircuitOutput CircuitD 1M A 2 Y D 2 3

12

L 1U C 5 0 2 2 T-6 8 1 (2 2 u H / 4 A )

L 2U C 5 0 2 2 T-6 8 1 (2 2 u H / 4 A )

V 1 5

J 1

12

R 1 34 . 7 K

C 8

1 0 0 n / 1 0 V

V 3 _ 3

C 5

0 . 4 7 / 5 0 V

D 4M A 2 Y D 2 3

12

+C 1 6

4 7 . 0 / 2 5 V C 1 41 0 0 n

V 3 _ 3

V 3 _ 3

C 9

1 0 0 n / 3 0 V

V 1 5

C 1 31 0 0 n

R 1 44 . 7 K

C 70 . 0 4 7 / 5 0 V

C 10 . 0 4 7 / 5 0 V

U 5 A

7 4 H C 8 61

23

U 5 B

7 4 H C 8 64

56

U 5 C

7 4 H C 8 69

1 08

C 1 7

1 0 0 n / 3 0 V

V 1 5

U 5 D

7 4 H C 8 61 2

1 31 1

C 1 8

1 0 0 n / 3 0 V

V 1 5

o p wm a 1

Q 1I R F 5 4 0 N

Q 3I R F 5 4 0 N

D 5 M A 2 Y D 2 312o p wm a 2

V 1 5

D 2 M A 2 Y D 2 312

R 2 9 . 1

C 4

0 . 4 7 / 5 0 V

V 3 _ 3C 2

0 . 6 8 u

V 3 _ 3

P 1

H e a d e r 6

G N D12

+1 5 V+3 . 3 V

3

G N D4

C 60 . 6 8 u

D 3 M A 2 Y D 2 312

D 6 M A 2 Y D 2 312

V 1 5

C 3

1 0 0 n / 3 0 V

L 3 C H O K E

R 3 9 . 1

V 1 5V 1 5

V 1 5

U 2

I R 2 0 1 1

H I N5

L I N6

C O M7

L O8

V S4

H O3V B2

V C1

Q 2I R F 5 4 0 N

R 6 9 . 1

R 7 9 . 1

V 1 5V 1 5

V 1 5

U 3

I R 2 0 1 1

H I N5

L I N6

C O M7

L O8

V S4

H O3V B2

V C1

Q 4I R F 5 4 0 N

+C 1 1

1 0 0 0 . 0 / 2 5 V

DriversDrivers ProtectionProtectionFull Full BridgeBridge LPFLPF

EPWM1 - P8/9

EPWM2 - P8/11

PWM InversionPWM Inversion


Voltage Supply

Input Stage eZDSP-F2808

Output Stage

(Amplifier)

5 V

12 V

DC/DC3.3 V


Software RequirementsSoftware Requirements

TMS 320F2808

The input Signal in range 0~3V The Conversion Sequence starts on SOC signal Conversion Sequence capture 8 times the same channel with configuration: ADC Clock = 12.5 MHz S/H width = 320ns Generates Interrupt at the end of each Conversion Sequence

At the Start:Initialize: CPU clock to 100MHz GPIO for PWM output Interrupt Vector (PIE)Set up ADC, PWMEnable HRPWM calibrationSelect Interrupt on ADC EOS

Perform Endless Loop of HRPWM calibration

PWM width is 1000 CPU clocks = 10us = 100KHz Timer in Up-count modeValues loaded at the end of PWM duty cycle When Timer is zero PWM is inactive When Timer = Value PWM is active Generate SOC signal at the start of each PWM duty cycle (Timer is zero)

ADC CPU EPWM


Timer=CMPA

Timer=zeroCMPA Updated

Timer=zeroSOC is

generated

PWM Timer

PWM1A Out

SOC Impulse

Interrupt

Exit Interrupt

Timing DiagramTiming Diagram

PWM2A Out

PWM1A=Set

PWM2A=Clear

ISR exit CMPA

updated

Analog to PCM

ConversionADC generates

Interrupt End-of-

Sequence

PCM tp PWMConversion

CMPA Calculation

PWM1A=Clear

PWM2A=Set


Simulink Model


Hardware Interrupt Module


ADC Configuration


ePWM1 Settings (1)ePWM1 Settings (1)

• Time-Base Settings:

• PWM Frequency 97.6 KHz

(100 MHz/1024)

• with up-count mode timer



• Counter-Compare: • Load new Value at

the start of PWM duty cycle

• Action-Qualifier:

• PWM= ‘1’ for TBCTR=0

• PWM =‘0’ for

TBCTR=CMPA



• Event-Trigger: •Generate SOC to module A at the start of PWM duty cycle



• Time-Base Settings:

• PWM Frequency 97.6 KHz

(100 MHz/1024)

• with up-count mode timer



• Counter-Compare: • Load new Value at

the start of PWM duty cycle

• Action-Qualifier:

• PWM= ‘0’ for TBCTR=0

• PWM =‘1’ for

TBCTR=CMPA



• Event-Trigger not activated

Documents

Class-D Audio Amplifier