NIETJOURNALoFENGINEERING&TECHNOLOGY

Winter 2011

VHDL IMPLEMENTATION OFINTERLEAVERS: FUNDAMENTALSAND RECENT DEVELOPMENTSFOR WIMAX AND WLAN

OJNOJL!)

IO'lNNNZCJ)CJ)

Deepak Bhardwaj' SP Singh' VKPande/

Abstract Introduction

In this age of wireless communication, WLAN and

WiMax are the most common IEEE standards used for

wireless. The concept of OFDM is used in these

standards to obtain a high data rate in addition to

reducing the effects like inter symbol interference and

inter channel interference. It has proved to be the air

interface for the next generation Broadband Wireless

System. FEC is a widely used technique to reduce

the error. Interleaver is an important and powerful

technique to combat a burst of errors for FEC coded

signal. In this paper, different inter-Ieaver schemeswhich are implemented using VHDL on FPGA

platform with all code rates and modulation schemeshave been reviewed in relation to their fundamental

application and challenges.

Keywords: BWA, BER, WIMAX, WLAN, FEC, EEC,

OFDM

Growth of high-performance wirelesscommunication systems has drasticallyincreased over the last few years [1-2]. Due torapid advancements and changes in radiocommunication systems, there is always a needfor flexible and general purpose solutions forprocessing the data[3].Broadband WirelessAccess (BWA) has become the most importantand challenging segment of the wirelessrevolution since it is a viable alternative to thecable modem and digital subscriber line [4-6].High processing speed, design flexibility andfast design Turn around Time (TAT) are theimportant requirements of BWA to meet thechallenges posed to it [7-9]. To meet theserequirements the designers choose the flexibleVHDL and reconfigurable hardware platform likeField Programmable Gate Array(FPGA) [10-12].

'Deptt. of Electronics and CommunicationEngineeringNoida Institute of Engineering &Technology, Gr Noida, India

Orthogonal Frequency Division Multiplexing(OFDM) technique offers a promising solutionthat has gained tremendous research interest inrecent years due to its high transmissioncapability and also for alleviating the adverseeffects of Inter Symbol Interference (ISI) andInter Channel Interference (ICI)[13-14]. In anOFDM system, the data is divided into multipleparallel sub-streams at a reduced rate and eachis modulated and transmitted on a separateorthogonal subcarrier [15-17]. This increasessymbol duration and improves system

1Deptt. of Electronics and CommunicationEngineeringNoida Institute of Engineering &Technology, Gr. Noida, India

JDeptt. of Electronics and CommunicationEngineeringNoida Institute of Engineering &Technology, Gr.Noida, India

-------

robustness [18-19]. OFDM is achieved byproviding multiplexing on users' data streams onboth uplink and downlink transmissions [20].OFDM is the fundamental building block of thedifferent IEEE wireless standards [21]. The mainfunction of a communication system is totransmit information from the Source to thedestination with sufficient reliability. The errorcorrection codes (ECG) play a very importantrole in modern digital communication systems.Interleaving is an important and powerfultechnique to combat burst of errors for FECcoded signal. This technique is traditionally usedto reduce the bit error rate (BER) of digitaltransmission over a bursty channel. Aninterleaver takes a given sequence of symbolsand permutes their positions, arranging them in adifferent temporary order. The basic goal of aninterleaver is to randomize the data sequence.When used against burst errors, interleavers aredesigned to convert error patterns that containlong sequences of serial erroneous data into amore random error pattern, thus they distributeserrors among many code vectors. Interleaversare classified into two broad types: periodicinterleaver and pseudo-random interleaver. Inperiodic interleaver, symbols of the transmittedsequence are scrambled as a periodic functionof time .The two main classes of periodicinterleaving are: block interleaving andconvolutional interleaving. Pseudo-randominterleaver rearranges the data in a pseudo-random sequence. The principal aim of this workis to review the efficient VHDL implementation ofconvolutional interleaver and block interleaverfor common OFDM based IEEE standards likeWLAN and WiMax which leads to higheroperating frequency, better resource utilization,lower power consumption and reduced delay inthe interconnection network.

The rest otthe paper is organized as follows:section II presents the detail of interleaving indigital data communication. Section III describesbasics of convolutional interleaver. Section IVdescribes the proposed hardware model of theefficient convolutional interleaver. Section Vdescribes basics of block interleaver. Section VIdescribes the proposed hardware model of the

Winter 2011

FSM based block interleaver for WLAN. SectionVII describes the proposed hardware model ofthe block interleaver for Wi Max. Section VIIIdescribes critical analysis of FPGAimplementation. Concluding remarks are givenin Section IX.

II. INTERLEAVING

Interleaving is a tool that can be used in digitalcommunications systems to enhance therandom error correcting capabilities of blockcodes. The interleaver subsystem rearrangesthe encoded symbols over multiple code blocks.This effectively spreads out long burst noisesequences so they appear to the decoder asindependent random symbol errors or shorter,more manageable burst errors. The amount oferror protection based on the length of the noisebursts determines the span length or depth ofinterleaving required.

Interleaving can be classified as either periodicor pseudo-random. The periodic interleaverorders the data in a repeating sequence of bytes.The two main classes of periodic interleavingare: block interleaving and convolutionalinterleaving [22]. The block Interleaver ordersthe data in a repeating sequence of bytes. Thetwo main classes of periodic interleaving are:block interleaving and convolutional interleaving[22]. The block interleaver accepts symbols inblocks and performs identical permutations overeach block of data. One way this isaccomplished involves taking the input data andwriting the symbols by rows into a matrix with irows and n columns and then reading the dataout of the matrix by columns. This is referred toas a (n,i) block interleaver and in convolutionalinterleaver the code word symbol from theencoder is fed into the array of shift registers, onecode symbol to each row. With each new codeword symbol the commutator switches to a newregister and the new code symbol is shifted outto the channel. Pseudo-random interleaverrearranges the data in a pseudo-randomsequence. Periodic interleaving is morecommonly invoked because it is more easilyaccomplished in hardware.

NIETJOURNALoFENGINEERING&TECHNOLOGY

I

S_I

Fig. 1.Communication system(WiMax PHY layer).

III. Convolutional interleaver

A convolutional interleaver consists of N rows ofshift registers, with different delay in each row. Ingeneral, each successive row has a delay whichis J symbols duration higher than the previousrow. The code word symbol from the encoder isfed into the array of shift registers, one codesymbol to each row. With each new code wordsymbol the commutator switches to a newregister and the new code symbol is shifted out

to the channel. The i-th (1 ~ i ~ N-1) shift register

has a length of (i-1)J stages where J = M/N andthe last row has M-1 numbers of delayelements[23]. The convolutional deinterleaverperforms the inverse operation of the interleaverand differs in structure of the arrangement ofdelay elements. Zeroth row of interleaverbecomes the N-1 row in the deinterleaver. 1strow of the former becomes N-2 row of later andsoon.Delav 0EJen;ent ~

~r----------__••

.------------------~X-I~=======~FIG.2. Convolutional interleaver

IV. Proposed model of convolutionalinterleaver

The proposed VHDL model of an 8 bit

Winter 2011

Convolutional interleaver with J = 1 is presentedin Fig. 3. The code word symbols (Din) receivedin serial form from an encoder is converted intoan 8 bit parallel code word by a Serial InputParallel Output (SIPO) register. The SIPO outputchanges its value with each clock which is notdesirable at the input of the delay unit. The bufferunit delivers a word to the delay unit after every 8Clock cycles. The delay unit is comprised ofeight rows and is having the structure asnarrated in Fig. 2[24]. Each code symbol of the 8bit code word is applied to the respective row ofthe delay unit. The code word gets scrambled asit progresses through the delay unit. Thescrambled code word then applied to the input ofan 8 line to 1 line multiplexer (MUX) whichconverts it into a stream of serial data(Dout) [25] [26]. The interleaver circuit requires aclock signal to drive the SIPO register; a clockcircuit and a three bit counter [27]. The clockcircuit basically divides the system clockfrequency by 8 which is used to drive the bufferand delay unit[28]. The 3 bit counter generatesthe select inputforthe MUX[29].

Dm ....• SIPO 8register

8 8D"",

CJock- ...•....-+--~

Fig.3 Block diagram of proposed 8 bitconvolutional interleaver.

V. Basics of block interleaver

The block interleaver is loaded row by row with Lcodewords, each of length n bits. These L codewords are then transmitted column by columnuntil the interleaver is emptied. Then theinterleaver is loaded again and the cyclerepeats. At the receiver, the codewords aredeinterleaved before they are decoded. A burstof length L bits or less will cause no more than 1bit error in anyone codeword. The random errordecoder is much more likely to correct thisSingle error than the entire burst. The parameterL is called the interleaver depth. The interleaverdepth is chosen based on worst case channelconditions. It must be large enough so that the rrrr=-II

interleaved code can handle the longest error

bursts expected on the channel. The maindrawback of block interleavers is the delayintroduced with each row-by-row fill of theinterleaver.

• • tI I ••Iij

II

Fig 4 Block interleaver

VI. Hardware model of interleaver for wlan.

The proposed hardware model of OFDM basedWLAN interleaver consists of two sections:address generator and interleaver memory.

raw data

read address +Address write address Interleaver

Generator kci Memory

"finterleaved data

Fig 5. Top level view of interleaver

A.Address generator

Our proposed design of address generator blockis described in the form of schematic diagram inFig. 6[30]. Bulk of the circuitry is used forgeneration of write address. It contains threemultiplexers (muxs): mux-1 and mux-2implements the unequal increments required in16-QAM and 64-QAM whereas mux-3 routes theoutputs received from mux-1 and mux-2 alongwith equal increments of BPSK and QPSK. Theselect input of mux-1 is driven by aT-flipflopnamed qam16_sel whereas that of mux-2 iscontrolled by a mod-3 counter, qam64_sel. Thetwo lines of rnod typ (modulation type are usedas select input of mux-3. The 6-bit output from themux-3 acts as one input of the 9-bit adder afterzero padding. The other input of the addercomes from accumulator, which holds theprevious address. After addition a new address iswritten in the accumulator.The preset logic is a

Winter 2011

elk elr

write9 address

elkelk clf

I ,el generator f-+ ,01

• •elk elfmod jyp

Fig 6. Schematic diagram of addressgenerator

hierarchical FSM whose principal function is togenerate the correct beginning addresses for allsubsequent iterations. This is presented inreference.

B. Interleaver memory

The interleaver memory block comprises of twomemory modules (RAM-1 and RAM-2) , threemuxs and an inverter as shown in Fig. 7. In blockinterleaving when one memory block is beingwritten the other one is read and vice-versa. Eachmemory module receives either write address orread address with the help of the mux connectedto their address inputs (A) and selline. RAM-1 atthe beginning receives the read address andRAM-2 gets the write address with write enable(WE) signal of RAM-2 active. After a particularmemory block is read / written up to the desiredlocation, the status of sel changes and theoperation is reversed. The multiplexer at theoutput of the memory modules routes theinterleaved data stream from the read memoryblock to the output.

RA.\I·Irawdata----<J>-+llno".~· I

read address

interleaved(lata

FIG 7.Schematic view of interleaverMemory block.

NIETJOURNALorENGINEERING&TECHNOLOGY

VII. HARDWARE MODEL OF Interleaver forwimax

As shown in Fig.8 [31], the design conceptcontains three levels of multiplexer. The first levelMUXs implement the unequal incrementsrequired in 16-QAM and 64-QAM. The four-interleaver depths of 16-QAM are implementedby the first four MUXs from the top in level 1. Theselect inputs of these four MUXs are tied togetherand are driven by a T-flip flop namedQAM16_SEL. Similarly, the last four MUXs are for64-QAM modulation. The select inputs are drivenby a mod-3 counter - QAM64 SEL. The secondlevel MUXs basically pick up o-ne input based onthe values of ID [32]. The topmost MUX in level 2implements the eight interleaver depths of QPSKmodulation scheme available by concatenationof sub-channels. The second and third MUXs inlevel 2 are for 16-QAM and 64-QAM respectively.The outputs from level 2 MUXs are routed to thenext section by level 3 MUX based on MOD TYPvalue[33]. The 7-bit output from the level 3MUXacts as one input to the 1O-bit adder circuit afterzero padding. The other input of the addercomes from the Accumulator, which holds theprevious address. After addition a new addressis written in the Accumulator [34]. The presetlogic is a FSM whose principal function is toqenerate the correct beginning addresses for all

MVXIHHI

MtAlfH~~6

9

l1

Fig 8 .Address generation scheme.

Winter 2011

subsequent iterations [35].

VIII. Critical analysis of fpga implementation

The proposed VHDL model of the interleaver isprepared using Xilinx Integrated SoftwareEnvironment (ISE) [36-37] and is implementedon Xilinx Spartan-3 FPGA[38-39]. Simulationresult of the proposed interleaver for OFDMbased WLAN and WIMAX is presented in theform oftiming diagram [40-41].

IX. Conclusion

In this paper an efficient VHDL model of theConvolutional and FSM based block interleaverfor WLAN and WIMAX are reviewed. Simulationresult has been taken from different literature.Both interleaver techniques reduce FPGAresource utilization, less power consumption,reduced FPGA interconnection delays andlower memory wastage compared to popularimplementation techniques.

DOReferences1. A. Ghosh, D. R. Wolter, J. G. Andrews and R.

Chen, "Broadband Wireless Access withWiMAX/802.16: current performancebenchmarks and future potential," IEEECommunication Magazine, vol. 43, pp.129-36, Feb. 2005.

2. J. B. Kim, Y J. Lim, and M. H. Lee, A lowComplexity FEC design for DAB, IEEE ISCAS,Sydney, Australia, pp. 522-525, 2001

3. "Air interface for fixed broad band wirelessaccess systems"IEEE standard 802.16-2004,2004

4. "Air interface for fixed and mobile broad bandwireless access systems"IEEE standard802.16e, 2005

5. J G. Andrews, A. Gosh, R. Mohamed,Fundamentals of WiMax: understandingBroadband Wireless Networking., PrenticeHall PTR, Upper Saddle River, NJ, 2007.

6. IEEE Std 802.11a-1999, "Wireless LANMedium Access Control (MAC) and PhysicalLayer (PHY) specifications: High SpeedPhysical Layer in the 5 GHz Band," July 1999.

7. J. Garcia, "FPGA-Based HardwareImplementations of OFDM Modules for IEEE802 standards: A common design," ThesisReport, Tonantzintla, Mexico, Sep.2005.

8. IEEE 802.16e-2005: "IEEE Standard for localand metropolitan area networks, Part 16: AirInterface for Fixed Broadband Wireless AccessSystems - Amendment 2: Medium AccessControl Layers for Combined Fixed and MobileOperations in Licensed Bands."

9. ETSI EN 300-744 V1.5.1: "Digital VideoBroadcasting (DVB); Framing Structure,Channel Coding and Modulation for DigitalTerrestrial Television," Nov. 2004.

10. IEEE 802.11-2007: "Standard for local andmetropolitan area networks, Part 11: WirelessLAN Medium Access Control (MAC) andPhysical Layer (PHy) Sepcifications," Revisionof IEEE Std. 802.11-1999.

11. W.Konhauser, "Broadband wireless accesssolutions progressive challenges and potentialvalue of next generation mobile networks",Wireless Personal Communications, vol 37,May 2006, pp.243--259

12. IEEE std. 802.11a-1999, "Wireless LANMedium Access Control (MAC) and PhysicalLayer (PHY) specifications: High SpeedPhysical Layer in the 5 GHz Band," July 1999.

13. IEEE std. 802.11g-2003, "Wireless LANMedium Access Control (MAC) and PhysicalLayer (PHy) specifications, Amendment 4:Further Higher Data Rate Extension in the 2.4GHz Band" July 2003

14. S. B. Wicker, Error Control System for DigitalCommunication and Storage, EnglewoodCliffs, NJ: Prentice-Hall, Inc.

15. J. Hieskala and J. Terry. OFDM Wireless LANs:A Theoretical and Practical Guide. SAMSPublishing, U.S, 2002.

16. U. S. Jha and R. Prasad, OFDM towards fixedand Mobile Broadband Wireless Access.Artech House Publisher.2007

17. A. Sghaier, S. Ariebi, and B. Dony, "A pipelinedimplementation of OFDM transmission onreconfigurable platforms", CCECE08Conference, Dec, 2007

18. K. Chang, G. Sobelman, E. Saberinia and A.Tewfik,"Transmitter Archeiticture for PulsedOFDM," in the proc. of the 2004 IEEE Asia-Pacific conf. on circuits and systems, Vol. 2,Issue 6-9, Tainan, ROC, Dec. 2004.

19. M. Engels. Wireless OFDM Systems: How toMake Them Work? Springer, 2001 .

20. IEEE Std 802.11 a-1999, "Wireless LAN MediumAccess Control (MAC) and Physical Layer

Winter 2011

(PHy) specifications: High Speed PhysicalLayer in the 5 GHz Band," July 1999.

21. A. Sghaier, S. Ariebi, and B. Dony, "A pipelinedimplementation of OFDM transmission onreconfigurable platforms", CCECE08Conference, De, 2007.

22. S. Vafi, T. Wysocki and I. Burnett,"Convolutional interleaver for unequal errorprotection of turbo codes," Joint 7thInternational Symposium on DSP andCommunication Systems (DSPCS) and 2ndWorkshop on the Internet,Telecommunicationsand Signal Processing (WITSP), pp. 485-491,Dec.2003.

23. B. K. Upadhyaya and S. K. Sanyal, "VHDLModeling of Convolutional Interleaver-Deinterleaver for efficient FPGAimplementation, International Journal ofRecent Trends in Engineering, AcademyPublisher, Finland, , November, 2009.

24. S. Vafi and T. A. Wysocki, Application ofConvolutional Interleaver in Turbo Code withunequal error protection, Journal ofTelecommunication and Information Theory,pp.17-23, Jan. 2006.

25. S. Vafi and T. Wysocki: "Weight distribution ofturbo codes with convolution interleavers," lETCommunications, 2007, Vol. 1(1), pp.71-78.

26. S. Vafi and T. Wysocki: "Performance ofconvolutional interleavers with differentspacing parameters in turbo codes," Proc. of6th Australian Communication TheoryWorkshop, Feb. 2005, pp. 8 -12.

27. C. Berrou, A. Glavieus and P. Thitimajshima:"Near Shannon limit error-correcting codingand decoding: Turbo-codes," Proc. of IEEEICC, May 1993, vol. 2, pp. 1064 -1070.

28. Ji-Hoon Kim and In-Cheol Park: "Duo-binarycircular turbo decoder based on border metricencoding for WiMAX," Proc. of IEEE ASPDAC,March 2008, pp. 109 -11 O.

29. Cheng-Hung Lin, Chun-Yu Chen and An-YeuWu: "High- Throughput 12-Mode CTC Decoderfor WiMAX Standard," Proc. Of IEEE VLSI-DAT,April 2008, pp. 216 - 219.

30. B. K. Upadhyaya and S. K. Sanyal "Design of ANovel FSM based Reconfigurable MultimodeInterleaverfor WLANApplication. "IEEE 2011.

31. B. K. Upadhyaya, I. S. Misra and S. K. Sanyal,"Novel design of address generator for WiMAXmulti mode interleaver using FPGA based finite

NIETJOURNALorENGINEERING&TECHNOLOGY

state machine," ICCIT 2010, AUST, Dhaka,Dec.,2010

32. E. Tell, and D. Liu, "A hardware architecture fora multimode block interleaver", ICCSC,Moscow, Russia, June 2004.

33. R. Asghar, and D. Liu, "Low complexitymulti mode interleaver core for WiMAX withsupport for c.

34. R. Asghar and D. Liu, "Low complexity multimode interleaver core for WiMAX with supportfor convolutional interleaving," InternationalJournal of Electronics, Communications andComputer Engineering, vol. 1, no. 1, pp.20-29,2009.

35. Xilinx Inc., "Interleaver/De-Interleaver,"Product Specification, v5.1, DS250, March2008.

Winter 2011

36. Altera Inc., "Symbollnterleaver/De-InterleaverCore," Mega Core Function User's Guide, ver.1.3.0, June 2002.

37. Lattice Semiconductor Inc., "Interleaver/De-Interleaver IP Core," ispLever Core User'sGuide, ipug_ 61_ 02.5, August 2008.

38. Xilinx, 'Spartan-3 FPGA Family: Complete DataSheet, '2007, available at www.xilinx.com.

39. Altera, 'Cyclone III Device Handbook, vol. 1,'2007 available at www.altera.com.

40. D. Perry, VHDL: Programming by Example, 3rdEdition,Tata McGraw Hill, New Delhi, 2001.

41. S. Brown & J. Rose, "FPGA and CPLDArchitectures: A Tutorial", IEEE Design & Testof Computers, Summer 1996, pp. 42-57.

000

In case of Tridax procumbens the synergisticanalgesic effect showed significance with as less as 50

mg / kg, p.o. of Ibuprofen: But with less than 50 mg/kg, p.o.the synergistic effect of Trida» procumbens was insignificant. In

the analgesic model, the analgesic effect of the herb was highest in the2nd hr: But, when lbuprofen was added the highest analgesic effect

was seen in the 1st hr (due to the action of lbuprcfen).

Mitra Mazumder Papiya, Das Saumya, Das Sanjita,Basu Saumya P and Das Manas K,NIET Journal of Engineering and Technology,Vol.: I (Autumn 2010) . p 91.

Winter 2011

NIET JOURNAL OF ENGINEERING & TECHNOLOGYINSTRUCTIONS FOR AUTHORS

NIET-Journal of Engineering & Technology (NIET-JET) is a bi-annual and multidisciplinary research journalcovering all areas pertaining to science, engineering and technology. NIET-JET offers a valuable opportunityfor the rapid publication of research papers and articles related to any aspect of science, engineering andtechnology.NIET -JET welcomes• Research papers• Reviews• Short communications• Science and technology news• Information on new books, book reviews and documents• Information on conferences/seminars/workshops and training programmes in various parts of the world• Report on conferences held recentlyAll manuscripts should be typed double-spaced and in 12 pt Times New Roman including footnotes, references,tables and figures. Manuscripts for publication must contain original work, focus on the core aims and the scope ofthe journal should be clearly and correctly written. The manuscript must be accompanied by a covering letter. In caseof an article having more than one author, the entire correspondence regarding the article will be made with thecorrespondence author. The Editorial Board reserves the right to condense or make necessary alterations in thescript. Manuscripts should be strictly in accordance with the prescribed format of the journal. Proof(s) may not besent to the authors (s).Title of article - Title should be concise and informative, describing the contents of pages.Abstract - The abstract should present a brief summary of the paper including questions being addressed and thekey findings of the study. It should not serve as an introduction nor contain references. It should be of one paragraphnot exceeding 200 words.Key words - Between 3-1 0 key words.Introduction - It should include the scientific importance, historical background, relevance to other areas andobjectives of the paper.Material and Methods -It should be written in sufficient detail to enable others to repeat the author(s) work.Result and Discussions- These may be combined or kept separate.Tables and Figures - Number the tables as Table 1, Table 2 etc. Figures should be completely labelled, taking intoaccount the need for necessary size reduction. Captions should be typed, double spaced on a separate sheet.Numberthefigures as Fig. 1, Fig. 2 etc.References - Within the text, references should appear as consecutive numbers in brackets (e.g., [1], [1,2,3,]). Thelist of references should be given in the order of the first appearance of references in the text. The list of referencesshould be formatted as follows:

1. For Articles in the Journal: Indicate the initials and surnames of the authors, the title of the journal in italics, thevolume number, the number of the first page, the year of the reference (in parentheses), for example, M. Smith,G. Gaur, and I. Mehta, LaserPhys., 1: 123 (1991).

2. For Books: S.S. Mishra, S. Morgan, and P. Charlton, Quantum Mechanics (Allen, New York, 1990).3. Conference Proceedings: J. Ansell, I. Harrison, and C. T. Foxon: Proceedings of the 4th International Conference

n Chemistry, Colorado, USA, 2001, Part A (Wiley-VCH, Berlin, 2002), pp. 279-282.4. References to Online Material: http//www.kzoo.edu/ajp/docs/information.html.5. Reference to a Thesis: A. J. Agutter, Ph. Dthesis, Edinburgh University (Edinburgh, UK, 1995).Submission of manuscripts1. All manuscripts should be submitted by email toeditor.nietjet@gmail.com. Text must be prepared in MS-word

software. Also one hard copy of manuscript should be sent to the Editor.2. The submitted manuscript should have a covering letter and undertaking with the signature of the corresponding

author.3. A declaration and copyright transfer form must be furnished by the corresponding author at the time of

submission of manuscripts for publication in the prescribed form.4. Bio-sketch along with a scanned photograph of the authors must also be sent.