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8/13/2019 Circuit Performance
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Circuit Characterization
Performance Estimation
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Introduction
making chips that work well, where "well" can be definedas fast, low in power, inexpensive to manufacture and
reliable.
we must develo wa s to estimate the oodness of eachoption, especially with regard to speed and power
consumption.
The most obvious way to characterize a circuit is throughsimulation, only inform us how a particular circuit
behaves, not how to change the circuit to make it better.
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Dela Estimation• logic paths that do not require any conscious effort when it
.
• there will be a number of paths, called the critical paths, thatrequire attention to timing details.
• can be recognized by experience or timing simulation, butmost designers use a timing analyzer,
• The critical aths can be affected at four main levels:
– The architectural/micro architectural level
– The logic level
– The circuit level – The layout level
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The architectural/micro architectural level
• a broad knowled e of both the al orithms that
implement the function and the technology beingtargeted.
• suc as ow many ga e e ays n a c oc cyc e, owfast addition occurs, how fast memories are accessed,
and how long signals take to propagate along a wire.
• Tradeoffs at the micro architectural level include the
num er o p pe ne s ages, e num er o execu onunits, and the size of memories.
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Logic level
• Tradeoffs include t es of functional blocks e. ., ri le
carry vs. look ahead adders), the number of stages ofgates in the cycle, and the fan-in and fan-out of the gates.
• The transformation from function to gates and registerscan be done b ex erience b ex erimentation orincreasingly by logic synthesis.
• Remember, however, that no amount of skillful logicdesign can overcome a poor micro architecture.
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• Once the logic has been selected, the delay can be tuned
at t e c rcu t eve y c oos ng trans stor s zes or us ngother styles of CMOS logic.
• Finally, delay is dependent on the layout.
• e oor p an e er manua y or au oma ca ygenerated) is of great importance because it determinesthe wire lengths that can dominate delay.
• Tuning of particular cells can also reduce parasiticca acitance.
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Simulation Tools Vs Manual Calculation
• Dela estimation is essential to desi nin critical aths.
• circuit simulators can compute very detailed switchingwaveforms and accurately predict delay, good designerscanno e epen en on s mu a on a one.
• Simulation only answers how fast a particular circuito erates the do not resolve the more interestinquestion of how the circuit could be modified to operatefaster.
• mp e mo e s a ow us o rap y es ma e e ay,understand its origin, and figure out how it can bereduced.
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Definitions
• Rise time, t = time for a waveform to rise from 20% to
80% of its steady-state value• Fall time, tf-= time for a waveform to fall from 80% to
o s s ea y-s a e va ue
• Edge rate, trf
= (tr
+ tf
)/2
• =, p input crossing 50% to the output crossing 50%
• Contamination delay time, tcd = minimum time from the
input crossing 50% to the output crossing 50%
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Switch-level RC Dela Models
• The a roximate the nonlinear transistor I-V and C-V
characteristics with an average resistance andcapacitance over the switching range of the gate; this.
• The RC delay model treats transistors as switches in
series with resistors.
• Define a unit nMOS transistor to have effectiveresistance R. The size of the unit transistor is arbitrary
length and minimum contacted diffusion width
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E uivalent RC Models An nMOS transistor of k times unit
width has resistance R/k.
A unit MOS transistor has reater
resistance, generally in the range of 2R‐
3R, because of its lower mobility.
T e resistance at some operating point
can be defined as:
If Vds is small and the transistor is
o eratin in the linear re ion, the
resistance can be approximated
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• Viewing ON transistors as a resistors, we see that a chain of resistors can
be represented as an RC Ladder.
• The Elmore delay model estimates delay of the RC ladder as the sum over node in the ladder of the resistance Rn‐1. between that node and a supply
multiplied by the capacitance on the node
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Estimatin Rise Dela
• Each in ut is connected to 4 units of ate width. Hence
the output load of h identical NAND gates may berepresented as 4h units of capacitance.
• n y one p rans s or s n e s owes case.
• The diffusion capacitance of the nMOS transistor isi nored because it is not on the ath between the su lrail and the output node Y.
• This results in a slightly optimistic result.
• The delay istpdr = R • ((6 + 4h)C) = (6 + 4h)RC.
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Estimatin Fall Dela
• Figure 4.6(c) shows the equivalent circuit for estimating thefalling delay.
• In the worst case, inputs is already '1,' so node x is chargedup to nearly VDD through the top nMOS transistor.
• Input B rises, turning on the bottom nMOS transistor and thusdischarging both the capacitance on node x and the output
capacitance.• The Elmore delay is tpdf= (R/2)(2Q + R • ((6 + 4h)Q = (7 +
4h)RC.
• Des ite the fact that the rise and fall resistances are e ual, the
falling propagation delay is slightly longer than the risingdelay on account of the time needed to discharge the internalparasitic capacitance.
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Design CMOS
circuit
for
the
logic
F = (A
B+
C)’,
size
the
NMOS
and
PMOS devices so that the resistance is same as that of an
inverter. Calculate its rising and Falling Delay.
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Power Dissi ation
• Static CMOS ates are ver ower-efficient because the
dissipate nearly zero power while idle.• For much of the history of CMOS design, power was a
secon ary cons era on e n spee an area ormany chips.
• As transistor counts and clock fre uencies haveincreased, power consumption has skyrocketed and nowis a primary design constraint.
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Power Dissi ation
The instantaneous power P(t) drawn from the power supply is
proportional to the supply current iDD
(t) and the supply voltage VDD
The energy consumed over some time interval T is the integral of the
instantaneous power
The average power over this interval is
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Power Dissi ation
Power dissipation in CMOS circuits comes from two components:
Static dissipation due to
sub threshold conduction through OFF transistors
tunneling current through gate oxide
leaka e throu h reverse-biased diodes
Dynamic dissipation due to
charging and discharging of load capacitances "short-circuit" current while both pMOS and nMOS networks are
partially ON
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Static Dissi ation
sub threshold conduction tunnelin and
leakage lead to small amounts of static
current flowing through the OFF
transistor.
Assuming the leakage current is constant
so instantaneous and average power arethe same, the static power dissipation is
the product of total leakage current and
the supply voltage.
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Com onents of static ower dissi ation (i) Sub threshold conduction is proportional to exponential of threshold
(ii) leakage current through the gate dielectric historically was very.
(iii) small static dissipation due to reverse biased diode leakage betweendiffusion regions, wells, and the substrate, in an inverter
diode leakage is generally muchsmaller than the sub threshold or
neglected.
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D namic Dissi ation
• The primary dynamic dissipation component is charging the loadcapacitance.
• Suppose a load C is switched between GND and VDD at an averagerequency sw over any g ven n erva o me , e oa w e
charged and discharged Tfsw times.
DD .
• Current then flows from the load to GND during discharge.
• In one complete charge/discharge cycle, a total charge of
Q = CVDD is thus transferred from VDD to GND.
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Power Dissi ation
• The average dynamic power dissipation is
Taking the integral of the current over some interval T as the totalcharge delivered during that time, we simplify to
Because
most
gates
do
not
switch
every
clock
cycle,
it
is
often
more
convenient
to
express switching frequency fsw as an activity factor α times the clock frequency
f.Now the dynamic power dissipation may be rewritten as:
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Short Circuit Power Dissi ation
• The input rise/fall time is greater than zero, both nMOS and pMOS transistors
will be ON for a short period of time while the input is between Vtn and VDD -
|Vtp|.
• " "
typically increases power dissipation by about 10% .
•
Short circuit power dissipation occurs as both pullup and pull down networksare par a y w e e npu sw c es.
• It increases as edge rates become slower because both networks are ON for more
time.
• it decreases as load capacitance increases because with large loads the output
only switches a small amount during the
• in ut transition leadin to a small V across one of the transistors.
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•
be written
as
=
•
where
p
is
the
parasitic
delay
inherent
to
the
gate w en no oa s attac e ; s t e e ort
• delay or stage effort that depends on the
complexity and
fanout of
the
gate:
• f = h
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• The com lexit is re resented b the lo ical effort,[Sutherland99].
• An inverter is defined to have a logical effort of 1.,
indicating that they take longer to drive a given fan-
out.• For example, the logical effort of the NAND gate
from the previous example is 4/3. A gate driving h
electrical effort of & If the load is not identical copiesof the°gate, the electrical effort can be computed as