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Circuit Networks - Calculations (Lecture Notes, ROWAN UNIVERSITY)
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CHAPTER 8CHAPTER 8
NETWORKS 1: NETWORKS 1: 09092010909201--03/0403/0410 December 2003 –
Lecture 8b
ROWAN UNIVERSITYROWAN UNIVERSITYCollege of EngineeringCollege of Engineering
Dr Peter Mark Jansson, PP PEDr Peter Mark Jansson, PP PEDEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERINGDEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING
Autumn Semester 2003Autumn Semester 2003
adminhw 7 due today, hw 8 due at finaltest review 5.15pm thurs. at end of lablast lab 6 due by end of next week’s normal lab day (no later than 5 PM)final exam: Next Mon 15 Dec 2:45pm
Rowan Hall Auditorium
take – home portionAssignment 8 (15%)Tool Kit (10%)
networks I
Today’s learning objectives –master first order circuitsbuild knowledge of the complete responseuse Thevenin and Norton equivalents to
simplify analysis of first order circuitscalculate the natural (transient) response
and forced (steady-state) response
new concepts from ch. 8
response of first-order circuitsto a constant input
the complete responsestability of first order circuitsresponse of first-order circuits
to a nonconstant (sinusoidal) source
What does First Order mean?
circuits that contain capacitors and inductors can be defined by differential equations
circuits with ONLY ONE capacitor OR ONLY ONE inductor can be defined by a first order differential equation
such circuits are called First Order Circuits
what’s the complete response (CR)?
Complete response = transient response + steady state response
OR….
Complete response = natural response + forced response
finding the CR of 1st Ord. Cir
1) Find the forced response before the disturbance. Evaluate at t = t(0-) to determine initial conditions [v(0) or i(0)]
2) Find forced response (steady state) after the disturbance t= t(∞) [Voc or Isc ]
3) Add the natural response (Ke-t/τ) to the new forced response. Use initial conditions to calculate K
Figure 8.0-1 (p. 290) A plan for analyzing first-order circuits. (a) First, separate the energy storage element from the rest of the circuit. (b) Next, replace the circuit connected to a capacitor by its Thévenin equivalent circuit, or replace the circuit connected to an inductor by its Norton equivalent circuit.
RC and RL circuits
RC circuit complete response:
RL circuit complete response:
)/())0(()( CRtOCOC
teVvVtv −−+=
tLRSCSC
teIiIti )/())0(()( −−+=
simplifying for analysis
Using Thevenin and Norton Equivalent circuits can greatly simplify the analysis of first order circuits
We use a Thevenin with a Capacitorand a Norton with an Inductor
Thevenin Equivalent at t=0+
Rt
C+–Voc
+v(t)-
i(t)
+ -
Norton equivalent at t=0+
RtIsc
+v(t)-
L i(t)
1st ORDER CIRCUITS WITH CONSTANT INPUT
+–
t = 0
R1 R2
R3 Cvs
+v(t)-
( ) s321
3 vRRR
R0v
++=−
Example (before switch closes)
If vs = 4V, R1 = 20kohms, R2 = 20 kohmsR3 = 40 kohms
What is v(0-) ?
( ) s321
3 vRRR
R0v
++=−
as the switch closes…
THREE PERIODS emerge….. 1. system change (switch closure)2. (immediately after) capacitor or inductor
in system will store / release energy (adjust and/or oscillate) as system moves its new level of steady state (a.k.a. transient or natural response) …. WHY??? 3. new steady state is then achieved (a.k.a.
the forced response)
Thevenin Equivalent at t=0+
Rt
C+–Voc
+v(t)-
32
32t RR
RRR
+= s
32
3oc v
RRR
V+
=
KVL 0)t(vR)t(iV toc =−−+
i(t)
+ -
0)t(vdt
)t(dvCRV toc =−−+ CRV
CR)t(v
dt)t(dv
t
oc
t=+
SOLUTION OF 1st ORDER EQUATION
CRV
CR)t(v
dt)t(dv
t
oc
t=+
CR)t(v
CRV
dt)t(dv
tt
oc −= dtCR
)t(vV)t(dv
t
oc −=
dtCR
1)t(vV
)t(dv
toc=
−dt
CR1
V)t(v)t(dv
toc−=
−
DdtCR
1V)t(v)t(dv
toc+∫−=∫
−
SOLUTION CONTINUED
( ) DCR
tV)t(vlnt
oc +−=−
DdtCR
1V)t(v)t(dv
toc+∫−=∫
−
⎟⎟⎠
⎞⎜⎜⎝
⎛+−=− D
CRtexpV)t(vt
oc
( ) ⎟⎟⎠
⎞⎜⎜⎝
⎛−=−
CRtexpDexpV)t(vt
oc ( ) oct
VCR
texpDexp)t(v +⎟⎟⎠
⎞⎜⎜⎝
⎛−=
( ) oct
VCR
0expDexp)0(v +⎟⎟⎠
⎞⎜⎜⎝
⎛−= ( ) ocV)0(vDexp −=
SOLUTION CONTINUED
( ) oct
oc VCR
texpV)0(v)t(v +⎟⎟⎠
⎞⎜⎜⎝
⎛−−=
( ) ⎟⎟⎠
⎞⎜⎜⎝
⎛−−+=
CRtexpV)0(vV)t(vt
ococ
so complete response is…
complete response = v(t) =forced response (steady state) = Voc
+natural response (transient) =
(v(0-) –Voc ) * e -t/RtC) NOTE: τ
=Rt C
( ) ⎟⎟⎠
⎞⎜⎜⎝
⎛−−+=
CRtexpV)0(vV)t(vt
ococ
Figure 8.3-4 (p. 301) (a) A first-order circuit and (b) an equivalent circuit that is valid after the switch opens. (c) A plot of the complete response, v(t), given in Eq. 8.3-8.
WITH AN INDUCTOR
+–
t = 0
R1 R2
R3 Lvs
( )21
sRR
v0i
+=−
i(t)
Why ?
Norton equivalent at t=0+
RtIsc
+v(t)-
L i(t)32
32t RR
RRR
+=
2
ssc R
vI =
KCL 0)t(iR
)t(vIt
sc =−−+
0)t(idt
)t(diLR1It
sc =−−+ sctt I
LR
)t(iLR
dt)t(di
+=+
Why ?
SOLUTIONsc
tt IL
R)t(i
LR
dt)t(di
+=+CR
VCR)t(v
dt)t(dv
t
oc
t=+
CR1
LR
t
t ⇔
( ) ⎟⎟⎠
⎞⎜⎜⎝
⎛−−+=
CRtexpV)0(vV)t(vt
ococ
( ) ⎟⎠
⎞⎜⎝
⎛−−+= tLR
expI)0(iI)t(i tscsc
so complete response is…
complete response = i(t) =forced response (steady state) = Isc
+natural response (transient) =
(i(0-) –isc ) * e –t(Rt/L)) NOTE: τ
=L/Rt
( ) ⎟⎠
⎞⎜⎝
⎛−−+= tLR
expI)0(iI)t(i tscsc
Figure 8.3-5 (p. 302) (a) A first-order circuit and (b) an equivalent circuit that is valid after the switch closes. (c) A plot of the complete response, i(t), given by Eq. 8.3-9.
Figure E8.3-1 (p. 308)
Figure E8.3-2 (p. 309)
Figure E8.3-3 (p. 309)
Figure E8.3-4 (p. 309)
Figure E8.3-5 (p. 309)
Stability of 1st order circuits
when τ>0 the natural response vanishes as t ∞
THIS IS A STABLE CIRCUIT
when τ<0 the natural response grows without bound as t ∞
THIS IS AN UNSTABLE CIRCUIT
forced response summary
Forcing function y(t) (steady-state before)
Forced response xf (t)(steady-state after)
Constant y(t) = M Constant: xf (t) = N
Exponential y(t) = Me-bt
Exponential xf (t) = Ne-bt
Sinusoid y(t) = M sin (ωt + )
Sinusoid xf (t) = Asin (ωt+ ) + Bcos(ωt+ )
Unit step or pulse signal
vo (t) = A + Be-at
for t > 0
Example
8.6-2, p. 321-323
Figure 8.6-12 (p. 322) The circuit considered in Example 8.6-2
Figure 8.6-13 (p. 322) Circuits used to calculate the steady-state response (a) before t = 0 and (b) after t = 0.
HANDY CHARTELEMENT CURRENT VOLTAGE
R
C
L
RVI = RIV ∗=
dtdvCi c
c = dtiC1v
tcc ∫=
∞−
dtdiLv L
L =dtvL1i
tLL ∫=
∞−
IMPORTANT CONCEPTS FROM CHAPTER 8
determining Initial Conditionsdetermining T or N equivalent to simplifysetting up differential equationssolving for v(t) or i(t)
Don’t forget HW 8 (test review)
Thursday 5.15 pm 11 Dec after lab