Circuit Aging Tools - MOS-AK Association · What Eldo needs first is — A model which computes the instantaneous stress of the transistor subject to a given bias and temperature

Circuit Aging Tools Reliability Verification In ELDO

Mohamed Selim

2 www.mentor.com© Mentor Graphics Corp.

Agenda

MS, MOS-AK Q4 2015.

Reliability Analysis

� Overview

� Challenges

� Degradation Mechanisms

� Aging Analysis

� Statistical Aging

� Joint Design

Conclusion


Agenda

MS, MOS-AK Q4 2015.


� Overview

� Challenges


� Aging Analysis


� Joint Design

Conclusion


Reliability

YieldQuality

Electronic Components are Everywhere …

ThermalAnalysis

Transient

Noise

Process

Variation

Leakage

Current

NBTI

HCI, TDDB

MS, MOS-AK Q4 2015.


Increasing Need for Statistical SimulationsWill I still meet time-to-market?

� As technology continues to advance, process variations continue to increase

� What you design may not be not what you get

� With advanced processes, number of corners increases making the simulation time an impediment to meeting time-to-market

� Statistical (Monte Carlo) simulations are mandatory to guarantee acceptable design yields

F

Intel 45nm

Process

MS, MOS-AK Q4 2015.



Aging Reliability: Industry Wide Issue

Reliability is a growing issue when moving through 90nm to smaller geometries

Nightmare: Growing risk of IC failing at the customer

MOS dielectrics average only 3 molecules thick at 65/45nm!

32nm

Process Technology

130nm 90nm 65nm 45nm

Time (years)

15

30

5

2

10

Military, Aerospace, Automotive

Consumer

Computing, Wireless

MS, MOS-AK Q4 2015.


Agenda

MS, MOS-AK Q4 2015.


� Overview

� Challenges


� Aging Analysis


� Joint Design

Conclusion


Reliability Bathtub Curve

� Infant Mortality

— All manufactured devices are subjected to elevated operating conditions for a short time to induce accelerated stress. Thus the devices that fail are thrown away. This is done by the so called burn-in testing process.

— Decrease in yield but it avoids failure in field during the promised operating life.

� Normal Operating Life

— During this time, devices incur stress and do degrade but still work within their performance specifications.

— Failure rate is low and remains fairly constant

� Wear Out

— This is the final phase of a device lifetime where the device has already been sufficiently

aged and deteriorated that the manufacturer cannot further guarantee its successful operation.

— By time, failure rate increases as more and more devices fail due to aging deterioration.

2[Alain Bravaix 2010]1[Wikipedia 2009]

[1]

[2]

[Neil H. E. Weste 2005] [Aamir Khan 2009]

MS, MOS-AK Q4 2015.


Is Reliability Challenge Increasing?

ITRS Roadmap defines the challenges for reliability:

1. Increased scaling

2. Introduction of new materials and devices

3. More demanding mission profiles

— Higher temperatures (Automotive sensors operating at very high temp)

— Extreme lifetimes (as for base stations and solar cells)

— High currents

4. Increasing constraints of time and money

— Speed of introduction of new materials and devices requires fast learning of new failure

mechanisms and physics

[ITRS Roadmap 2013]

MS, MOS-AK Q4 2015.


ITRS 2013 Roadmap “RELIABILITY”

The most effective way to meet requirements is to have

complete built-in-reliability and design-for-reliability solutions

available at the start of the development of each new technology

generation. This would enable finding the optimum

reliability/performance/power choice and would enable designing

a manufacturing process that can consistently have adequate

reliability.

Unfortunately, there are serious gaps in these capabilities today

and these gaps are likely to grow even larger in the future.

The penalty will be an increasing risk of reliability problems and

a reduced ability to push performance, cost and time-to-market.

MS, MOS-AK Q4 2015.


Agenda

MS, MOS-AK Q4 2015.


� Overview

� Challenges


� Aging Analysis


� Joint Design

Conclusion


Reliability Degradation Mechanisms

Historical View

MS, MOS-AK Q4 2015.

Time-Dependent Dielectric Breakdown (TDDB)Muhammad A. Alam , 2013


HCI Overview

HCI is the phenomenon that carriers at MOSFET’s

drain end gain sufficient energy to inject into the gate

oxide and cause degradation of some device

parameters such as channel mobility, threshold

voltage, sub-threshold slope,

transconductance, and drain saturation and

linear current.

Source: http://www.iue.tuwien.ac.at/phd/entner/node21.html1[Alain Bravaix, 2010]

[1]

[1]

MS, MOS-AK Q4 2015.


NBTI Overview

Vdd

S

G

-Vdd

VG = 0

Stress StressRelaxation

VG = Vdd

Substrate

Si H

Si H

PolyOxide

Si H

Si H

Dangling Bonds

The interface states generation rate is function of the bias, temperature and time.

Substrate

Si H

Si H

PolyOxide

Si

H

Si H

Interface Traps

PMOS Vth versus time for a 65nm PMOS transistor 1

� 25-30% degradation in PMOS Vth— Effect increases with technology scaling

� Around 10% delay degradation

� Effect worsens if High-k materials are used

1[Sanjay Kumar 06]

MS, MOS-AK Q4 2015.


Gate Oxide Breakdown

� Traps start to form in the Gate Oxide originally the traps:

— Non-overlaping

— Don’t conduct

� As more and more traps are created

— Start to overlap

— Conduction path is created

� Once this conduction path is created we have Soft Breakdown (SBD)

� Conduction leads to heat

— Heat leads to thermal damage

— Thermal Damage leads to Traps

— More Traps leads to more conduction

� Silicon in the breakdown spots melts

— Oxygen is released

— Silicon Filament is formed from Gate to Substrate (Hard Breakdown)

MS, MOS-AK Q4 2015.


Agenda

MS, MOS-AK Q4 2015.


� Overview

� Challenges


� Aging Analysis


� Joint Design

Conclusion


Reliability Analysis in Eldo

� Advanced technology exists to simulate any modeled stress effect e.g. HCI, NBTI and TDDB effects

� Benefits

— Accurate & efficient

— Avoids Over-Design

— Supports Mixed Signal and RF

— Supports Statistical Aging

— Supports Aging Sensitivity

— Supports specialty processes

— Protects Intellectual Property

— Supports passive devices

— Analog and Digital design

Lifetime Prediction is a MUST, not an Option …

MS, MOS-AK Q4 2015.


Reliability in Digital Domain

� Timing information is represented in the Analog domain in the form of an extracted RC circuit

� Timing information is represented in the Digital domain in the form of characterized models using Liberty format or HDL (Verilog with generate statements or VHDL with VITAL)

— Aging information can be added an extension to Liberty format

— Cell Characterization can handle aging as additional corners

— However, this extension in the Liberty format has to be endorsed by the industry to be standardized

� Digital representation of aging parameters will allow Digital verification to include reliability analysis

— To be used in OVM/UVM

MS, MOS-AK Q4 2015.


Reliability in Analog Domain

� Eldo supports flexible Reliability Analysis, UDRM (user-defined reliability models)

� Models reliability issues due to aging:

— Hot Carrier Injection

— Negative Bias Temperature Instability

— Possibly any other stress effects

� What does the analysis provide?

— Allows comparing behaviors of:

– The ‘fresh’ circuit, just out of the fab

– The ‘aged’ circuit, i.e. the same circuit after N years of operation, under arbitrary periodic conditions

— Designer can thus predict the life-time of his circuit

MS, MOS-AK Q4 2015.


Verification Flow Incorporating Reliability

MS, MOS-AK Q4 2015.


Flow Description – Stress

� What Eldo needs first is

— A model which computes the instantaneous stress of the transistor subject to a given bias and temperature

— While running a normal simulation, Eldo calls this stress model to compute and integrate this stress, for each device

— Each device sees a different bias, and thus accumulates a different stress, a priori

� Total accumulated stress after Y years is computed by linear extrapolation:

— �� = �� ×�

��

� Then Eldo uses another set of equations which model the way ‘fresh’ .MODEL parameters (VTH, U0…) are modified into ‘aged’ ones by this accumulated stress (.MODEL parameters are updated)

� A new ‘aged’ simulation is run using these updated .MODEL parameters

MS, MOS-AK Q4 2015.


Stress model, Update model

� HCI stress models

— Accurate models are proprietary

— Public models have simple form

� HCI update models

— Different types of updating laws are commonly used (Linear, Saturated)

� NBTI stress models

— Accurate models are proprietary

— Public models have simple form

� NBTI update models

— Typical update formula for VTH0

m and H are parameters of the stress model

MS, MOS-AK Q4 2015.


Refined Iterative Flow

� Two flows are available:

1. Two-steps Quick Flow

– Fresh simulation

– Update

– Aged Simulation

2. N-steps Flow

– Fresh simulation

– [��, ��]×�

– More accurate

– N times slower

MS, MOS-AK Q4 2015.


Agenda

MS, MOS-AK Q4 2015.


� Overview

� Challenges


� Aging Analysis


� Joint Design

Conclusion


Statistical Aging

� Aging appears to be a statistical process unto itself

� Two identical devices drawn side-by-side, they will have slightly different (fresh) threshold voltages, drive current, and leakage currents → Same is true

for their aging characteristics

� Two identical devices with identical bias conditions do not age exactly in the same way

— Vth shift, propagation time and distortion level

— Required measurements are complicated, lengthy and costly

MS, MOS-AK Q4 2015.

Spread of aged transistor parameters are reflected onto measured performances such as a propagation time


Monte Carlo – Devices

� UDRM Extensions

— Monte Carlo on aging parameters

– Support BSIM3/4SOI, PSP, HiSIM models

— Degradation summary table

– Includes sorted ∆��, ∆��, ∆��, etc.

– Enhanced API can read sub-circuit pin voltages

– Local parameters can be updated with age

MS, MOS-AK Q4 2015.


Aging Sensitivity Analysis

� Sensitivity analysis provides insights about which aging devices have the most impact on the outputs

— Some devices may suffer from aging, but their degradation has no or little impact upon the performance of the circuit

— Some devices may exhibit seemingly minor aging degradation, but this has a dramatic impact upon the outputs

— Naïve Aging analysis does not say anything about this question…

— Aging Sensitivity analysis tells the user what is important, and what is less important

— It is complex, but flexible, supporting absolute/normalized stress modes, device coupling, output specifications, sorting, etc.

MS, MOS-AK Q4 2015.


RF & Passive elements

� Reliability analysis in RF context

— Support of reliability analysis with Harmonic Balance Steady-State

— Aging assumes periodic operation of the circuit

� Passive elements are prone to aging due to high voltage stress

� New challenges with power applications where resistors and capacitor degradations are becoming critical issues.

� Resistors instability due to aging has become mandatory.

� This proves very valuable for accurate electrothermal simulation to account for both electrical and thermal aging.

MS, MOS-AK Q4 2015.


Agenda

MS, MOS-AK Q4 2015.


� Overview

� Challenges


� Aging Analysis


� Joint Design

Conclusion


Joint DesignReliability Flows and Advanced Models Address IC-Reliability Issues

� Benefit:

— Allow designer to predict behavior of circuit versus “wall-clock” time

� Next:

— Which device is primarily responsible for the degradation?

MS, MOS-AK Q4 2015.

Operating frequency of a CMOS oscillator degrades over time

Results are sorted by decreasing “delta-Vth.”

Devices that have theirthreshold voltage degraded the most severely are presented first


Joint Design – Example A-ZReliability Flows and Advanced Models Address IC-Reliability Issues

� Alagi et al. describe the full process of modeling and simulation using Eldo UDRM.

� A Zero crossing detector comparator (ZCDC) example is used to demonstrate the aging effect.

� Special attention was given to simulation of the recovery effect which is important to avoid overdesign.

MS, MOS-AK Q4 2015.

[Alagi et al. (ESSDERC). 2014]


Agenda

MS, MOS-AK Q4 2015.


� Overview

� Challenges


� Aging Analysis


� Joint Design

Conclusion


Conclusion

� Reliability effects such as HCI , NBTI and TDDB are real threats with advanced process nodes

— Joint design–reliability flows, can mitigate their effects allowing designers to take them into account as early as possible

— This also helps to avoid overdesign that would normally be done to protect the design against these effects

� IP protection

— Details of the equations and models used to predict degradation are not considered public information

— Eldo has developed encryption mechanisms allowing full information protection

� Importance of flexible model definitions

— Modeling of these aging effects is under constant investigation and “reshaping”

— Black-box models provided in some solutions are not good enough for addressing this need

— Eldo gives the user a fully customizable and robust solution.

� This solution can be used with any type of analysis: AC, DC, Transient, RF, statistics, sensitivity and mixed signal simulations.

MS, MOS-AK Q4 2015.


w w w . m e n t o r . c o m

MS, MOS-AK Q4 2015.

Documents

Circuit Aging Tools - MOS-AK Association · What Eldo needs first is — A model which computes the instantaneous stress of the transistor subject to a given bias and temperature