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ELECTRIC FIELD EMISSIONS OF FPGA CHIP
BASED ON GIGAHERTZ TRANSVERSE
ELECTROMAGNETIC CELL MODELING AND
MEASUREMENT
CHUA KING LEE
UNIVERSITI TUN HUSSEIN ONN MALAYSIA
This thesis has been examined on 15th
September 2015 and is sufficient in fulfilling
the scope and quality for the purpose of awarding Doctoral.
Chairperson:
Professor Hj Ayob Bin Johari
Faculty of Electrical and Electronic Engineering
Universiti Tun Hussein Onn Malaysia
Examiners:
Professor Dr. Mohamad Kamal Bin A Rahim
Faculty of Communications Engineering
Universiti Teknologi Malaysia
Dr Zuhairiah Bte Zainal Abidin
Faculty of Electrical and Electronic Engineering
Universiti Tun Hussein Onn Malaysia
ELECTRIC FIELD EMISSIONS OF FPGA CHIP BASED ON
GIGAHERTZ TRANSVERSE ELECTROMAGNETIC CELL
MODELING AND MEASUREMENTS
CHUA KING LEE
A thesis submitted in
fulfillment of the requirement for the award of the
Doctoral of Electrical and Electronic Engineering
Faculty of Electrical and Electronic Engineering
Universiti Tun Hussein Onn Malaysia
JANUARY, 2016
iii
DEDICATION
To my beloved mother and family.
iv
ACKNOWLEDGEMENT
In this thesis, I would like to take this opportunity to express my deepest graditude to
everyone who supported me throughout the journey of PhD study. This thesis would
not be completed without the guidance and support from them.
Foremost, I would like to express my sincere gratitude to my supervisor, Professor
Dr. Mohammad Zarar bin Mohamed Jenu, who has supported me with his patience,
inspiring and invaluable guidances as well as friendly advices during my PhD study.
His guidance and encouragement assisted me to overcome many issues and obstacles
related to the research activities.
Besides, I would like to thank, Professor Dr. James L. Drewniak for giving an
internship opportunity at Missouri University of Science and Technology EMC
Laboratory, Rolla, Missouri, United States. The intensive training allowed me to gain
experiences and exposure on the latest technology for the integrated circuit field
measurement techniques and to learn practical issues which are beyond the scope of
the textbooks. Special thanks are addressed to Dr. David Pommerenke, Dr. Jun Fan
and Dr. Zhang Yao Jiang, who provided technical advice and insight comments
throughout my work to evaluate electromagnetic radiation of integrated circuit and
emission modelling along the period of the intensive training at their laboratory.
My sincere thanks also goes to Department of Higher Education, Universiti Tun
Hussien Onn Malaysia and Multimedia Development Corporation (MDeC) for
providing financial support to undertake my doctorate programme. I also would like
to thank Mr Wong Man Onn, Mr Fong Chee Siong and Mr. Ying See Hour from
Altera Corporation (M) Sdn. Bhd. for providing FPGA test board, intensive training
and technical support on using the Altera Quartus II software and the test board.
Many thanks to my friendly and cheerful group of friends Professor Jing Shen
Hui, Professor Gui Liang Qi, Associate Professor Gou Xiang, Ms. Li Jing, Ms. Pan
v
Jing Nan, Mr. Jackie Ngu and Ms. Ng Ping Ping, whose always willing to help and
give their best suggestions in my daily work. I also would like to thank workers in
the laboratory, Mr. Sharifunazri bin Johari@Johadi, Mr. Mahmod bin Munajat, and
Mr. M. Nazeri bin Sarmijan for assisting me to prepare experimental samples and
measurement setup for the investigation.
Last but not the least, I would like to express my greatest appreciation to my
mother, madam Ling Kui Ing for her endurance, sacrification and unconditional love
for raising me on her own. I also would like to thank my siblings, they always
supporting me and encouraging me with their best wishes. Finally, with great sadness
and sorrow, I would like to dedicate my greatest bleesing to my elder brother, Mr
Chua Siew Yiing who has passed away on October 2014. May Almighty God
receives his soul with His Love and Mercy.
vi
ABSTRACT
Modern integrated circuits (ICs) are significant sources of undesired
electromagnetic wave. Therefore, characterization of chip-level emission is essential
to comply with EMC tests at the product level. A Gigahertz Transverse
Electromagnetic (GTEM) cell is a common test instrument used to measure IC
radiated emission and the test cost is relatively low. Regular IC radiated emission
measurements using GTEM tend to neglect some significant emission sources. Thus,
this research proposed an alternative methodology to perform field measurement of
the IC inside the GTEM cell in order to optimize the field measurements. This
research study also attempted analysis of the overall GTEM cell performance using
transmission line theory. An FPGA chip was adopted as the IC under test because of
its flexibility in configuration to any digital circuit. The investigations discovered
that the impact of the FPGA board supporting components and interconnection
cables can be significantly reduced with appropriate shielding and grounding. The
electric field predict a far distance from the FPGA chip was carried out based on the
dipole moment technique. In particular, the dipole moment model emphasizing the
tiny horizontal and vertical radiation elements inside the FPGA chip as Hertzian
antenna and small current loop. Equations to predict the horizontal and vertical
electric field were developed based on Hertzian antenna and small current loop
which relate the tiny radiation sources to electric and magnetic dipole moments. The
prediction was validated with 3-meter field measurements in a semi-anechoic
chamber. On top of that, a spiral-like pattern was developed to obtain a correction
factor for further improvement of the correlation between prediction and SAC
measurement. The results revealed that the correction factor effectively reduced the
gap between the prediction and measurement fields and boosted the correlation
coefficient by 44%. The difference of peak values also has limited to less than 10dB
after correction. These results suggest a promising finding for a future EMI test of
ICs with a cheaper GTEM cell.
vii
ABSTRAK
Litar bersepadu (IC) moden adalah sumber penting menyumbang kepada
gelombang electromagnet yang tidak diingini. Oleh sebab ini, penyifatan
pengeluaran peringkat cip adalah penting untuk mematuhi ujian EMC di peringkat
produk. Sel elektromagnetik melintang gigahertz (GTEM) ialah satu alatan yang
biasa digunakan untuk mengukur medan IC yang telah dipancarkan dan kos ujian
adalah agak murah. Satu ujian mengukur pancaran medan IC biasa yang dilakukan
dengan mengapit papan ujian IC di dinding sel GTEM, yang hamper mengabaikan
beberapa sumber pengeluaran penting. Oleh itu, kajian ini telah mencadangkan satu
keadah alternatif untuk melaksanakan pengukuran medan IC di dalam sel GTEM
untuk mengoptimakan pengukuran medan. Kajian manganalisa prestasi keseluruhan
sel GTEM menggunakan teori talian penghantaran. Cip FPGA telah dipilih sebagai
peranti dalam ujian kerana ia fleksibe ditatarajah dengan sebarang litar berdigit.
Penyiasatan menemui bahawa kesan komponen sokongan papan FPGA dan kabel
saling sambung boleh dikurangkan melalui perisaian dan pembumian yang sesuai.
Sinaran medan elektrik sepadan pada jarak jauh cip FPGA diramal berasaskan teknik
momen dwikutub. Khususnya, model momen dwikutub mewakili sumber pancaran
cip yang kecil mendatar dan menegak sebagai antena Hertzian dan gelung arus kecil.
Persamaan untuk meramal medan elektrik mendatar dan menegak diterbit daripada
antena Hertzian dan gelung arus kecil, dimana sumber pancaran ruas kecil dikaitkan
dengan momen dwikutub elektrik dan magnetik. Ramalan ini telah disahkan
menggunakan ukuran SAC 3 meter. Untuk penambahbaikan, satu corak pusaran
dibentukkan untuk membangun satu faktor pembetulan bagi tujuan meningkatkan
lolerasi antara ramalan dan ukuran SAC. Keputusan mendedahkan bahawa faktor
pembetulan adalah berkesan untuk mengurangkan jarak antara medan ramalan dan
ukuran dan meningkatkan pekali kolerasi sebanyak 44%. Perbezaan dalam nilai-nilai
puncak selepas pembetulan juga telah diambil kira bawah 10dB. Hasil keputusan ini
mencadangkan satu pencarian yang menjanjikan satu ujian EMI IC masa hadapan
dengan sel GTEM yang lebih murah.
viii
TABLE OF CONTENTS
DEDICATION ........................................................................................................... iii
ACKNOWLEDGEMENT ........................................................................................ iv
ABSTRACT ............................................................................................................. vi
ABSTRAK ............................................................................................................ vii
TABLE OF CONTENTS ........................................................................................ viii
LIST OF TABLES .................................................................................................... xi
LIST OF FIGURES ................................................................................................. xii
LIST OF SYMBOL ................................................................................................ xvii
LIST OF ABBREVIATION ................................................................................... xix
LIST OF APPENDICES ........................................................................................ xxi
CHAPTER 1 INTRODUCTION ................................................................................. 1
1.1 General .......................................................................................... 1
1.2 Problem Statements ...................................................................... 3
1.3 Objectives of the Research ............................................................ 4
1.4 Scopes of the Research ................................................................. 5
1.5 Aim of the Research ...................................................................... 6
1.6 Significance of the Research ......................................................... 6
1.7 Outline of the Thesis ..................................................................... 7
CHAPTER 2 LITERATURE REVIEW ...................................................................... 9
2.1 Background ................................................................................... 9
2.2 Development of Digital Logic Technology ................................ 10
2.2.1 Integrated Circuit Technology ...................................... 10
2.2.2 Field-Programmable Gate Arrays ................................. 12
2.2.3 FPGA Process Technology ........................................... 13
2.3 A Brief Historical Prespective of IC EMI Research ................... 14
2.4 Justification of The Research Gap .............................................. 16
2.5 Mechanism of Chip Emission ..................................................... 20
ix
2.5.1 How Integrated Circuit Generates Disturbances ........... 22
2.6 GTEM Cell for Emission Measurements .................................... 24
2.6.1 GTEM Cell Concept...................................................... 25
2.6.2 IC EMC Testing Standard ............................................. 26
2.6.3 IC Test Board Layout .................................................... 27
2.6.4 Application of GTEM for Emission Measurements ..... 28
2.7 IC Modeling ................................................................................ 30
2.8 Summary ..................................................................................... 32
CHAPTER 3 RESEARCH METHODOLOGY AND CALIBRATION ................... 34
3.1 Introduction ................................................................................. 34
3.2 Development Process .................................................................. 34
3.3 The Proposed GTEM Measurement Setup ................................. 39
3.3.1 FPGA Test Board .......................................................... 39
3.3.2 Logic Circuit Design and Implementation .................... 40
3.3.3 Shielding of Test Board................................................. 42
3.3.4 Grounding of the Enclosure .......................................... 48
3.3.5 Radiated Emission Measurement in GTEM Cell .......... 48
3.4 Calibration of GTEM Cell Parameters ....................................... 50
3.4.1 Characteristic Impedance .............................................. 50
3.4.2 VSWR ........................................................................... 52
3.4.3 Return Loss ................................................................... 53
3.4.4 Analyze Impact of Impedance Mismatch Using
Transmission Line Theory ............................................ 54
3.5 Using Comb Generator for GTEM Cell Calibration ................... 57
3.5.1 Conducted Signal Measurement.................................... 58
3.5.2 Radiated Signal Measurement ....................................... 59
3.6 Semi Anechoic Chamber Measurement ...................................... 62
3.7 Summary ..................................................................................... 64
CHAPTER 4 MODELING THE FPGA CHIP WITH DIPOLE MOMENT
TECHNIQUE ..................................................................................... 65
4.1 Introduction ................................................................................. 65
4.2 Concept of Dipole Moment Technique ....................................... 65
4.3 Multipole Model of Measured Voltage at GTEM Port ............... 66
4.4 Electric Fields Prediction Using Dipole Moments ..................... 73
x
4.5 Summary ..................................................................................... 80
CHAPTER 5 ELECTRIC FIELDS MEASUREMENTS AND PREDICTIONS ..... 81
5.1 Introduction ................................................................................. 81
5.2 The Relation between Electric Field Intensity and Voltage ....... 81
5.2.1 Measurement Approach ................................................ 82
5.2.2 Analytical Formulation ................................................. 85
5.3 GTEM Cell Response with Different Positioning of Test Device ..
..................................................................................................... 87
5.4 Ambient Noise in GTEM Cell .................................................... 92
5.4.1 Grounding of The Enclosure ......................................... 94
5.4.2 Suppression with Ferromagnetic Material .................... 99
5.4.3 High Quality Interconnection Cable ........................... 102
5.5 The TFF Pattern for FPGA Configuration ................................ 105
5.6 Orientations of Test Device in Fields Measurements ............... 109
5.7 Semi Anechoic Chamber Validation ........................................ 115
5.8 Improve Correlation by a Correction Factor ............................. 117
5.8.1 Representation of IC with a Spiral Pattern .................. 118
5.8.2 Evaluation of Spiral-like Equivalent Circuit ............... 119
5.8.3 Field Adjustment by Using Correction Factor ............ 121
5.9 Summary ................................................................................... 126
CHAPTER 6 CONCLUSIONS AND RECOMMENDATIONS ............................ 127
6.1 Introduction ............................................................................... 127
6.2 Conclusions ............................................................................... 127
6.3 Contribution of The Research ................................................... 129
6.4 Recommendations for Future Works ........................................ 130
REFERENCES ....................................................................................................... 132
APPENDIX A : Altera EMI Test Board .................................................................. 142
APPENDIX B .......................................................................................................... 151
APPENDIX C .......................................................................................................... 153
APPENDIX D .......................................................................................................... 155
APPENDIX E .......................................................................................................... 161
APPENDIX F : Comb Generator CGO-520 ............................................................ 166
APPENDIX G : Bias Network 11590B ................................................................... 168
xi
LIST OF TABLES
Table 2.1 : International guidelines for ICs EMC characterization and modelling .. 16
Table 2.2 : Existing research works that relavent to the scope in the research ......... 17
Table 2.3 : Standards for EMC emission measurement of IC ................................... 27
Table 2.4 : Current techniques used to create IC emission model ............................ 30
Table 3.1 : Comparison correlation coefficient before and after considering 𝑽𝒊 ...... 57
Table 4.1 : Coordinate and magnitude for the vector path 𝒓𝟏 and 𝒓𝟐 ....................... 78
Table 5.1 : Specifications of two coaxial cables selected for connecting the cell and
spectrum analyzer .................................................................................. 104
Table 5.2 : Guidelines to interprete Pearson’s correlation coefficient .................... 123
Table 5.3 : Correlation coefficient of predicted and measured fields ..................... 123
Table 5.4 : Variation ranges for the box plot in Figure 5.36 ................................... 126
xii
LIST OF FIGURES
FIGURE TITLE PAGE
Figure 2.1 : Cost and time saving benefits ................................................................ 10
Figure 2.2 : Digital logic technologies [16, 17] ........................................................ 11
Figure 2.3 : Technology trade-off [16] ..................................................................... 12
Figure 2.4 : FPGA block structure [16, 17] .............................................................. 13
Figure 2.5 : FPGA process technologies [18] ........................................................... 13
Figure 2.6 : Intentions for the Altera high-end Stratix product [18] ......................... 14
Figure 2.7 : Milestone for EMI research focusing on ICs ........................................ 15
Figure 2.8 : Mechanism of emissions due to current flowing during switching [28] 21
Figure 2.9 : Strong di/dt generation with technology scale down [28] ..................... 22
Figure 2.10 : Paths for ICs to generate disturbances [19] ......................................... 23
Figure 2.11 : Mechanism of direct electric field emission ........................................ 23
Figure 2.12 : Mechanism for direct magnetic field emission ................................... 24
Figure 2.13 : (a) GTEM cell, (b) Cell cross-section [28] .......................................... 25
Figure 2.14 : (a) TEM wave, (b) GTEM field distribution ....................................... 26
Figure 2.15 : IC test board; (a) Top view; (b) Side view [8] ................................... 28
Figure 2.16 : GTEM cell measurement setup [28].................................................... 29
Figure 3.1 : Flow chart for the research methodology .............................................. 35
Figure 3.2 : FPGA test board (a) top side, (b) bottom side ....................................... 39
Figure 3.3 : FPGA test board connection .................................................................. 40
Figure 3.4 : Process of TFF circuit ........................................................................... 41
Figure 3.5 : Flow chart to develop TFF circuit ......................................................... 41
Figure 3.6 : Testing TFF circuit using built-in in-system sources and probe editor . 42
Figure 3.7 : Geometry of an enclosure ...................................................................... 43
Figure 3.8 : Cut-off frequencies of metallic enclosure ............................................. 44
xiii
Figure 3.9 : Reflection and attenuation within a shield ............................................ 45
Figure 3.10 : Apertures built for interconnection ..................................................... 46
Figure 3.11 : Shielding the space using gaskets; (a) Structure of gasket;
(b) Placement of gasket between metallic enclosure and test board .. 46
Figure 3.12 : Actual setup of the test device; (a) The FPGA chip is bounded with
conductive gasket; (b) Setup of the test board in the enclosure; and
(c) Complete setup for emission test .................................................. 47
Figure 3.13 : Radiated emission measurement setup in GTEM cell, (a) Illustration of
EUT setup in GTEM cell, (b) Actual setup of EUT in GTEM cell .... 49
Figure 3.14 : Measuring setup of network analyzer .................................................. 51
Figure 3.15 : Characteristic impedance versus frequency ........................................ 51
Figure 3.16 : VSWR versus frequency ..................................................................... 53
Figure 3.17 : The return loss of GTEM cell .............................................................. 54
Figure 3.18 : Representation of radiated emissions measurement, (a) GTEM cell
setup, (b) Equivalent circuit of the GTEM cell .................................. 55
Figure 3.19 : Comb Generator CGO-520 ................................................................. 57
Figure 3.20 : Conducted reference signal for CGO-520, (a) Setup for measurement,
(b) Corresponding result of the measurement setup ........................... 59
Figure 3.21 : Measurement radiated reference signal of Comb Generator; (a) general
setup concept; (b) placement of Comb Generator inside the GTEM
cell; (c) measurement the radiated reference signal using spectrum
analyzer............................................................................................... 60
Figure 3.22 : Radiated reference signals ................................................................... 61
Figure 3.23 : The radiated emission system of SAC which available at research
center for applied electromagnetics; (a) Typical SAC setup for 3m
field measurement; (b) Actual setup in SAC for 3m field
measurement; (c) The control system for SAC measurement ............ 64
Figure 4.1 : GTEM cell ............................................................................................. 66
Figure 4.2 : GTEM versus EUT coordinate systems ................................................ 69
Figure 4.3 : A Hertzian dipole .................................................................................. 73
Figure 4.4 : A small current loop .............................................................................. 74
Figure 4.5 : Real and image sources of image theory ............................................... 78
Figure 5.1 : Electric field distribution of two parallel plates .................................... 82
Figure 5.2 : Radiated electric field measurement using E-field probe...................... 83
xiv
Figure 5.3 : HI-6005 isotropic electric field probe ................................................... 83
Figure 5.4 : E-field plot against voltage (a) Normal plot, (b) log scale plot ............. 84
Figure 5.5 : Calculate electric field intensity for the incline septum plate ............... 86
Figure 5.6 : Comparison field strength of measurement and approximation for
frequency 200MHz; (a) Normal scale plot; (b) Log scale plot ............. 86
Figure 5.7 : Test circuit ............................................................................................. 88
Figure 5.8 : Top view for the orientations of test circuit at horizontal position ...... 88
Figure 5.9 : Actual setup of test circuit in horizontal position, orientation O1 ........ 89
Figure 5.10 : Side view for the orientations of test circuit at vertical position ......... 89
Figure 5.11 : Actual setup of test circuit in vertical position, orientation O1 ........... 89
Figure 5.12 : Radiated emissions of the simple test circuit in various positions and
orientations; (a) horizontal position; (b) vertical position .................. 90
Figure 5.13 : Illustration of the fields for two microstrip traces ............................... 91
Figure 5.14 : Noise floor of empty GTEM cell......................................................... 93
Figure 5.15 : Comparison of noise level after setup EUT in GTEM cell ................. 93
Figure 5.16 : Minimizing the enclosure effect by using ground straps; (a) different
types of ground straps selected, (b) grounding using copper tape, (c)
grounding with wire Setup for analyzing grounding path on emission
measurement ....................................................................................... 95
Figure 5.17 : Comparison noise floor in a GTEM cell by grounding the EUT with
different ground straps: (a) before activating the DUT and (b) after
activating the DUT ............................................................................. 96
Figure 5.18 : Grounding at P1 and P2 using copper tape .......................................... 97
Figure 5.19 : Comparison copper tape grounding at different locations; (a) before
powering the DUT, (b) after activating the DUT ............................... 98
Figure 5.20 : Equivalent circuit model for a ferrite .................................................. 99
Figure 5.21 : Reducing the effect of cables (a) using ferrite beads, (b) bundling all
the cables using conductive woven, and (c) wrapping the cable with a
flexible ferrite sheet .......................................................................... 100
Figure 5.22 : Measurement results corresponding to the cable setup in Figure 5.8,
(a) ambient noise level, (b) radiated emissions captured after
triggering the DUT with 100 MHz ................................................... 101
Figure 5.23 : Noise evaluation of empty cell, (a) Cell configuration, (b) Noise level
measured ........................................................................................... 102
xv
Figure 5.24 : Configuration cable RG213 ............................................................... 103
Figure 5.25 : Sucoflex coaxial cable structure ........................................................ 104
Figure 5.26 : Removing GSM signal using double shielded cable ......................... 105
Figure 5.27 : TFF pattern to configure the FPGA chip ........................................... 106
Figure 5.28 : Usage of biased RF sinusoidal signal, at 100 MHz frequency to
exercise FPGA chip; (a) The setup to create biased RF signal using the
bias network; (b) The measurement of the biased RF signal and output
of TFF pattern using oscilloscope .................................................... 106
Figure 5.29 : TFF pattern after adding tri-state buffer ............................................ 107
Figure 5.30 : Comparison on the radiated emission measured of enabled and
disabled buffer gate; (a) Horizontal position; (b) Vertical position . 108
Figure 5.31 : IC current loops ................................................................................. 109
Figure 5.32 : Actual setup of EUT inside GTEM cell; (a) horizontal position;
(b) vertical position........................................................................... 110
Figure 5.33 : Orientation of FPGA test device in x-axis; (a) 0o; (b) +45
o; and (c) -45
o
.......................................................................................................... 111
Figure 5.34 : Orientation of FPGA test device in y-axis; (a) 0o, (b) -45
o; and (c) +45
o
.......................................................................................................... 112
Figure 5.35 : Orientation of FPGA test device in z-axis; (a) 0o; (b) -45
o; and (c) +45
o
.......................................................................................................... 113
Figure 5.36 : Peak voltages correspond to the FPGA radiation in three orthogonal
positions; (a) 0 degree; (b) +45 degree; (c) -45 degree .................... 114
Figure 5.37 : Radiated emissions measurement setup in SAC ............................... 115
Figure 5.38 : Changing receiving antenna position to account neglected horizontal
components; (a) typical antenna setup, 𝐻1; (b) additional antenna
setup for SAC measurement, 𝐻2 ...................................................... 116
Figure 5.39 : Estimated radiated emission from FPGA chip in GTEM cell as
compared to SAC measurement; (a) horizontal electric field
component and (b) vertical electric field component ....................... 117
Figure 5.40 : Proposed circuitry representative of standard IC for deriving a
correction factor. (a) Schematic diagram of test circuitry, (b) Top view,
(c) Bottom view. ............................................................................... 118
Figure 5.41 : Radiated electric field test in SAC, (a) SAC measurement parameters;
(b) Actual setup for equivalent SAC measurement .......................... 120
xvi
Figure 5.42 : Comparison of GTEM estimated fields and SAC measured fields
before and after adjustment by using the correction factor. (a)
Horizontal component of radiated electric field, (b) Vertical
component of radiated electric field. ................................................ 122
Figure 5.43 : The box plot. ...................................................................................... 124
Figure 5.44 : The difference between GTEM prediction and SAC measurement
before and after taking correction factor into account; (a) horizontal
component; (b) vertical component. ................................................. 125
xvii
LIST OF SYMBOL
Symbol Description Unit
E Electric Field Intensity V/m
H Magnetic Field Intensity A/m
Z Wave Impedance Ω
𝑍0 Characteristic Impedance Ω
𝑍𝐿 Load Impedance Ω
𝑍𝑆 Source Impedance Ω
RL Return Loss dB
𝑃𝑟 Reflected Power W
𝑃𝑖 Incident Power W
𝑓𝑟 Resonant Frequency Hz
δ Skin Depth m
σ Conductivity S/m
Relative Permeability H/m
0 Relative Permeability of Free-Space, 𝜇0 = 4𝜋 × 10−7 H/m
r Relative Permeability of Material (dimensionless)
Reflection Coefficient (dimensionless)
𝜃𝑟 Phase Angle degree (o)
Phase Constant rad/m
c Speed of Light in Vacuum cm/s
V Voltage V
VL Load voltage V
Vi Input voltage V
F Electric Force N
q Electric Charge C
W Work J
𝐼 𝐷 Differential-mode Current A
xviii
Symbol Description Unit
L Inductance H
C Capacitance F
𝑬 Electric Field Vector V/m
𝑯 Magnetic Field Vector A/m
𝑎𝑛 Forward Excitation Coefficient (dimensionless)
𝑏𝑛 Backward Excitation Coefficient (dimensionless)
𝑘𝑛 Propagation Constant (dimensionless)
𝑒𝑛 Normalized Electric Field Component
𝑛 Normalized Magnetic Field Component
𝛿𝑚𝑛 Kronecker Delta Function
J Current Density A/cm2
𝑃 Electric Dipole Moment C.m
𝑀 Magnetic Dipole Moment A.m2 = J/T
a Cell Width m
g Septum Height m
y Gap Width m
Vij GTEM Measured Voltage dBV
bij GTEM Correspondence Voltage V2 ∙ m2 2
𝑒0𝑦 Vertical Electric Field Component at Origin 𝑚
0 Intrinsic Impedance of Free Space, 0 = 120π Ω
Angle Across Vertical Axis Rotation degree (o)
Phase of Moments rad/m
Radian Frequency of Waveform rad/s
xix
LIST OF ABBREVIATION
Abbreviation Description
EMC Electromagnetic Compatibility
EM Electromagnetic
EMI Electromagnetic Interference
RFI Radio Frequency Interference
EMP Electromagnetic Pulse
IC Integrated Circuit
I/O Input / Output
FPGA Field Programmable Gate Array
NREs Non-Recurring Expenses
ASIC Application-Specific Integrated Circuit
SAE Society of Automotive Engineer
IEC International Electrotechnical Commission
PCB Printed Circuit Board
TEM Transverse Electromagnetic Mode
GTEM Gigahertz Transverse Electromagnetic Mode
SAC Semi-Anechoic Chamber
PLD Programmable Logic Device
CPLD Complex Programmable Logic Device
CAD Computer Aided Design
CACA Computer-Aided Circuit Analysis
MOS Metal Oxide Semiconductor
CMOS Complementary Metal Oxide Semiconductor
SSN Simultaneous Switching Noise
SIP System-In-Package
MCM Multichip Modules
BGA Ball Grid Array
EXPO Expert System for Power Supply
xx
Abbreviation Description
NEMO Netlist-based Eission MOdels
PMOS p-type MOS
NMOS n-type MOS
DUT Device Under Test
OATS Open Area Test Site
TDR Time-Domain-Reflectrometry
TFF Toggle Flip-Flop
HDL Hardware Description Language
TE Transverse Electric
TM Transverse Magnetic
EUT Equipment Under Test
RAM Radio-frequency Absorbing Material
VNA Vector Network Analyzer
VSWR Voltage Standing Wave Ratio
VSWR Voltage Standing Wave Ratio
CF Correction Factor
IQR Interquartile Range
xxi
LIST OF APPENDICES
APPENDIX A : Altera EMI Test Board
APPENDIX B
APPENDIX C
APPENDIX D
APPENDIX E
APPENDIX F : Comb Generator CGO-520
APPENDIX G : Bias Network 11590B
1
CHAPTER 1
INTRODUCTION
1.1 General
The electromagnetic compatibility (EMC) of electronic devices is defined as the
ability of the device to operate in its own electromagnetic (EM) environment without
generating and propagating any excessive EM wave and/or suffering degradation
from external electromagnetic interference (EMI) or radio frequency interference
(RFI). In general, EMI is an unintentional EM disturbance which may degrade the
performance of an electronic device or causes malfunction of the device. Any
electronic device must not be susceptible to EMI. This protects correct operation of
the devices from spurious emissions such as lightning strikes, electromagnetic pulses
(EMP), and the absorption of EMI. The concept is applicable for devices in different
levels including system, board, or component levels.
Modern electronic appliances use integrated circuits (ICs) for signal processing
due to the benefits of smaller size and lower development cost. An IC, which is also
known as a chip or microchip, is a semiconductor device fabricated with thousands
or millions of tiny resistors, capacitors and transistors. An IC is considered a
miniature set of electronic circuits fabricated on semiconductor materials, such as
silicon. In the semiconductor industry, advanced process integration technology and
the introduction of new packaging technology at chip scale realized the production of
denser ICs with a higher number of I/Os that can operate at a higher frequency. As a
result, the IC these days most likely has become a significant noise source that causes
EMC problems in electronic devices [1, 2].
A Field Programmable Gate Array (FPGA) chip is a programmable IC that
comprises prebuilt programmable logic blocks and reconfigurable interconnects.
2
Reconfigurable interconnects can be hard-wired to connect different logic blocks
together for the execution of any desired digital logic function. The flexibility and
rapid prototyping capabilities of the FPGA chip have provided an excellent solution
to reach time-to-market constraints in product development, as well as cutting down
non-recurring expenses (NREs) cost for the ICs design industry from the beginning.
These are the uniqueness of the FPGA chip and why it has been increasingly adopted
to replace custom application-specific integrated circuits (ASICs) instead, as
processors for signal processing and control applications. Since the invention of
programmable technology, its density has grown dramatically from a simple
programmable chip into a high density FPGA chip [3]. Therefore, the FPGA chip as
well as the modern IC eventually became an ultimate source of EMI that may
generate excessive disturbance to interfere with functionality of nearby components
or devices [4].
Over the years, EMI concerns at the component level have gained great attention
among semiconductor producers [5]. This is due to growing demand by the end user
with respect to low emission and high immunity device towards EM disturbance,
especially when engaging safety implications in automotive and consumer
electronics applications [6]. In particular, the Society of Automotive Engineers has
introduced standard SAE J1752/3 [7] for measuring the EM radiation from an IC in
1995. During the following year, the International Electrotechnical Commission
(IEC) published standard IEC 61967-2 [8] for the similar purpose. Both standards
define evaluation of an IC EM radiation by clamping the IC test printed circuit board
(PCB) to a wall port cut in the top or bottom of a TEM or wideband TEM (GTEM)
cell. The frequency range of the evaluation is 150 kHz to 1 GHz. Today, both
standards are widely accepted by industry and researchers to perform EM radiation
from an IC. As ICs require supporting components for operation, it is extremely
important to separate the radiation of the IC from its board environment. This is the
reason why the standards suggest evaluation by clamping on the cell wall.
The exploration of the IC EM behavior provides vital information for component
selection and design concerns in an early product development stage. This can
further help to shorten the product development process and avoid additional costs
for shielding or filtering prior compliant product EMC requirements.
3
1.2 Problem Statements
Modern ICs which engage in extraordinary complexity and clock frequency pose
vast challenges for product design engineers in developing electronic appliances to
comply with product EMC test. Inadequate information on the EM behavior of the
ICs is the key factor unworkable of EM simulation involving IC at the early PCB
design stage. Therefore, it has become a normal practice for designers to evaluate
radiated emission of their design at the end of product development. In this case, the
whole design cycle will be repeated if the test is unsuccessful. This happens to
require a longer design timeline and the rising of design costs. Evaluation the EM
behavior at IC level provides useful information that can be used to facilitate EMI in
the design process. With many sophisticated tools available, designers may utilize
the information provided to build a model for analyzing product performance at the
design level.
The International Standard IEC 61967-2 describes the characterization of ICs
radiated emissions using TEM/GTEM cell up to 1GHz. The test setup as described in
the standard is clamping the IC test board on a cell wall port so that the IC test board
becomes a part of the cell wall. This ensures that the IC is the only radiation source
in the measurement and the interference contributed by other noise sources can be
avoided. According to the test procedure in the IEC 61967-2, a wall port must be
developed at an exact location of a GTEM cell for the IC radiated emission test.
Inappropriate wall port integration not only affects the cell characteristics, but it also
will upset the accuracy of the measured voltage because it is closely related the
spacing between the septum and the test board.
The horizontal positioning of the IC has limited the device rotation in two
dimensions across its vertical axis. However, radiated emissions due to the vertical
polarization field is also significant [6, 7] and should not be neglected. It is therefore
desirable to develop an alternative method to evaluate IC radiated emissions, which
account for both horizontal and vertical polarization fields. By performing the
emission test inside the GTEM cell, unpredicted fabrication defects can be avoided.
In addition, the test device can freely rotate in three orthogonal dimensions for data
collection.
Having the IC radiated emission test performed inside the GTEM cell is
challenging because the IC requires supporting components for operation. So, the IC
4
under test must firstly be isolated from the disturbance due to the supporting
components so that reliability of the measured voltage is attained. The isolation can
be done using a metallic enclosure; however, there is a possibility whereby the cavity
might be excited as a radiator. Hence, the metallic enclosure must be set up carefully
to avoid this situation. The usage of external sources to exercise the IC remains the
most crucial matter in the effort to improve repeatability of emission measurement
[9]. The unbalanced current on the outer layer of the connection cable causes
common-mode radiation and requires further studies for minimizing the cable effects
for emission tests in the GTEM cell .
In GTEM cell measurement, the electric field strength cannot be directly
measured instead its relative voltage of the field strength is evaluated. Hence, a
model must be developed for estimating the actual electric field strength. As the
internal structure of the IC is complex, it is difficult to evaluate all the corresponding
parameters throughout measurement technique. The dipole moment technique is a
unique approach which is suitable for this research. In this technique, an equivalent
dipole model is extracted from the GTEM measurement to represent the behavioral
aspect of the IC. The advantage is that the model can be constructed without
revealing the inner details of the actual circuit. The equivalent model is useful to
facilitate EMI of ICs in the design process. Thus, designers may use the model to
represent actual activities for analyzing their design alternatively via simulation.
1.3 Objectives of the Research
i. To establish a technique to perform radiated emission measurement of FPGA chip
inside a GTEM cell.
ii. To create an equivalent model to represent the radiation sources in the FPGA chip
based on dipole moment technique and GTEM cell measurement.
iii. To predict the electric fields of the FPGA using the equivalent model for
correlation with semi-anechoic chamber fields.
iv. To validate the predicted electric fields with the measurement in a semi-anechoic
chamber.
5
1.4 Scopes of the Research
In this research, a GTEM cell is the designated test facilities because this cell has
vast potential be utilized to perform field measurement. First, GTEM cell has a
broadband frequency that is cost effective to perform measurement up to 18GHz.
Unlike a scanning approach, whereby the field probes for measurement have a
limited frequency range, a variety of field probes are required to perform
measurement in broadband frequency. Even though this investigation merely
concentrates on frequency range between 30Mhz to 1GHz, but as fundamental
understanding for the suggested measurement approach has been established, the
work can easily be extended to perform measurement at higher frequency. The
choice to adopt IEC 61967 standard as the guidance for the investigation is the main
reason to limit the scope of the frequency range to between 30MHz to 1GHz.
Second, the cell is well shielded, so interruption of external interference on the
measurement is not an issue. Therefore, field measurement can be carried out in
common environment and do not need be conducted in costly facilities for instance
shielding room. Third, cell test volume has provided sufficient space to
accommodate the test board, hence the board can freely be rotated in three positions
during evaluation.
Since the FPGA chip can be configured multiple times, the programmable feature
of the FPGA chip has provided a perfect test platform for the EMI research at
component level. Thus, the FPGA chip was selected to be the device under test in the
research so that it can be configured with any digital circuit for testing. These
characteristics can greatly reduce the research cost and extensively boost the
capability of a variety of tests to meet different research purposes. The configuration
of toggle flip-flop pattern into the FPGA chip can ensure that the device is
continually active for field measurement.
This research also limits the study scope only on the component of electric field
intensity. The reason is the relationship between the electric field intensity and the
magnetic field intensity can be related with the Maxwell’s Equations. The Maxwell’s
Equations relate the electric and magnetic fields to the sources, current density and
charge density via a set of partial differential equations [10].
In the process to correlate the GTEM measurement to semi-anechoic chamber
(SAC) measurement, the dipole moment technique has been acquired to predict the
6
corresponding electric field intensity in the far distance. The advantage of this
technique is that the equivalent model can be developed without disturbing the
internal structure of the test device. However, a correction factor has been introduced
for the purpose to ease the differences in the correlation. Moreover, the correlation is
validated by performing actual field measurement in SAC which is available at EMC
center.
1.5 Aim of the Research
This research is intended to present a well-conceived approach to conduct radiated
field measurement of an active FPGA chip while the entire FPGA board is laid inside
a GTEM cell. Besides, the research also desires to produce an improved algorithm to
be utilized to enhance the correlation between the GTEM prediction fields to SAC
fields.
1.6 Significance of the Research
This research study on evaluation radiated emission of ICs inside the GTEM cell is
significant to overcome the issues of neglecting part of noise source [11], particularly
for improving weakness of the field measurement technique that mounting the IC test
board on GTEM cell wall. By the way of placing the ICs inside the GTEM cell, the
evaluation can be done thoroughly by rotating the test device in different
orientations.
Further, this research begins an effort to analytically calculate the impact of
irregular measured GTEM cell parameters towards overall cell performance using
the concept of transmission line. This would be beneficial to those facing problems
to obtain suitable test equipment, i.e. TDR for GTEM cell characterization, as this
study has expressed an alternative method which is simple and affordable to evaluate
the GTEM cell.
Furthermore, this research study has described a new idea to enhance component
level EMC measurement approach whereby a correction factor was introduced to the
correlation between the GTEM prediction fields and SAC fields. Even though the
concept of correction factor is not new, the effort to integrate the correction factor to
determine the new GTEM estimation fields could provide to serve as useful
guidelines and information that would benefit other researchers that intend to reduce
7
the gap while correlating the GTEM fields to SAC fields. The correction factor is a
good solution to resolve the differences due to uncertainty in correlation.
1.7 Outline of the Thesis
This thesis is structured as follows. Chapter 1 provides a thorough description the
general concept about the research, such as the overall goals to be achieved in the
research, current issues related to the research, significant of this research work and
why it needs further investigation, techniques and instruments acquired to conduct
the investigation and achievements in the research.
Prior to perform an investigation, the literature review in Chapter 2 provides a
brief understand with theoretical knowledge, rationale, and the IC technologies,
particularly suggesting why the modern integrated circuits are likely to contribute to
electromagnetic interference in compliance EMC test of devices. By reviewing
research work conducted by other researchers, we gain ideas of the common
practices and methodologies that can be utilized for guiding, managing and
organizing activities of the investigation accordingly.
In chapter 3, step-by-step actual research methodologies and data collection
explained and summarized in a flow chart. The chapter explains the reason in behind
why the particular methodology was proposed for investigation so the reader is able
to gain insight how the research objectives can be achieved. The descriptions are
supported with all essential experimental pictures so that the reader can visualize the
environment in which the experiments were conducted. The chapter also discusses
preliminary work to calibrate and analyze the necessary measuring instrument to
ensure reliability and acceptability of the measurement data before proceed further
analysis.
Chapter 4 focuses on modelling of the FPGA chip with dipole moment technique.
The chapter describes the extraction of an equivalent model to represent tiny
radiation sources inside the FPGA chip. An algorithm is developed by considering
the tiny radition sources as Hertzian antenna and small current loop. The algorithm is
then employed to predict the corresponding horizontal and vertical electric fields of
the FPGA chip for correlation with SAC measurement.
Chapter 5 primarily discusses the field measurements of FPGA chip in GTEM
cell. As the GTEM measured voltage is directly related to current distribution across
8
conductor traces; thus, a simple experiment was carried out to investigate field
coupling in GTEM cell. The chapter clearly describes the approaches to encounter
challenges while setting up the FPGA chip for the field measurement inside the
GTEM cell. The discussion also extends to the FPGA chip evaluation in SAC as the
process of field prediction with equivalent dipole model.
The thesis finally is ended with Chapter 6, where the attention, will be particularly
pulled to summarize and conclude on the research works that have been discussed
previously. In addition, recommendations and suggestions will be addressed for
future action.
9
CHAPTER 2
LITERATURE REVIEW
2.1 Background
Prior to the advent of ICs, it was popular to build digital circuits using individual
bulky components, such as transistors and resistors. By the 1960s, the emergence of
the first IC has opened the door for chip fabrication revolution by placing a number
of transistors, and thus the entire circuit on a single chip [12]. As ICs technology
improved, it has evolved dramatically and made possible the first microprocessor, the
2300-transistor 4004 for information processing in one chip by 1970 [13]. Today, it
has become a reality to produce ICs that may accommodate more than one billion
transistors system on a single chip.
IC technology has brought ever-increasing challenges to the electrical product
designer, concerning the ability of their design to operate safely in an increasingly
disruptive electromagnetic environment, especially involving several chips placed on
a PCB. Designers whose have the concepts of EMC would know what they can do
and cannot do at the design stage to minimize the impact of EMI/RFI [14]. As seen
in Figure 2.1, the EMC costs of a product development typically increase from
concept, to detail and validation. So, by taking EMC into account in the early stages,
a product can be designed correctly from the beginning, where the cost to implement
many options is minimal. Conversely, the cost to fix any design flaws is dramatically
increased in the prototyping stage. As time is needed to redesign and retest the
product, this causes delay in the product delivery time and reduces the revenues
generated over the product lifecycle. [15]
10
Initial
investment
Time
savingsPrototype
Retrofit
Progress of project in time
EM
C c
ost
s
With EMC
design
software
Cost savings
Figure 2.1 : Cost and time saving benefits
2.2 Development of Digital Logic Technology
2.2.1 Integrated Circuit Technology
Figure 2.2 shows several types of devices that available for the implementation of
logic circuit using ICs. Programmable logic devices (PLDs) are ICs which contain
pre-fabricated logic circuit elements and programmable switches that can be
configured by the user to realize the desired operation. Recent PLDs for example
complex programmable logic devices (CPLDs) and FPGAs have higher densities,
higher speed and cost advantages that allow a wider variety of circuit
implementations. The PLDs provide design flexibility and therefore it is an ideal fit
for any different markets. However, the programmable switches in the PLDs
consume a significant amount chip area that raises development expenses. This also
leads to a reduction in the circuits operating speed and an increase in power
consumption.
In contrast to PLD, an ASIC chip is device that is built from scratch for a specific
application. Since ASIC chip does not require programmable interconnect circuitry,
it allows a larger number of transistors to be integrated in the same chip area, does
not suffer programmable interconnect delays, and allows power saving. As seen in
Figure 2.2, ASIC chips can be divided into two major categories, full-custom chip
and semi-custom chip. The full-custom design approach is considered as the best
technique as its design can be optimized for developing the highest performance
devices, i.e. microprocessor and RAM chips used in PCs.
11
Digital Logic
Circuit
Programmable Logic
Devices (PDLs)
Application-Specific
Integrated Circuits
(ASICs)
Programmable
Logic Array
(PLA)
Programmable
Array Logic
(PAL)
Complex
Programmable
Logic Devices
(CPLDs)
Field-
Programmable
Gate Arrays
(FPGAs)
Simple
Programmable
Logic Devices
(SPLDs)
Semi-Custom
Chip
Full-Custom
Chip
Microprocessor Memory
Chips
Gate
Array
Standard
Cell
Figure 2.2 : Digital logic technologies [16, 17]
The biggest advantage of the full-custom chip is that the chip designer has
complete decisions on the chip specifications such as the chip process technology,
chip size, the number of transistors on the chip, transistor placement, and how the
transistors are connected together. However, designing a full-custom chip is a time-
consuming task and requires huge design effort. It can require up to several years of
engineering effort to design and test. This explains why full-custom chip
development and fabrication costs are extremely expensive. These high production
costs are typically recouped with high volume product sales.
In situations in which the design does not require complete flexibility like a full-
custom chip, semi-custom approach may be an alternative to reduce some of the
design effort. In standard cell technology, the layout of individual gates so called
standard cells are pre-built, fixed and stored in a library by the manufacturer. The
library can be accessed by the designer and computer aided design (CAD) tools are
used to automatically create the chip layout.
In the actual process to build ICs, transistors and interconnection wires are
basically fabricated in different sequence of steps. Thus, the gate array technology
utilizes this fact, prefabricated parts of the chip without considering the requirements
of the user desired circuit. Then other parts are custom fabricated based on the user
desired circuit. Fabrication is typically involved in the formation of the transistors.
The expense of gate array approach is lower than the standard cells and full-custom
approaches, because the cost of chip fabrication can be amortized by identical
transistors over a large number of template wafers.
12
Overall, ASICs need a final custom manufacturing step to form the desired logic
circuit; however, PLDs only requires user programming to perform the desired
application or function. The manufacturing step involves additional time and
development costs. Any design error in the chip will lead to additional manufacturing
delays and costs. Therefore, high ASIC design costs are making PLDs become a
potential devices to serve many markets. The benefit of PLDs such as being easy to
program and redesign can further reduce design cost and time to market. A design
using PLDs typically require several weeks of engineering effort instead of months.
Figure 2.3 shows the economic and performance trade-off between PLDs and ASICs
design approaches.
SPLDs
FPGAs
CPLDs
Semi-custom chips
Full-custom Chips
Development cost and time
Sp
eed
, d
ensi
ty,
com
ple
xit
y,
pro
du
ct v
olu
me
Figure 2.3 : Technology trade-off [16]
2.2.2 Field-Programmable Gate Arrays
FPGAs are the highest density, sophisticated, and most advanced PLDs which
contain plenty of logic circuit elements and programmable switches. The general
structure of an FPGA is shown in Figure 2.4. The chip consists of three major
resources: logic blocks, I/O cell for connecting to the pins of the package and
interconnection wires, and switches. The logic blocks can be connected together
through the switches to implement any application. Recent FPGA chips may contain
up to several hundred million transistors [18].
13
I/O cellSwitch
block
Logic
block
Figure 2.4 : FPGA block structure [16, 17]
2.2.3 FPGA Process Technology
Figure 2.5 illustrates the device process technology for building Altera FPGA chip
between year 2002 to 2011. As shown in the figure, the process technology for the
FPGAs has dramatically improved since 2004. This achievement significantly
increases the FPGA market potential and vendors’ interest to invest in FPGA
devices. With FPGA technology, the investor no longer needs to compromise with
the ASICs expensive development cost and large production quantity to achieve a
return on investment.
2002 2003 2004 2005 2006 2007 2008 2009 2010 2011
180nm
130nm
90nm
65nm
45nm
32nm28nm
22nm
40nm
Technology
Gap
Primary FPGA
Process Node
Primary ASIC
Process Node
Figure 2.5 : FPGA process technologies [18]
14
Figure 2.6 : Intentions for the Altera high-end Stratix product [18]
At the end of 2013, Altera delivered a 14nm FPGA, Stratix 10, which built on
Intel’s FinFET process. This allows the company to introduce the device as the most
advanced, highest performance, and highest levels of system integration at the lowest
power consumption [18]. However, the design of low power consumption device is
more likely to cause EMI problems due to narrow noise margin, while reducing the
logic threshold.
2.3 A Brief Historical Prespective of IC EMI Research
Figure 2.7 illustrates numerous investigations into the EM behavior involving ICs.
The figure clearly indicates that the earliest EMC studies on IC primarily concerned
exploration of the response and behavior on components, while exposing these
components to excessive high energy waves. The studies are typically intended to
discover a solution to protect the components from affecting by the harsh
environment.
By the 1980s, the rapid growth of VLSI (Very Large Scale Integration)
technology in the semiconductor industry made it possible to produce more complex
chip. The development has brought in the modern electronic era to build smaller and
sophisticated electronic systems. Advance semiconductor technology happens to be a
huge challenge to EMC problems [6]. Consequently, demand for low emission ICs
has become a focus of research. For that reason, it can be observed that the research
focus has shifted toward modelling parasitic emission, especially radiation, coupling,
and overall design modelling.
15
[19-37]
Figure 2.7 : Milestone for EMI research focusing on ICs
Year
2
3
1965
Steinecke [12]
Investigated the EMI effect
of missile launch site on
electronic devices
1975
Richardson [14]
Studied response of low &
high frequency BJT
transistor to microwave
energy
1971
Wooley & Pederson [13]
Investigated IC 741
performance limitations,
characteristics &
parameters using
computer-aided simulator
1985
Tront [16-17]
Studied behavior of 8085
processor for 100 &
220MHz RFI
1979
Larson & Ro [15]
Studied nonlinear RF &
microwave effects in
semiconductor devices
using transistor model
1990
IEC61967 [18]
Started research on ICs
and proposed IC emissions
measurement standard
1991
Senthinathan,
Prince [19]
Established
precise
formulations to
estimate the peak
voltage of
ground bounce
Graffi [20]
Studied
behavior of 741
op-amp when
interfered with a
200KHz -5MHz
signal
1997
Slattery [23]
Highlighted impact of embedded
software on programmable
components (8- & 16- C)
besides IC technology, packaging,
number of switching gates,
temperature
2006
Steinecke [25]
Predict power integrity,
power domain crosstalk, &
EMI noise with EXPO &
NEMO
1
1996
McCredie & Becker [22]
Developed switching
noise model for 1000 pins
ASIC chip using
distributed current
sources, on-chip & on-
package decoupling
capacitance models and
serial connections
inductances
European
Commission
[21, 27]
Enforcement of
EM compliance
on electrical and
electronic
equipment
2011 Scandiuzzo & et al [25]
Non-contact testing for 3D-
IC EMC test 2012
Yaglioglu & Eldridge [26]
External access with nano
contactor for 3D-IC EMC test
2000
Hayashi & Yamada [24]
Predicted simultaneous switching noise
& conducted power-line EMI noise
using hierarchical power supply
distribution model, on-chip power bus
& distributed switching circuit model
2010
Chen, Dong & et al [26]
Characterized radiated emission
at board level and simulated its
far-field EMI spectra.
2013
S. Muroga & et al [25]
Development of 3D magnetic
near field scanner for
measuring magnetic near field
on LTE-class RFIC chips 2014
J. Wu & et al [26]
A review on the most recent 3D-
IC EMC measurement methods
16
In 1996, expansion of chip level EMC knowledge was again driven by the
enforcement of the parasitic emission level limit on electrical and electronic
equipment. The enforcement was commenced by the European directive. In
response, several international standards were introduced as guidelines for EMC
characterization, modelling and strategies for reducing the radiation emitted by ICs.
Table 2.1 lists several standards widely utilized for IC EMC characterization and
modelling.
Table 2.1 : International guidelines for ICs EMC characterization and modelling
Indicator Standard Issued Date
SAEJ1752-3 : Measurement of Radiated Emissions from
Integrated Circuits – TEM/Wideband TEM (GTEM) Cell
Method; TEM Cell (150KHz to 1GHz), Wideband TEM
Cell (150KHz to 8GHz)
March 1995
IEC62014-3 : EMC for Component, Integrate Circuits
Electrical Model (ICEM) March 2001
IEC 61967-2 : Integrated Circuits – Measurements of
Electromagnetic Emissions, 150KHz 1GHz
Part 2 : Measurement of Radiated Emissions – TEM cell
and wideband TEM cell method
September 2005
Nowadays, 3D fabrication technology [38, 39] complements conventional
transistor scaling to achieve the realization of higher levels of integration with the
size reduction. Three dimensional integrated circuits, 3D ICs, promise significant
benefits to address the scaling challenge by stacking 2D dies and connecting the 2D
dies in the three-dimension. As 3D IC stacking semiconductor dies are
interconnecting using through-silicon-via (TSV) technology, the TSV defects test is
the most recent study concerning on the 3D-IC defects and failures [40, 41]. In
future, study will focus on the development of new techniques for 3D-ICs EMC
measurement.
2.4 Justification of The Research Gap
Table 2.2 summarizes numerous studies relevant to EMC investigation at the
component level. From observation, the near field scanning technique has become a
1
2
3
17
preferable choice of most researchers to investigate chip-level emission since the
technique was first adapted to evaluate the radiated field above the integrated circuit
[42-45]. The near field scan captures the EM field by fixing a radio frequency probe
at near distance over the planar surface of the IC. The mechanical positioning system
is acquired to grasp and automate the movement of the probe over the surface.
Therefore, the measurement setup for near field scan method is cheap and easy.
However, studies by [28, 43] indicate that time is needed to repeat the
measurement across multiple points on the surface, the finer distance variation, the
longer time acquired. In the meantime, different probes also required to measure
each of the electromagnetic field components separately [46]. This clearly
demonstrates the importance of an alternative approach for IC emission measurement
if time is significant in the evaluation.
Furthermore, the highly sensitive field probes suggest that the probes may capture
undesired components if the setup ambient is not free from contamination of EM
interference. A practical approach to overcome the weakness is to setup the system in
a shielded room, leading to a rise in measurement cost. To minimize the cost for
EMC evaluation and maintain competency of device time to market, it thereby found
that TEM or GTEM cell still a widely utilized method to investigate electromagnetic
field emission [47-51]. An advantage of the TEM or GTEM cell is that the test
environment is well-shielded by the cell body. This allows measurement to be
conducted without concerning the surrounding ambient condition.
Table 2.2 : Existing research works that relavent to the scope in the research
Author Measurement
Technique
Modeling
Technique Validation Result
Ippalapalli
Sreenivasiah,
David C.
Chang, & Mark
T. Ma, 1981
[52]
TEM cell
method (placed
EUT inside
TEM cell)
An equivalent
dipole system
which consists of
three electric
dipoles and three
magnetic dipoles.
Comparing
electric-dipole
source with a
TEM
measurement
dipole.
No significant
differences of
the dipole
moment when
moving along
the vertical
axis.
Edwin L.
Bronaugh &
John D. M.
Osburn, 1991
[53]
Measurement
inside GTEM
cell
Nil 3m and 10
OATS
measurement
The average
difference field
of personal
computer for
3m and 10m
OATS
18
measurements
are respectively
3.18dB and
2.18dB.
Xu Cheng &
Chen Zhiyu,
2003 [54]
GTEM cell Linear method
which assumes
phase difference
between the
electric and
magnetic dipoles
is 𝜋 2 .
- 1m SAC
measurement
- 3m SAC
measurement
- 10m OATS
measurement
- Only requires
six equations
to obtain all
dipoles.
- The radiated
field strength
10m OATS is
well matched
to predict.
Bernd
Deutschmamn,
Harad Pitsch, &
Gunter Langer,
2005 [43]
Near field
scanning
method
No model builds
in for
investigation
TEM cell
measurement
(campling on
cell body).
The results
match in an
acceptable
manner.
Yolanda V.G,
Christian A.
Anne Loius, F.
Daran, P.
Eudeline, & B.
Mazari, 2007
[55]
Near field
scanning
- A set of
electric dipoles
- A set of
magnetic
dipoles
Compare near
field
measurement
using the vector
network
analyzer and
the spectrum
analyzer.
- Shorter time
needed to
measure the
magnetic
dipoles (only
measures one
component of
the magnetic
field).
- The electric
dipole
approach
provides
higher
accuracy.
J. Li, S.G. Xing,
& S.F. Li, 2008
[56]
Field
measurement in
GTEM cell
- EMD
technique
(consider the
electric dipole
as equivalent
model)
- Linear
technique
(phase
difference
between the
dipoles is 90
degrees.
Open Area Test
Site (OATS),
10m.
Attain good
agreement
between
simulation and
measurement
result.
S. M. Pan, J.G.
Kim, S.Nn Kim,
J. Park, H.C.
Oh, & J. Fan,
TEM cell Model the
radiation source
with three dipole
moments, Pz, Mx
Semi-anechoic
chamber
measurement
- z-direction:
peak values
are matching
well
19
2010 [57] and My. - y-direction:
TEM
measurements
are smaller
than far-field
measurement.
H.N. Lin, T.J.
Cheng, & C.M.
Liao, 2010 [58]
TEM cell
method
Nil Surface scan
method.
Device rotation
affects the
radiation at
different
frequencies.
C.C. Chan, J.L.
Dong, Y.T.
Chang, C.K.
Chen, C.W.
Hsue, &
S.Ikami, 2010
[33]
- Near field
scan:
determine hot
spot
- Far field
measurement:
identify the
critical
frequency
Simplified model
(represent the
CPLD with two
conducting
power planes -
3.3V and 5V).
- 10m semi
anechoic
chamber
measurement
- Simulation
with SPICE
solver,
moment of
method
(MoM).
Simplified
model reduces
computational
complexity at
system level.
Z.W. Yu, J.A.
Mix, S.
Sajuyigbe, K.P.
Slattery, J. Fan,
2012 [59]
Near field
scanning
measurement
Extract dipole
moment model
using
regularization
technique and the
truncated SVD
method.
- Simulation
with ful-wave
tool
The extracted
dipole moments
reflect the
voltage and
current
distribution in
IC.
J. N. Pan, G.H.
Li, Y. Zhou,
Y.D. Bai, X.Q.
Yu, Y.J. Zhang,
& J. Fan, 2013
[60]
Near field
scanning
method
Model the
radiation with
three dipole
moment, Pz, Mx
and My.
Semi-anechoic
chamber
measurement
Peak
differences less
than 8dB.
M. Al-Hamid,
M. Leone, S.
Schulze, 2013
[61]
GTEM cell
method
Numerical
models for
monopole noise
generator and
metallic
enclosure with
monopole noise
generator with
CONCEPT.
Semi-anechoic
chamber
measurement
The frequency-
dependent
directivity able
to improve
correlation of
emission
spectrum.
In term of the process to correlate field measurement from near distance to far
distance, Table 2.2 reports a variety of efforts that have been made to create better
and simpler models to achieve more accurate results. Existing research indicates the
20
dipole moment model gains greater attention than others. The details for other IC
models are discussed in section 2.7. Basically, the concept of the dipole moment
model is to symbolize the radiation source with either a complete set of dipoles
which comprises three electric and three magnetic dipole moments [54, 62, 63]; a
small number of dipoles (an electric dipole moment and two magnetic dipole
moments) [54, 57, 60]; the three electric dipole moments [56]; or the three magnetic
dipole moments [56].
A challenge of GTEM cell measurement is that the phase difference between the
electric and magnetic dipole moments cannot be obtained via measurement because
the GTEM cell is a single port instrument. This is the difference between GTEM cell
and TEM cell as well as near field scan. Ae-kyoung Lee proposed an algorithm to
determine the relative phase differences of dipole moment components [62].
However, this approach requires at least fifteen orientations of the test device in
GTEM cell. As the main objective of this research is to establish a methodology to
perform field measurement inside a GTEM cell, the issue may simply be resolved by
assuming the phase difference between the electric and magnetic moments to be
either zero or 90 degrees. The literature in [54] indicates that both assumptions may
result in a comparable conclusion.
In view of the fact that existing investigations mainly emphasized on
manipulating algorithm to achieve higher accuracy. The uncertainty of the realistic
measurement parameters which indirectly affect the measurement are not considered
in the prediction. Therefore, this investigation intends to propose a solution to tackle
real-world measurement uncertainty using the correction factor. In general, the
developed correction factor is integrated in the algorithm in order to improve the
correlation between GTEM estimation to SAC measurement. As this research work
is comparable with Pan’s work, even different approaches have been utilized in the
prediction. Thus, the peak differences of Pan’s work, which is 8dB, were accepted as
benchmark for comparison in my research work.
2.5 Mechanism of Chip Emission
CMOS is a typical design style that utilizes a pair p-type MOS (PMOS) transistor
and n-type MOS (NMOS) transistor to implement any logic circuits. Under steady
state conditions, no current flows in CMOS circuits; hence, no power is dissipated.
21
The power is only drawn during switching between ON and OFF states. This
suggests that CMOS circuits have high noise immunity and low power consumption.
This explains why CMOS technology is popular for use in implementing ICs.
The major source of chip emissions is internal noise activities which are generated
from simultaneous switching in ICs. For an example in a CMOS inverter circuit,
simultaneous switching causes a transition from low to high and high to low. The
switching activity generates a power current IP or ground current IN which flow
mainly on the supply lines (VDD and VSS) as shown in Figure 2.8. Subsequently,
voltage spikes are developed within the circuit due to the rapid changes from low to
high or high to low. The variations of current flow through the bonding and package
inductances induce a voltage drop to cause a severe ground-bounce.
VDD
Ip
C
Input
VDD
IN
C
Input
(a) (b)
Figure 2.8 : Mechanism of emissions due to current flowing during switching [28]
Current amplitude and IC operating frequency are two important factors that
affecting power or ground current. As shown in Figure 2.9, the voltage supply of IC
continue to decrease in new process with the purpose of minimizing power
consumption as well as heat dissipation due to the growing number of transistors in
the device. Nevertheless, the amplitude of the current flowing into the device stays
consistent with the lower voltage supply. With high speed switching activities, the
signals within interconnects switch faster and tend to cause strong current variation
over short period (di/dt) on power supply lines. These short and sharp peaks
apparently become sources to generate electric and magnetic fields in the power
supply lines. The generated fields will provoke severe interference both inside and
near the IC [31, 64].
22
Volt
Time
Old process
New process
Current
Time
Old process
New process
di/dt
Figure 2.9 : Strong di/dt generation with technology scale down [28]
2.5.1 How Integrated Circuit Generates Disturbances
Figure 2.10 shows several channels how EMI associated with the internal noise
activities can cause EMC problems. First, noise is directly emitted from the chip
surface. In this condition, bonding wires between the die and package, package leads,
and metal wires within the die behave as an antenna to transmit the high frequency
peaks. Second, the noise is transferred by coupling to data buses on a PCB, I/O pins,
connectors and cables. Third, the noise is transmitted by coupling to power or ground
lines on the PCB and power cable. In general, the noise can be transferred through
two mechanisms: direct emission and conducting paths. The conducted emission
transfers the noise by generation of both common mode and differential mode at
conductor paths whereas the radiated emission propagates the noise directly off the
chip via space [31, 65].
23
Internal activities
noise
Conducted
Emissions
Radiated
Emissions
Coupling by
Power Lines
Coupling by
Input/Output
(a)
»
Conducted
emission
Radiated
emission
v
i
(b)
Figure 2.10 : Paths for ICs to generate disturbances [19]
As previously described, high frequency voltages and currents are known to be
factors that contribute to electric and magnetic fields inside ICs. Electric fields are
particularly generated by the square-wave clock voltages between the metal traces
inside the IC or between the metal traces and the GND plane. If the route between
traces and the GND system is short, it maybe found that most electric flux lines are
grounded to the GND system and few spreading upward into the surrounding area as
illustrated in Figure 2.11.
Figure 2.11 : Mechanism of direct electric field emission
Magnetic fields are generated by the high currents flow in Vdd-Vss current loops
that are blocked by the input capacitors and the PCB GND plane. Two types of
24
magnetic fields, 𝐻 1 and 𝐻 2 are generated as shown in Figure 2.12. The field 𝐻 1 is
formed around the ground plane to induce a voltage and then it is coupled with the
cables that are connected to the PCB. The field 𝐻 2 surrounding the IC surface is
caused by the currents across the ICs internal conductors, and is generally stronger
than the field 𝐻 1.
Figure 2.12 : Mechanism for direct magnetic field emission
2.6 GTEM Cell for Emission Measurements
The Gigahertz Transverse Electromagnetic (GTEM) cell is an alternative facility
developed to overcome the frequency limitations of the TEM (Transverse
Electromagnetic) cell for EMC testing. The earliest TEM waveguides operated in an
open environment, so they have to be protected with shielded rooms. To avoid the
need for a shielded environment, the first self-contained shielded cavity TEM cell,
Crawford Cell was introduced in 1974 [66]. The cell comprises a flat and wide center
transmission line, and two tapered ends for transition to standard 50 coaxial
feeding points.
The transition between the rectangular and the tapered part excites higher order
mode to disturb TEM wave propagation, thus the cell frequency is limited at low
frequency, between 150 kHz to 1 GHz [1, 2]. Therefore, the GTEM cell was
developed to overcome frequency limitation of the TEM cell. The GTEM cell has the
following advantages:
(a) Adequate usable space for accommodating test device.
(b) Affordable cost to buy and maintain.
(c) Provide broad frequency and good ambient shielding.
(d) Applicable for both radiated emissions and radiated immunity measurements.
132
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