Journal of ELECTRICAL ENGINEERING, VOL. 53, NO. 3-4, 2002, 76–80

CHIP DESIGN BASED ON GENETIC APPROACH

Gregor Papa — Jurij Silc∗

With the growth of circuits and higher testability demands there is a need to speed up the design to shorten the time-to-market delay. But ensuring this demands many parameters have to be taken into account. The most appropriate algorithmsare based on an evolutionary approach, since they are able to investigate a wide range of possible solutions and to give a nearoptimal solution in a relatively short time. This paper presents a new Allocation-Based Scheduling (ABS) algorithm. Thisalgorithm improves part of the chip design process — scheduling and allocation. The algorithm bases on a genetic schedulingalgorithm, but due to its cost function it is able to produce the optimal schedule for the process of allocation. The algorithmis also compared with other algorithms through the evaluation of schedules of different input graphs. It turned out that theABS algorithm made the best solutions in all tests and is therefore very appropriate for use in chip designing.

K e y w o r d s: evolutionary technique, high-level synthesis, scheduling, allocation

1 INTRODUCTION

Automated chip design can be described as the high-level synthesis of a chip. High-level synthesis is the designprocess which produces a register transfer level (RTL)design that implements the behavioral specification ofa digital system at the algorithmic level [3]. An RTLstructure consists of two parts, a data path and a controlpath. The data path is a network of functional units(eg , ALUs to perform arithmetic and logical operations),registers for data storage and interconnections for datatransportation. The control path is a programmable logicarray (PLA) used to control the data transfers in the datapath. The control path is produced by the specificationof a finite state machine that derives the data path.

The first step in high-level synthesis is the compilationof the high-level description language (eg , VHDL) intoa graph-based representation, which contains both thedata flow and the control flow implied by the specifica-tion. Some transformations can be made here to enhancethe efficiency of the resulting design. The next two stepsin synthesis are the cores of transforming behavior intostructure: scheduling and allocation. They are closely in-terrelated. Operations are scheduled into time steps andhardware elements are allocated for the functional unitsand registers that are needed. Finally, a controller is de-signed to generate the control signals that are needed toinvoke the data operations in the scheduled control steps.Such a completed RTL design is ready to be sent to alogic synthesis system or physical design system.

The crucial part of synthesis is the search for the struc-ture that best meets the constraints, such as cycle time,chip area and power consumption, while minimizing othercosts. Within a control step, a separate functional unit isrequired to execute each operation assigned to that step.Thus, the total number of functional units required in

a control step directly depends on the number of opera-

tions scheduled into this control step. Therefore, schedul-

ing is an important task in high-level synthesis because it

compromises between design cost and performance. Andeven more, through the allocation, it influences the final

design.

As it can be seen in [5, 6, 7], there are many scheduling

algorithms but they differ in production of optimal solu-

tion. Best results were obtained by Genetic Algorithm(GA) [1] and therefore it is reasonable to use the prin-

ciples of this algorithm to find some optimal solutions.

Even if sometimes it does not give the best solution, its

undeterministic approach makes it possible to find the

global optimum in a field of many local optimums.

All algorithms have different approaches to solving the

same problem. No matter how close to the optimum an

algorithm can come, it is important how those schedules

would be allocated in the final design. Since the processes

of scheduling and allocation [4] are heavily interrelated,we cannot judge if some algorithm is optimal till we get

the final results of the allocation algorithm.

When creating the new algorithm someone should take

into account that the scheduling algorithm has to considerthe allocation criterions. The speed and effectiveness of

the GA conducted us to build our new algorithm on the

basics of evolution. Moreover, the GA gives the results

that are convenient for the process of allocation.

2 ABS ALGORITHM

This paragraph presents our new Allocation-Based

Scheduling (ABS) algorithm. This is an improved schedul-

ing algorithm, and due to its evaluation criteria it is able

to schedule the input data-flow graph into the optimum

∗ Computer Systems Department, “Jozef Stefan” Institute, Jamova 39, SI-1000 Ljubljana, Slovenia, Gregor.Papa@ijs.si, Jurij.Silc@ijs.si

ISSN 1335-3632 c© 2002 FEI STU

Journal of ELECTRICAL ENGINEERING VOL. 53, NO. 3-4, 2002 77

read the inputgraph

calculate ASAPand

ALAP values

set the s tartingpopulation

cheapes tunits

randomunits

fast units on thecritical path

unitallocation

end ofevolution

reproduction

crossover

mutation

find the bestsoluti on

write the finalschedule

geneticalgorithm

0 2

1

yes

no

single soul tion

set of sol utions(parallel solving)

Fig. 1. Block diagram of the ABS algorithm

input for the process of allocation. Consequently, this al-gorithm prepares the data to be allocated more quickly,more easily, and more effectively.

2.1 Motivation

In the field of high-level synthesis there are a lot ofscheduling and allocating algorithms. They differ in termsof approach, complexity and efficiency. But there are justa few algorithms that combine both processes and preventsome of the disadvantages that come from the interdepen-dence of the two processes. Basically, both processes arecontradictive but the algorithm that considers the prin-ciples of both processes can be more efficient.

As mentioned, our algorithm is based on GA andtherefore comprises many of its characteristics. The ad-vantages of the ABS algorithm are:

• Speed: for the computation of the initial population ofsolutions it uses ASAP and ALAP algorithms.

• Simplicity: for transformation of the solutions it usesGA, so it is not computationally greedy.

• Robustness: due to the nature of GA, it is resistant toany extreme state — it does not increase the compu-tation but is evaluated through cost function.

Although GA uses random search, this search is notblind. The information from the past is namely used inthe search of the next, better generation.

Suitability of GA in chip designing can be describedas:

• Complexity : design problems are complex, but the ef-fectiveness of GA, according to other algorithms, in-creases with the complexity of the problem.

• Parallelism: the nature of GA enables parallel execu-tion of the algorithm on more processors, which leadsto greater time saving.

• Extensiveness : GAs research the wide area of possiblesolutions and not only the narrow part of the area.

• Scalability : the nature of GA (they give good resultsquickly and need more time for excellent solutions)enables us to choose the kind of solution according toavailable time.

The algorithm also supports multicycling and the useof multifunctional units. Since the nature of the GA al-lows it, parallel implementation of an algorithm can beachieved with some minor changes of the algorithm code.With the parallelism the time complexity of the algorithmis slightly improved.

2.2 Schematic description of the algorithm

Figure 1 presents the block diagram of the ABS al-gorithm, where the successiveness of functions and theirrelations can be seen. Also the parallelism is pointed withthe set of solutions that are solved concurrently.

The pseudo code of the ABS algorithm can be pre-sented as:

Initialization()ReadData()ASAP()ALAP()SetStartingPopulation()Generation = 1UnitAllocation ()Evaluation()while Generation < Generationmax do

Reproduction()Crossover()Mutation()UnitAllocation()Evaluation()Generation = Generation + 1

endwhile

FindBestSchedule()WriteResult()

78 G. Papa — J. Silc: CHIP DESIGN BASED ON GENETIC APPROACH

6.9

4.4

2.7

77.7

77.4

77.6

3.8

2.7 2.7

5.3

3.2

1.9

5.3

3.1

1.9

0.1

0.0

0.0

0

1

2

3

4

5

6

7

8

9

10

100-200 200-300 300-400

ASAP

ALAP

FDS

LS

FDLS

ABS

3.8

4.5

5.8

63.6

76.2

93.0

3.6

2.4

3.2

2.8

2.5

5.1

2.8

2.5

5.0

0.0

0.1

0.0

0

1

2

3

4

5

6

7

8

9

10

5 3 2

ASAP

ALAP

FDS

LS

FDLS

ABS

cost*

4.7

3.1 3.5

3.5

77.6

0

2

4

6

8

10

ASAP ALAP FDS LS FDLS ABS

0.0

Fig. 2. Costs of the algorithms

2.3 Cost function

One of the main parts of the ABS algorithm is itscost function, which considers more criterions. The costfunction Cost , derivatives of which are described in [2, 9],is here defined as

Cost =

( n∑

i1

(

FUi∗ costFUi

)2

+(

Reg∗ costReg

)2

+(

Bus∗ cost Bus

)2

+(

T ∗ costT

)2

)1/2

(1)

considers the number of functional units FU , the num-ber of registers Reg , the number of buses Bus , and theexecution time T . In each control step the number ofresources has to be evaluated.

• number of functional units FU is the largest numberof one type of a unit, used in any of the control step,

• number of registers Reg is the largest number of vari-ables needed in any control step,

• number of buses Bus is the largest number of tran-sitions (inputs/outputs into/from functional units) inany control step,

• execution time T is time needed to finish all scheduledoperations.

According to different kinds of multi-objective costfunctions and their effectiveness [2, 9], we decided to usethe distance function in multi-dimensional space, whereeach coordinate presents one of the criterions. All thesecriterions are also weighted to ensure compatibility ofparameters.

This approach was already used in several applica-tions, as described in [2], where some scheduling opti-mizations are also included.

3 EVALUATION OF THE ABS ALGORITHM

To evaluate the ABS algorithm we compared it withother algorithms (like ASAP — As Soon As Possible[3], ALAP — As Late As Possible [3], FDS — Force-Directed Scheduling [8], LS — List Scheduling [3] andFDLS — Force-Directed List Scheduling [3]) when tryingto schedule the data-flow graph of different input graphs.

Random graphs were made to evaluate the algorithmwith various kinds of graphs (different sizes, differentnumber of operation types). The following Figs. 2, 3, 4and 5 present the evaluation of the schedules obtainedwith different algorithms. In each figure the first graphpresents overall evaluation of the parameter while the sec-ond and the third present the evaluation of the parame-ters according to the size of the graph and the number ofdifferent operation types, respectively.

The cost of each scheduled graph is set by the ABS’scost function (Eqn. 1) and with parameters (weights):

• costs of functional units: 7.1, 6.3, 6.3, 5.9, 7.4

• cost of register: 2.9

• cost of bus: 1.1

• cost of execution time: 0.5

The weights for cost parameters were set accordingto the importance of the parameters and their area. Theweights of the functional units are set according to theirarea size. The weight of the registers is set by their sizeand evaluated number of transitions of data. The weightof the buses is set according to their importance, sincethey connect all registers and functional units and theyalso need a lot of space in their implementation. Theweight of the execution time is used to prevent the in-crease of the execution time.

Figure 2 presents the evaluation of the algorithms withthe cost* function of the ABS algorithm. The cost* valueis an average normalized cost of the function presented inEqn. 1, for different graphs. No matter what the size ofgraph is or how many operation types it has, it is alwaysthe ABS algorithm that produces the solution with thelowest cost.

Journal of ELECTRICAL ENGINEERING VOL. 53, NO. 3-4, 2002 79

100-200 200-300 300-400

63.6

76.2

93.0

10

functional units

10.8

4.1

4.1

11.4

31.2

510.0

0

10

20

30

40

ASAP ALAP FDS LS FDLS ABS

36.0

32.8

24.8

384.9

518.4

626.7

9,7

7.9

14.9

2.1

4.6 5.5

2.1

4.6 5.5

12.9 15.1

6.0

0

5

10

15

20

25

30

35

40

22.4

35.4

35.8

25.8

6.7

0.0

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4.9

0.0

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4.9

0.0

1.9

7.4

24.7

0

5

10

15

20

25

30

35

5 3 2

ASAP

ALAP

FDS

LS

FDLS

ABS

ASAP

ALAP

FDS

LS

FDLS

ABS

Fig. 3. Excess of functional units

registers

1.4

0.0

1.5

2.1

2.1

0.1

0

1

2

3

4

ASAP ALAP FDS LS FDLS ABS

1.7 1

.7

0.8

0.0

0.0

0.0

1.2

1.9

1.2

3.0

2.3

1.1

3.0

2.2

1.1

0.0 0

.2

0.1

0

1

2

3

4

100-200 200-300 300-400

ASAP

ALAP

FDS

LS

FDLS

ABS

1.2

1.2

1.7

0.0

0.0

0.00

.1

1.8

2.4

1.2 1.3

3.9

1.0

1.0

4.0

0.1 0

.2

0.0

0

1

2

3

4

5 3 2

ASAP

ALAP

FDS

LS

FDLS

ABS

Fig. 4. Excess of registers

Figure 3 presents the evaluation of the excess of the

number of all functional units needed in each schedule ac-

cording to the schedule with smallest number of needed

units for that graph. Since the other algorithms are op-

timized for scheduling only (they minimize the number

of functional units only), the ABS is able to compete

with them when scheduling large graphs or graphs with

a large number of operation types. Actually ABS needs

more functional units than some other algorithms, but

functional units are not the only resources that influence

the overall design cost.

Important parts of the overall design cost are also reg-

isters and buses. In contrast to other algorithms, ABS is

able to evaluate the number of registers and buses. Fig-

ure 4 presents the evaluation of the excess of the num-

ber of registers in each schedule according to the sched-

ule with the smallest number of needed registers for that

graph. Figure 5 presents the evaluation of the excess of

the number of buses in each schedule according to theschedule with smallest number of needed buses for thatgraph.

When scheduling with ABS algorithm functional unitsand registers are used optimally and there are fewer busesneeded to make the final design. So, the ABS algorithmmade the best solutions in all tests and is therefore veryappropriate for use in chip designing. Namely it is one ofthe algorithms that considers allocation while trying tooptimally schedule the data-flow graph.

4 CONCLUSIONS

In this paper we presented a part of the chip designprocess. For this purpose we made a new genetic algo-rithm which has some good approaches used in other al-gorithms. We preferred speed, universality and robust-ness.

80 G. Papa — J. Silc: CHIP DESIGN BASED ON GENETIC APPROACH

68.1

63,9

107.3

629.8

622.4

767.5

63.2

22.0

63.0

56.4

37.6

77.4

56.4

37.6

77.4

1.6

0.0

0.0

0

10

20

30

40

50

60

70

80

90

100ASAP

ALAP

FDS

LS

FDLS

ABS

buses

79.8

49.4

57.1

57.1

0.5

673.2

0

20

40

60

80

100

ASAP ALAP FDS LS FDLS ABS

87.2

77.3

74.8

548.8

675.4

795.5

55.1

35.5

57.7

69.2

52.7

49.5

69.2

52.7

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0.0 1.6

0.0

0

10

20

30

40

50

60

70

80

90

100

100-200 200-300 300-400

ASAP

ALAP

FDS

LS

FDLS

ABS

Fig. 5. Excess of buses

The evaluation of the algorithm shows that this algo-rithm is appropriate for chip design as for the speed andeffectiveness. According to those results it is obvious thatthe algorithm is good not only for scheduling but also forthe next step of the design allocation. Schedules obtainedwith the ABS algorithm need fewer resources than thoseobtained with other algorithms.

The ABS algorithm, its effectiveness and wider usagecan be improved with some of these changes:

• reproduction within the separate breeds (in directionsof separate criterions) and mixing of them periodicallyto achieve a larger difference between single solutionsand better development of solutions in the direction ofsingle criterion;

• changed (completed) cost function — weights couldbe set according to the allocation demands and rules,which avoids the problem of defining the weights, be-cause the choice of bad weights leads to inappropriatesolutions;

• even better results would be achieved if we consideredthe areas of all resources and their layout in the finaldesign;

• connection with the source file would enable bettercontrol of all variables (constants) and therefore higherusage of registers;

• faster convergence and accuracy: merging of GA andsome gradient method, where GA would come close tothe global optimum and gradient method would find theoptimum quickly and accurately.

All improvements mentioned above show how unex-plored the area of GA is and that they can be used tosolve any kind of problem.

References

[1] BACK, T. : Evolutionary Algorithms in Theory and Prac-

tice:Evolution Strategies, Evolutionary Programming, Genetic

Algorithms, Oxford University Press, New York, 1996.

[2] COELLO, C. A. : A Comprehensive Survey of Evolution-

ary-Based Multiobjective Optimization Techniques, Knowledge

and Information Systems 1 No. 3 (1999), 269–308.

[3] GAJSKI, D.—DUTT, N.—WU, A.—LIN, S. : High-Level Syn-

thesis: Introduction to Chip and System Design, Kluwer Aca-

demic Publishers Norwell, Massachusetts, 1992, pp. 213–258.

[4] McFARLAND, M. C.—PARKER, A. C.—CAMPOSANO, R. :

The High-Level Synthesis of Digital Systems, Proc. of the IEEE

78 (2), 301–318.

[5] PAPA, G.—SILC, J. : Scheduling Algorithms Based on Genetic

Approach, Proc. 4th Conference on Neural Networks and theirApplications, Zakopane, Poland, May 1999, pp. 469–474.

[6] PAPA, G.—SILC, J. : Using Simulated Annealing and Genetic

Algorithm in the Automated Synthesis of Digital Systems, In

Mastorakis (ed.): Recent Advances in Circuits and Systems,

World Scientific, 1998, pp. 377–381.

[7] PAPA, G.—SILC, J.—BRATKOVIC, F. : Scheduling Algo-

rithms in High-Level Synthesis — Overview and Evaluation,

Electrotechnical review 65 (4) (1998), 153–165.

[8] PAULIN, P. G.—KNIGHT, J. P. : Force-Directed Scheduling in

Automatic Data Path Synthesis, Proc. 24th ACM/IEEE Design

Automation Conference, Miami, FL, June 1987, pp. 195–202.

[9] SRINIVAS, N.—DEB, K. : Multiobjective Optimization Using

Nondominated Sorting in Genetic Algorithms, Journal of Evo-

lutionary Computation 2 (3) (1994), 221–248.

Received 4 April 2001

Gregor Papa is a research assistant at the “Jozef Stefan”

Institute in Ljubljana, Slovenia. He received his MSc degree in

Electrical Engineering from the University of Ljubljana, Slove-

nia, in 2000. His research interests include high-level synthesis,

parallel computing, and optimization techniques.

Jurij Silc is a researcher at the “Jozef Stefan” Institute

in Ljubljana, Slovenia. From 1980 to 1986 he was a researchassistant at the Department of Computer Science and In-

formatics. From 1987 to 1993 he was the Head of the Labora-

tory of Computer Architecture at the same department. Since

1994 he has been Deputy Head of the Computer Systems De-

partment at the “Jozef Stefan” Institute. Mr. Silc received his

PhD degree in Electrical Engineering from University of Ljubl-

jana, Slovenia, in 1992. His research interests include parallel

computing, computer architecture, and high-level synthesis.