Charge-packet splitting in charge-domain devices

1494 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-31, NO. 10, OCTOBER 1984

[ 21 L. Halbo and J. Haraldson, “The magnetic field sensitive transi.rtor- A new sensor for crank shaft angle position,” Trans. ASE, vcI. 89, p. 701,1981.

[3] R. S. Popovic and H. P. Baltes, “Dual-collector magneto-trartsjstnr optimized with respect to injection modula_tion,” in Solid.State Transducer ‘83. Delft, The Netherlands: Delft Univ. of Technol., to be published.

[4] A. W. Vinal and N. A. Masnari, “Bipolar magnetic sensor:,” in IEDM Tech. Dig., pp. 308-31 1, Dec. 1982.

[5] A. Hanneborg and L. Halbo, “Using a lateral pnp transistcr for sensing lateral magnetic fields,” in Roc. 10th Nordic Semicon- ductor Physics Conf., (Elsinore, Denmark), June, 1982.

[6] A. W. Vinal and N. A. Masnari, “p-n junction injection modulated magnetic sensors (JIMMS),” in Solid-State Dansducers. Delft, The Netherlands: Delft Univ. of Technol., June 1983.

[7] -, “Magnetic transistor behavior explained by modulation of emitter injections, not carrier deflection,” IEEE Electron Device Lett . , vol. EDL-3, pp. 203-205, Aug. 1982.

[8] -, “Response to comment on magnetic transistor behavior explained by modulation of emitter injection, not carrier deflection,” IEEE Electron Device Lett., vol. EDL-3, pp. 396-397, Dec. 1982.

[9] D. Shain, private communication.

Charge-Packet Splitting in Charge-Domain Devices

SELM s. B E N C F A , STUDENT MEMBER, IEliE, AND ANDREW J. STECKL, SENIOR MEMBER, IEEE

Aktruct-The charge packet splitting operation employed by charge domain filters to implement fractional multiplication has been descr bed. Several experiments have been designed to determine the accuralry of this operation. The fabricated circuits investigate the dependence of split accuracy on coefficient value, channel width, barrier shape, barrier location, and the extra (dummy) barriers. A computerized data al:qui- sition system has been designed and used in the characterization o P the ckcuits. The dc and pulse transfer curves of these circuits show a p o d overall linearity. The transfer inefficiency, coefficient value, ant1 coefficient error have been determined as a function of clock frequtncy. Results show that coefficient error is essentially independent a!! frequency, and that large coefficients and large channel widths :rield higher accuracies. Dummy barriers decrease coefficient error si@fi- cantly, especially in narrow-channel devices.

C I. INTRODUCTION

HARGE-DOMAIN devices (CDD’s) have been introdt ced in the past few years as a new class of charge-transfer de-

vices [ l ] -[6]. These devices are primarily used to perhrm sampled data signal processing functions. The major applica- tion of these devices is charge-domain filters (CDF’s), w h s e advantage over conventional CCD filters is the ability to realize various infinite impulse response as well as finite impulse response filters.

Manuscript received March 15, 1984;revised June 7, 1984. Thiswork was supported by DARPA and RADC under Contract F19628-83-C- 0213. S. S. Bencuya was supported by the IBM Corporation under a VLSI Fellowship.

The authors are with the Center for Integrated Electronics, Rensaelaer Polytechnic Institute, Troy, NY 12181.

The basic concept of charge-domain devices is to perform all of the signal processing required strictly in the charge domain by manipulating the charge packets themselves rather than using the image charge on the overlying electrodes, as is done in other CCD signal processing devices 171, [8]. In CCD’s the charge packets representing the input signal can be split, routed, delayed, and combined to form new charge packets that represent the output signal. These charge-domain operations implement the functions required by sampled data signal processing, namely, delay and four-quadrant addition and multiplication [9].

With these operations, charge-domain devices have the capa- bility to realize recursive fdters without using any operational amplifiers that consume substantial silicon area and complicate the design and layout. The elimination of operational amplifiers minimizes the number of conversions between charge and voltage domains, thus reducing the noise and improving linearity. Furthermore, since charge-domain operations depend only on the geometry of the devices that accomplish them and not on the capacitance-voltage characteristics, buried-channel CCD technology can be used as well as the surface-channel technology. These and many other characteristics of charge-domain devices enable them to exceed the frequency handling capabilities of conventional charge-transfer signal processing devices [ 101 .

Charge-packet splitting, which is used to implement fractional multiplication of the signal by filter coefficients, is the basis of charge-domain signal processing. The concept of

0018-9383/84/1000-1494$01 .OO 0 1984 IEEE

BENCUYA AND STECKL: CHARGE-PACKET SPLITTING

..fj[B* piFl 0 : . - ONE

STAGE

Fig. 1. Charge packet splitting mechanism

charge-packet splitting is to physically divide the charge in a CCD register into fractions, and then manipulate each fraction independently as shown in Fig. 1. It should be noted that only coefficients less than unity can be obtained by this technique.

These filter coefficients must be implemented precisely since they determine various fdter characteristics. Therefore, it is important to determine and accurately control the factors thqt influence the accuracy of the charge-packet splitting operation.

11. PACKET SPLITTING TECHNIQUES

Charge-packet splitting uses the basic charge-transfer operation of CCDs, except that the receiving reservoir consists of two or more sections, whose relative sizes correspond to predetermined ratios and whose total capacitance is roughly equal to that of the source rese:rvoir. Once the charge has been split into portions, each individual portion can’ be carried on independently.

A simple method of performing unidirectional charge-packet splitting is to divide the main CCD channel &to predetermined components by inserting field-oxide barriers into the channel area. These barriers start at a certain location in the shift register and extend to the end of the register, isolating the receiving channels from each other. A charge packet that is transfered through this register is split into components proportional to the respective channels.

The splitting barriers can be constructed in several different configurations. First, the shape of the leading edge’af the barrier may be designed to come to a point, as shown in Fig. 2(a), creating a triangular edge, or may be truncated forming a square edge (blunt edge). Although the point edges become somewhat rounded by the end of the fabrication process, this feature is stiy very essential, since it shapes the electric field pattern in the vicinity of the barrier and minimizes the area of electron transfer path uncertainty. Therefore, the pointed-tip stiucture is expected to yield higher accuracy and lower noise. The configuration shown in Fig. 2(a) also has the CCD channel pinched in by half of $e barrier width from each side of the channel at the same gate that the barrier’s leading edge is located, establishing a structure that result8 in a more symmetrical electric field pattern.

The existence of transfer gates and storage gates in a CCD introduces two options for the placement of the barrier [ 111. If the leading edge of the barrier is positioned under the transfer gate as shown in Fig. 2(a), the‘qharge packet is split into two portions as it is being transferred from the source storage gate to the receiving storage gates. Since the potential in the transfer gate region is always higher’than that of the receiving

1495

FIELD OXIDE BARRIER

7\ I - -OXIDE FIELD

BARRIER

SPLIT RATIO 8 - AI

A2

@)

Fig. 2. Charge packet splitting techniques. (a) Dynamic splitting. (b) Pseudo-static splitting.

reservoir, the charge will not be able to back up around the barrier and equilibrate between the reservoirs. The split ratio of the charge packets resulting from this operation is equal to the width ratio of the transfer gates as determined by the position of the leading edge of the barrier. Since equilibration of charge carriers in @e receiving reservoirs does not take place during this process, this operation is cdled “dynamic

- - - - - charge-packet splitting.”

1496 IEEE TRANS’JLCTIONS ON ELECTRON DEVICES, VOL. ED-31, NO. 10, OCTOBER 1984

SPLIT RATIO + I : 2 2a

Fig 3. The use of dummy splitters.

In the case of the storage-gate splitting (Fig.. 2(b)), both barrier position and storage-gate areas affect the split r;.tio. The charge carriers that are transferred into the storage ;ate with the splitting barrier are distributed uniformly across the entire area prior to being split. In this case it is appropriat: to assume that during’the next clock cycle, carriers located to the right of the barrier (line B-B’ in Fig. 2(b)) will be transfe:’red to the corresponding independent channels, whereas car:t iers initially to the left of the barrier will be split dynamically within the same transfer cycle. Charge packets that result from the first process are proportional to the respective i:ate areas, whereas in the second case they are proportional to the respective channel widths. This operation is called “st3tic packet splitting.”

The lateral channel transconductance as a function of split position must also be taken into account in both of the above mechanisms, especially if due to time delay or threshold vi ria- tions channel turn-on is not simultaneous along its width.

Extra “dummy” barriers may be placed across the channel in order to obtain a more symmetrical electric field patterr at the gate where the split takes place. These splitters inserted into the channel with the actual coefficient barrier are placed with identical spacings and are only a few stages long (Fig. 3). The number of these barriers should be chosen appropriafely so that the incoming charge packet is divided into equal components by the set of barriers. Only one of these split charge packets is carried out separately, while all others are recom- bined after a few gates. By creating a symmetrical structtwe, these dummy splitters compensate nonlinearities due to ellge effects and equalize lateral forces applied to the charge carrilxs. For example, if the size of the gate area is less than its design value due to “bird’s beak” effect, the use of these equispamd barriers will cause all subchannels to be reduced equally :nd will maintain the proper splitting ratios. The same is truc if the effective channel width varies with the level of charge in the well.

One other technique of achieving charge-packet splitl: .ng in CDDs is the “ungated equilibration” method. This te1:h- nique is accomplished by connecting the output of a CCD register to the input of two or more CCD registers, as i.t is

DIFFUSION

SPLIT RATIO. 3 0 2

Fig. 4. Charge packet splitting by ungated equilibration.

shown in Fig. 4. The output diffusion of the initial register is connected to the input diffusions of the receiving registers by metal lines. The charge carriers are first equilibrated between the diodes, and then on the next clock cycle they are transfered to the potential wells of the corresponding registers. In this configuration, the ratio of the split charge packets is equal to the area ratio of the input diffusions.

111. EXPERIMENTS

Experimental circuits have been designed and fabricated to investigate the packet splitting accuracies of the above techniques. Circuits realizing three split ratios (1 : 1, 1 : 3, and 1 : 9) are implemented in two channel widths, 250 and 500 p, to investigate the dependance of split accuracy on coefficient value and channel width. The structure with the 1 : 9 ratio is repeated, again in two channel widths, but this time having eight dummy barriers along the actual one to determine the effect of these extra splitters on the coefficient accuracy. One other circuit having a 1 : 3 ratio uses a blunt barrier and serves the purpose of demonstrating the effect of the point edge splitters.

These experiments which are organized on chips A and B utilize the dynamic splitting technique, and are replicated onto chips C and D, but this time employing the static splitting technique. A microphotograph of one of the chips is given in Fig. 5. All four chips have a common pad and functional layout to simplify testing. These circuits have been fabricated using n-channel surface-channel double poly-silicon gate technology with a 12.5-pm gate length, 7.5-pm separation, and 10- pm-wide field-oxide barriers.

The input of the CCD registers is a modified “fill-and-spill” structure, having an additional dc-biased gate between the input diode and the reference gate for further noise isolation. The output of the CCD is connected to a “gated charge inte- grator.” The same output circuit is used for the two subpackets obtained from one original charge packet, thus eliminating possible output nonlinearities that could be introduced with

BENCUYA AND STECKL: CHARGE-PACKET SPLITTING 1497

Fig. 5. Microphotograph of one of the test chips.

=-l INPUTS

Fig. 6 . Output signal of the 1 : 9 split ratio experiment.

the use of two different output circuits. This is accomplished by having one of the registers a few cells (6) shorter than the adjacent register, providing a time delay between the two split charge packets. This is illustrated in Fig. 6 which shows the output of the 1 : 9 ratio experiment for a sequence of 5 ones and 22 zeroes.

The testing and characterization of the devices has been done by a computerized data acquisition system that performs time domain analysis. The block diagram of the experimental setup used is shown in Fig. 7. The output of the CCD is digitized and fed to a Motorola 6809 based computer. Most of the 12-bit A/D converters are limited to the 100-kHz region, and this requires a computerized sampling technique to capture all the data at the higher rates. The entire output waveform consists of a certain number of ones and zeroes specified by the operator. The peripheral digital circuitry built for these experiments triggers the sample-and-hold to hold the first pulse of the first waveform. This value is digitized and fed to the computer. Then, the digital board counts the output pulses and triggers the sample-and-hold when the second pulse of the

TIMING LOGIC

D 1; SUPPLIES

COUNTER

FI 12 BIT

I ' p y i 0

OSCILLOSCOPE

second waveform is available. This is repeated until the entire waveform is digitized and stored in the computer. If averaging of N waveforms is requested, then this whole procedure occurs N times and the computer stops taking data at the end of the Nth waveform. The advantage of the pulse response data analysis performed by this technique is to average the data

1498 IEEE TRANS/kCTIONS ON ELECTRON DEVICES, VOL. ED-31, NO. 10, OCTOBER 1984

over many cycles in order to improve the accuracy by avert ging out the noise components.

The four-phase CCD’s used in these experiments are operated in a one-and-a-half mode, that is two of the electrodes are clocked while the other two are at a dc level. The unidirectional charge flow is obtained by the different gate ulKide thicknesses of the lower and upper electrodes. The upper Airnit of device operation is set by capabilities of the clock dtive :s in driving a large capacitive load (300 pF).

IV. RESULTS AND DISCUSSION The fabricated circuits have been tested and characterited.

In general, it has been observed that the dynamic packet splitting method is much more accurate than the static splitting [12j. All the data presentedhere is taken from ex.?er- iments which employed dynamic splitting, unless otherlvise indicated.

The dc transfer functions at 1-MHz clock rate are shown in Fig. 8(a) for two 250-/.un channel circuits implemefiting the 1 : 9 ratio with and without dummy splitters. It can be seen that the overall circuit transfer function i’s extremely linea I in spite of the charge-packet splitting, and that the addition of the dummy barriers does not affect the linearity of the device. The reduction in dynamic range shown in Fig. 8(a) for the case of dummy splitters can be closely correlated to the CU:H~- tiponding reduction in active channel area. In the device w th- out the dummy splitters the maximum peak-to-peak inmt signal is 2.4 V. This would correspond to an imput dynztaic range of 80-100 dB given the normal noise sources in CCI9’s. In the case with the dummy splitters the maximum peakto- peak input signal drops to 1.3 V. This drop in dynamic range due to dummies is considerably less in the devices with 500-1m channel width (see Fig. 8(b)), since the area occupied by 1 he splitters is quite small with respect to the total channel area..

Fig. 9(a) and (b) gives the “pulse response” of the devE:es whose dc transfer curves are given in Fig. 8(a). This technj,c!ue identifies the transfer characteristics of the two split registers of each device and shows their linear and dynamic ranges. A number of interesting features of the pulse response are (:‘.is- cussed. In the case without dummy splitters (Fig. 9(a)), lhe pulse output of the small-coefficient channel saturates at lower input voltage than the large-coefficient channel. The charge packet is contained by a potential weli which is not rectangular but has sloping sides at the channel edges. The narrower the channel, the more pronounced is this effect on the saturation level. Beyond the saturation region level lor the “I” channel, an increased level of charge appears at t h,e output of the “9” channel, slightly modifying the ratio of the coefficients. As expected, the sum of the two outpl.Lts remains linear with the input voltage. For the wider 500-1,m channel, the output saturation level occurs at roughly tine same input pulse voltage.

By comparison, this edge effect is equally present in bo.:h channels when dummy splitters are introduced (Fig. 9(b:), because the electric field, and therefore the potential .wc:ll pattern, is completely symmetric. Consequently the over2 11 saturation with dummies present takes place at the saturaticn level of the narrow channel.

CHFWNEL UIDTH - 250 pm CLOCK FREWENCY - 1 MHz * 119 w/D + 119 u/D

CHFWNEL UIDTH - 250 pm CLOCK FREWENCY - 1 MHz * 119 w/D + 119 u/D

CIYWNEL UIDTH - 5W pm CLOCK FREWNCY = 1 MI 8 1:9 uo/D + 189 u/D

a 1.m 1.9 2.w 2.50 3.00 3.50 4.M , 4.s

INPUT (VI

cb) Fig. 8. dc transfer curves of the devices realizing 1 : 9 split ratio with

(+) and without (*) dummy splitters. (a) Channel width = 250 pm. (b) Channel width = 500 pm.

The transfer inefficiency of the experimental circuits imple- menting the 1 : 9 split ratio is shown in Fig. lO(a) and (b) as a function of clock frequency. The total transfer inefficiency measured combines the transfer losses experienced by the full channel (before packet splitting occurs), with losses in the subchannels defined by the barrier. The data shown in Fig. 10 represent the overall transfer inefficiency. A 20-percent fat zero was used in all cases and the signal packet size was chosen such that no spillover occured in the smallest channel.

Fig. 1 O(a) shows the tranfer inefficiency for the split registers of the 250-pm (total) channel width experiment. The split registers with 0.1 coefficient have transfer inefficiencies of the order of 1 X up to a frequency of 1 MHz. For frequencies higher than 1 MHz, the transfer inefficiency increases.


CHRNNEL UIDTH - 250 pm

0 '1+9' OUTPUT CLOCK FREOUENCY - 1 RHz

* "1' OUTPUT + '9' OUTPUT

0.0

CHANNEL UIDTH - 250 p n CLOCK FREOUENCY - I tiHz 0 *1+9' W T W T + '9' W T W * '1' W T W T

/ / 0 0.a 0.40 0.p

INPUT I%E ( V t m 1.20 1.40 1.a

0) Fig. 9. Pulse transfer curves. (a) 1 : 9 split ratio; channel width =

250 pm. (b) 1 : 9 split ratio with dummies; channel width = 250 pm.

The 0.9 portion of these same registers have transfer inefficiencies of about 2 X at low frequencies. The narrow registers (0.1 registers) of these circuits have the smallest level output voltages. After the split, these narrow channels con- t,inue for 5 cells only. The first of these is actually only 15 p wide due to area loss to the charge barrier. In addition, the width of all of these 5 cells is reduced by the "bird's beak" effect of the isoplanar process. Furthermore, fat zero is more effective in improving the transfer inefficiency of narrow channels where a relatively more pronounced edge effect is present. These combined effects are the probable cause of the observed high transfer inefficiency in the registers implement- ing the 0.1 coefficients. Furthermore, even for transfer inefficiencies as high as lo-", the A V measured in the 25-pm (nominal channel was of the order of 3 mV. This is only a

.I

7

2 3 1 5 6 1 0 9 ' 2 3 1 5 6 1 0 9 ' 4-H

2 3 4 5 8 7 8 ( 1~105

FREOUENCY (Hz) 81D8

Fig. 10. Experimentally obtained transfer inefficiencies as a function of clock frequency. (a) 1 :9 split ratio with and without dummy splitters; channel width = 250 pm. (b) 1 : 9 split ratio with and without dummy splitters; channel width = 500 pm.

factor of 2 to 3 higher than the noise level of the AID con- verter. Therefore, a fair amount of noise was present in some of the data even though the signal was averaged over 2000 samples.

The difference in transfer efficiency for the various other coefficients (0.25, 0.50, 0.75) implemented again with 250-pm total channel width is less than the case (0.10,0.90) shown in Fig. lO(a). This is due to the fact that even the smallest coefficient (0.25) has a reasonably wide channel (52.5 pm).

Fig. 10(b) shows the transfer inefficiency curves for the devices with 5 0 0 - p total channel width and 1 : 9 split ratio. In the case of the small coefficient (0.10), the doubling of the channel width results in a decrease of the transfer inefficiency by a factor of two. For the other coefficient, the increase in

1500 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-31, NO. 10, OCTOBER 1984

channel width has only a minimal effect on the trtmsfer inefficiency. As with the 250-pm channel, the effect clf the dummy splitters is essentially negligible.

Transfer inefficiency in all of the previously ment Imed devices starts to increase considerably after 1-MHz :lock frequency, but does not exceed 2.5 X at 2 MHz.

The experimental values of most of the coefficients inple- mented with 250- and 500-prn channel widths are deternlined as a function of clock frequency. It was observed that the basic value of all coefficients is essentially constant with frequ1:ncy. Since the accuracy required for practical applications is q,uite high, however, the coefficient error was examined in some detail. The errors in the coefficients are given in Fig. 1 J.(a), (b), and (c). These coefficient errors are calculated in the following manner. For example, in the 1 :9 split ratio experiment, the implemented coefficients would be 0.1 and O.'?. If the measured coefficients are 0.099 and 0.901, then the ':rror in the coefficients is 0.001 and corresponds to about a IO-bit equivalent accuracy.

The measured coefficient errors in the 1 : 9 split ratio e:::per- iments are shown in Fig. 1 l(a). With a 250-/.m channel 'A idth the coefficient error is of the order of 0.01, correspondiitlg to better than 6-bit equivalent accuracy. The introduction o ' the dummy splitters in this case decrease this error to app:oxi- mately 0.005-0.006, an improvement of about 1-bit acculacy. Increasing the channel width to 500 prn drastically lower:; the coefficient error to the range or approximately 10-bit accuracy. Once again, adding dummy splitters increases the accuracy by more than 1 bit. The coefficient errors for the devices realizing 1 : 3 and 1 : 1 split ratio are shown in Fig. 1 1 (b). The 1 : 3 split ratio implemented with the regular point odge technique is approximately 4 bits more accurate when com- pared to the ungated equilibration method. The ungited equilibration method has the largest coefficient error. The charge-packet splitting mechanism in this case is more com- plicated than the regular barrier splitting. Although the s'plit ratio is determined by the ratio of the input diodes, the clocks on each side of the diodes also affect the packet splitting.

The best results are obtained in the 1 : 1 case as expec led, with errors in the order of 0.0002-0.0003 (12-bit equiva ent accuracy) up to 1-MHz clock frequency. Below 1 MHz the dominant error sources present in this experiment are split :ing noise introduced during charge-packet splitting and coeffic:ent error introduced during the fabrication of the circuits. Above 1-MHz clock frequency, transfer inefficiencies and char ne1 turn-on delays apparently become the major sources of ex.or. The sharp increase with frequency is not observed in the other devices since other error sources such as edge effects dominate the coefficient error. It should be noted that the 1 : 3 split r;.tio structure (with the point edge split but without dummies) is more accurate than the structure with 1 : 9 split ratio m d dummy splitters. This result is somewhat surprising as the '.at- ter structrue should have a more symmetrical field pattern.. A possible explanation can be that the large number and c lxe spacing of dummies generate sufficient splitting noise to dc m- inate the coefficient error, and that dummy barriers can Ojdy compensate partially for edge effects and lateral field oxtde growth.

-.I

if -I

i/

t'

tctf 2 3 4 5 1 7 8 9 1 2 3 4 5 6 7 9 9 '

t: : l.l@ l X l o 5 1.106

FREOUENCY (Hz)

/

:t I -t

2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 x:

1r.d 2 3 4 5 e 7 9 9

l.l+ FREOUENCY (Hz1

1.106 lxlQ7

(c 1 Fig. 11. Coefficient error as a function af clock frequency. (a) 1 : 9

split ratio. (b) 1 :3 and 1 : 1 split ratio; channel width = 250 fim. (c) 1 : 3 split ratio; channel width = 500 pm.


rical configuration obtainable with the point-edge barrier.

V. CONCLUSIONS 111

The accuracies of the coefficients implemented with the above techniques are generally high enough (6-12 bit equivalent accuracy) to build high-performance signal processing devices. Highest accuracies are obtained in devices with wide channels using point edge and dummy barriers, and with coef- [31 ficient ratios close to unity. [41

The error sources that affect coefficient accuracy are: non- uniform electric field pattern, delays in channel turn-on, threshold variations along the channel, isotropic etching of the nitride layer, lateral growth of the field oxide, and the intrinsic potential well nonuniformity at the edges of the channel (edge f51 effects). [6 I

Introduction of dummy barriers creates a symmetrical electric field pattern, and also partly compensates for edge effects 171 and the bird’s beak problems. This compensation is especially more effective in the narrow-channel devices. The lateral [81 growth of the field oxide into the channel must also be measured and compensated for during the mask design. Alterna- 191 tively, better edge defin.ition techniques such as anisotropic etching or implanted barriers could also be used. Since the wide channel provides better results than the narrow channel, [ l o ] it is apparent that structure size variations are more important than threshold variations which should be larger for wider devices. The optimum splitting barriers should have a point edge and should be as narrow as the fabrication technology allows.

These techniques are also applicable to burried-channel technology, and therefore accurate charge-packet splitting can also be obtained at very high frequencies.

[21

1111

[I21

REFERENCES J. R. Hill, D. V. McCaughan, J. M. Keen, and J. C. White, “Charge- splitting CCD tapped delay lines,” Electron. Lett., vol. 15, no. 7, pp. 204-206, Mar. 29, 1979. J. J. Tiemann, T. L. Vogelsong, and A. J. Steckl, “Charge domain recursive filters,” in ZSSCC Dig. Tech. Papers, pp. 96-97, Feb. 1980. M. Feldmann and J. Henaff, “New charge transfer recursive filters,’’ Electron. Lett., vol. 16, no. 15, July 17, 1980. H. Mar, M. Mathue, H. J. Pfleiderer, 0. Poenisch, and F. Kune- mund, “Passive recursive CCD filters, Part I: Basic circuit configuration,” in Proc. Znt. Symp. Circuits Systems, pp. 1039-1040, 1980; R. Schreiber, A. Bardl, H. Betz1,M. Feil, andF. Kunemund, “Passive recursive CCD fiiters, Part 11: Bandselect filters,”in Proc. Znt. Symp. Circuits Systems, pp. 1041-1042, 1980. J. J. Tiemann, T. L. Vogelsong, and A. J. Steckl, “Charge domain analog sampled data filters,” in Proc. Eascon, Sept. 1980.

ZEEE J. Solid-state Circuits, vol. SC-17, no. 3, June 1982. D. R. Collins, W. H. Bailey, W. M. Gosney, and D. D. Buss, “Charge coupled device analogue matched filters,” Electron. Lett., vol. 8, pp. 328-329, 1972. D. D. Buss, D. R. Collins, W. H. Bailey, and C. R. Reeves, “Trans- versal filtering using charge transfer devices,” ZEEE J. Solid-state Circuits, vol. SC-8, pp. 138-146, Apr. 1973. T. L. Vogelsong, “The design of a charge domain filter,” masters thesis, Rensselaer Polytechnic Inst., May 1979; --, ‘:Charge domain integrated circuits for signal processing, Ph.D. dissertation, Rensselaer Polytecnic Inst., Dec. 1983. T. L. Vogelsong, J. J. Tiemann, and A. J. Steckl, “A high Q band- pass filter demonstrating charge domain technology,” in IEDM Dig. Tech. Papers, pp. 127-129, Dec. 1982. S. S. Bencuya, A. J. Steckl, T. L. Vogelsong, and J. J. Tiemann, “Dynamic packet splitting in charge domain devices,” IEEE Electron Device Lett., vol. EDL-3, no. 9, pp. 268-270, Sept. 1982. S. S. Bencuya, A. J. Steckl, and T. L. Vogelsong, “Coefficient accuracy for CDD packet splitting techniques,” in ZEDM Dig Tech. Papers, pp. 123-126, Dec. 1982.

- , “Fundementals and operation of charge domain filters,”

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Charge-packet splitting in charge-domain devices