Chapter05-2UP(2_25_03)

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Chapter 5 – Introduction (2/25/03) Page 5.0-1

CMOS Analog Circuit Design © P.E. Allen - 2003

CHAPTER 5 – CMOS AMPLIFIERS

Chapter Outline

5.1 Inverters

5.2 Differential Amplifiers

5.3 Cascode Amplifiers

5.4 Current Amplifiers

5.5 Output Amplifiers5.6 High-Gain Architectures

Goal

To develop an understanding of the amplifier building blocks used in CMOS analogcircuit design.

Design Hierarchy

Blocks or circuits

(Combination of primitives, independent)

Sub-blocks or subcircuits

(A primitive, not independent)

Functional blocks or circuits

(Perform a complex function)

Fig. 5.0-1

Chapter 5



Illustration of Hierarchy in Analog Circuits for an Op Amp

Operational Amplifier

Biasing

Circuits

Input

Differential

Amplifier

Second

Gain

Stage

Output

Stage

Current

Source

Current

Mirrors

Current

Sink

Current

Mirror Load

Inverter Current

Sink Load

Source

Follower

Current

Sink LoadSource

Coupled Pair

Fig. 5.0-2

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Active Load Amplifiers

What is an active load amplifier?

V DD

Fig320-01

V CC

I Bias

+

-

V T +

2V ON

V T +V ON +

-

V T +V ON +-

+

-

V T +

2V ON

I Bias

+

-V EB

V EB +

V EC (sat)

+

-

+-

V BE

V BE +

V CE (sat)

+

-

MOS Loads BJT Loads

MOS Transconductors BJT Transconductors

I Bias I Bias

It is a combination of any of the above transconductors and loads to form an amplifier.

(Remember that the above are only some of the examples of transconductors and loads.)

Chapter 5 – Section 1 (2/25/03) Page 5.1-1


SECTION 5.1 - CMOS INVERTING AMPLIFIERS

Characterization of AmplifiersAmplifiers will be characterized by the following properties:

• Large-signal voltage transfer characteristics

• Large-signal voltage swing limitations

• Small-signal, frequency independent performance

- Gain

- Input resistance

- Output resistance

• Small-signal, frequency response• Other properties

- Noise

- Power dissipation

- Etc.

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Large-Signal Voltage Swing Limits of the Active Load Inverter

Maximum output voltage, vOUT (max):

vOUT (max) ≅ V DD - |V TP|

(ignores subthreshold current influence on the MOSFET)

Minimum output voltage, vOUT (min):

Assume that M1 is nonsaturated and that V T 1 = |V T 2| = V T .v DS 1 ≥ vGS 1 - V TN → vOUT ≥ v IN - 0.7V

The current through M1 is

i D = β 1

(vGS 1 − V T )v DS 1 − v 2 DS 1

2 = β 1

(V DD − V T )(vOUT ) − (vOUT )2

2

and the current through M2 is

i D = β 22 (vSG2 − V T )2 =

β 22 (V DD − vOUT − V T )2 =

β 22 (vOUT + V T − V DD)2

Equating these currents gives the minimum vOUT as,

vOUT (min) = V DD − V T − V DD − V T

1 + (β 2 / β 1)



Small-Signal Midband Performance of the Active Load Inverter

The development of the small-signal model for the active load inverter is shown below:

M2

M1v IN

vOUT I D

V DD

gm2vgs2

gm1vgs1

r ds2

r ds1

+

-

vin

G1 D1= D2=G2

S 1= B1

S 2= B2

+

-

vout gm1vin r ds1

+

-

vin

+

-

vout gm2vout r ds2

Rout

Fig. 320-03

Sum the currents at the output node to get,gm1vin + gds1vout + gm2vout + gds2vout = 0

Solving for the voltage gain, vout / vin, gives

vout

vin =

−gm1

gds1 + gds2 + gm2 ≅ −

gm1

gm2 = −

K' N W 1 L2

K' P L1W 21/2

The small-signal output resistance can also be found from the above by letting vin = 0 to

get,

Rout = 1

gds1 + gds2 + gm2 ≅

1gm2

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Frequency Response of the MOS Diode Load Inverter

Incorporation of the parasiticcapacitors into the small-signalmodel:

If we assume the input voltage has asmall source resistance, then we canwrite the following:

sC M (V out -V in) + gmV in

+ Gout V out + sC out V out = 0

∴ V out (Gout + sC M + sC out ) = - (gm – sC M )V in

V out

V in =-(gm – sC M )

Gout + sC M + sC out = -gm Rout

1-sC M

gm

1+ sRout (CM + C out ) =

−gm Rout

1 -s

z1

1 -s

p1

where

gm = gm1, p1 = −1

Rout (C out +C M ) , and z1 =gm1

C M

and

Rout = [gds1+gds2+gm2]-1 ≅ 1

gm2 , C M = C gd 1 , and C out = C bd 1+C bd 2+C gs2+C L

Fig. 320-04C gs1

C gd 1

C gs2

C bd 2

C bd 1

V DD

V in

V out

C L

M2

M1

C M

C out Rout V out

+

-

V in gmV in

+

-



Frequency Response of the MOS Diode Load Inverter - Continued

If | p1| < z1, then the -3dB frequency is approximately equal to [ Rout (C out +C M )]-1.dB

20log10(gm Rout )

0dB| p1| ≈ ω-3dB

log10 f z1

Fig. 5.1-4A

Observation:

The poles in a MOSFET circuit can be found by summing the capacitance connectedto a node and multiplying this capacitance times the equivalent resistance from this nodeto ground and inverting the product.

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Example 5.1-1 - Performance of an Active Resistor-Load Inverter

Calculate the output-voltage swing limits for V DD = 5 volts, the small-signal gain, theoutput resistance, and the -3 dB frequency of active load inverter if (W1 /L1) is 2 µm/1 µmand W2 /L2 = 1 µm/1 µm, C gd 1 = 100fF, C bd 1 = 200fF, C bd 2 = 100fF, C gs2 = 200fF, C L = 1pF, and I D1 = I D2 = 100µA, using the parameters in Table 3.1-2.

Solution

From the above results we find that:vOUT (max) = 4.3 volts

vOUT (min) = 0.418 volts

Small-signal voltage gain = -1.92V/V

Rout = 9.17 k Ω including gds1 and gds2 and 10 k Ω ignoring gds1 and gds2

z1 = 2.10x109 rads/sec

p1 = -64.1x106 rads/sec.

Thus, the -3 dB frequency is 10.2 MHz.



Voltage Transfer Characteristic of the Current Source Inverter

0 1 2 3 4 5

I D ( m A )

vOUT

0 1 2 3 4 5

v O U T

vIN

M2

M1

v IN

vOUT

I D

5V

+

-

+

-

W2L2

=2µm1µm

W1L1

= 2µm1µm

Fig. 5.1-5

C

M2

2.5V

A B C

D

E

G H I K

FJ

1

0

2

3

4

5

M2 saturated

EHIKJ

G

F

M2 active

M 1 a c t i v

e

M 1 s a t u r

a t e d

v IN =5.0V v IN =4.0Vv IN =4.5V

v IN =1.0V

v IN =1.5V

v IN =2.0V

v IN =2.5V

0.0

0.1

0.2

0.3

0.4

0.5v IN =3.5Vv IN =3.0V

D

A,B

Regions of operation for the transistors:

M1: v DS 1 ≥ vGS 1 -V Tn → vOUT ≥v IN - 0.7VM2: vSD2 ≥ vSG2 - |V Tp| → V DD - vOUT ≥V DD -V GG2 - |V Tp| → vOUT ≤ 3.2V

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Large-Signal Voltage Swing Limits of the Current Source Load Inverter

Maximum output voltage, vOUT (max):

vOUT (max) ≅ V DD


Assume that M1 is nonsaturated. The minimum output voltage is,

vOUT (min) = vOUT (min) = (V DD - V T 1)

1 - 1 -

β 2

β 1

V DD - V GG - |V T 2|

V DD - V T 1

2

This result assumes that v IN is taken to V DD.



Small-Signal Midband Performance of the Current Source Load Inverter

Small-Signal Model:

M2

M1v IN

vOUT I D

V DD

gm1vgs1

r ds2

r ds1

+

-

vin

G1 D1= D2

S 1= B1=G2

S 2= B2

+

-

vout gm1vin r ds1

+

-

vin

+

-

vout r ds2

Rout

Fig. 5.1-5B

V GG2

Midband Performance:

vout

vin = −gm1

gds1 + gds2 =

2K' N W 1

L1 I D1/2

−1

λ 1 + λ 2 ∝ 1Ι D

!!! and Rout = 1gds1 + gds2

≅ 1 I D(λ 1 + λ 2)

0.1µA 1µA 10µA 100µA 1mA 10mA

10

Amax

log| Av|

Weak

inversion

Strong

inversion

I D

Fig. 5.1-6

Amax

100 Amax

1000 Amax

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Frequency Response of the Current Source Load Inverter

Incorporation of the parasiticcapacitors into the small-signalmodel ( x is connected to V GG 2):

If we assume the input voltagehas a small source resistance,

then we can write the following:

V out(s)V in(s) =

−gm Rout

1 -s

z1

1 -s

p1

where gm = gm1, p1 = −1

Rout (C out +C M ) , and z1 =

gm

C M

and Rout = 1

gds1 + gds2 and C out = C gd 2 + C bd 1 + C bd 2 + C L C M = C gd 1

Therefore, if | p1|<| z1|, then the −3 dB frequency response can be expressed as

ω -3dB ≈ ω 1 = gds1 + gds2

C gd 1 + C gd 2 + C bd 1 + C bd 2 + C L

C gd 2

C gd 1

C gs2

C bd 2

C bd 1

V DD

V in

V out

C L

M2

M1

C M

C out Rout

V out

+

-

V in gmV in

+

-

Fig. 5.1-4

x



Example 5.1-2 - Performance of a Current-Sink Inverter

A current-sink inverter is shown in Fig. 5.1-7. Assumethat W 1 = 2 µ m, L1 = 1 µ m, W 2 = 1 µ m, L2 = 1µ m, V DD = 5volts, V GG1 = 3 volts, and the parameters of Table 3.1-2describe M1 and M2. Use the capacitor values of Example5.1-1 (C gd 1 = C gd 2). Calculate the output-swing limits andthe small-signal performance.

Solution

To attain the output signal-swing limitations, we treatFig. 5.1-7 as a current source CMOS inverter with PMOS parameters for the NMOS andNMOS parameters for the PMOS and use NMOS equations. Using a prime notation to

designate the results of the current source CMOS inverter that exchanges the PMOS andNMOS model parameters,

vOUT (max)’ = 5Vand vOUT (min)’ = (5-0.7)

1 - 1 -

110·1

50·2

3-0.7

5-0-0.72 = 0.74V

In terms of the current sink CMOS inverter, these limits are subtracted from 5V to get

vOUT (max) = 4.26V and v OUT (min) = 0V.

To find the small signal performance, first calculate the dc current. The dc current, I D, is

I D =K N ’W 1

2 L1 (V GG 1-V TN )2 =

110·12·1 (3-0.7)2 = 291µA

vout / vin = −9.2V/V, Rout = 38.1 k Ω, and f -3dB = 2.78 MHz.

V DD

vOUT

v IN M1

M2

V GG1

Figure 5.1-7 Current sink CMOS inverter.

ID

+

-V SG1

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Voltage Transfer Characteristic of the Push-Pull Inverter

0 1 2 3 4

I D ( m A )

vOUT

0 1 2 3 4 5

v O U T

vIN

M2

M1

v IN

vOUT

I D

5V

+

-

+

-

W2L2

=2µm1µm

W1

L1=

1µm

1µm

Fig. 5.1-8

0.0

0.2

0.4

0.6

0.8

1.0

v IN =1.0V

v IN =1.5V

v IN =2.0V

v IN =2.5V

v IN =3.0V

A B C D

E

GH I K

F

J

v IN =5.0V v IN =4.0Vv IN =4.5V

v IN =3.5V

E

D

F

GHI

v IN =3.0V

2

3

4

1

0

M 2 a c t

i v e

M 2 s

a t u r a t

e d M

1 a c t i v e

M 1 s

a t u r a t

e d

CA,B 5

v IN =4.5Vv IN =3.5V

v IN =2.5V

J,K

v IN =2.0V

v IN =0.5Vv IN =1.0V

v IN =1.5V

Note

the rail-

to-rail

output

voltage

swing

Regions of operation for M1 and M2:

M1: v DS 1 ≥ vGS 1 - V T 1 → vOUT ≥ v IN - 0.7V

M2: vSD2 ≥ vSG2-|V T 2| → V DD -vOUT ≥ V DD -v IN -|V T 2| → vOUT ≤ v IN + 0.7V



Small-Signal Performance of the Push-Pull Amplifier

gm1vin r ds1 gm2vin r ds2

+

-

vin

+

-

vout

Fig. 5.1-9

C out

C M

M2

M1

5V

+

-

+

-

vinvout

Small-signal analysis gives the following results:

vout

vin =

−(gm1 + gm2)gds1 + gds2

= − (2/ I D)

K' N (W 1 / L1) + K' P(W 2 / L2)

λ 1 + λ 2

Rout = 1gds1 + gds2

z =gm1+gm2

C M =

gm1+gm2

C gd 1+C gd 2

and

p1 = −(gds1 + gds2)

C gd 1 + C gd 2 + C bd 1 + C bd 2 + C LIf z1 > | p1|, then

ω -3dB = gds1 + gds2

C gd 1 + C gd 2 + C bd 1 + C bd 2 + C L

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Example 5.1-3 - Performance of a Push-Pull Inverter

The performance of a push-pull CMOS inverter is to be examined. Assume that W 1 =1 µ m, L1 = 1 µ m, W 2 = 2 µ m, L2 = 1µ m, V DD = 5 volts, and use the parameters of Table3.1-2 to model M1 and M2. Use the capacitor values of Example 5.1-1 (C gd 1 = C gd 2).Calculate the output-swing limits and the small-signal performance assuming that I D1 =

I D2 = 300µA.

SolutionThe output swing is seen to be from 0V to 5V. In order to find the small signalperformance, we will make the important assumption that both transistors are operatingin the saturation region. Therefore:

vout

vin =

-257µS - 245µS12µS + 15µS = -18.6V/V

Rout = 37 k Ω

f -3dB = 2.86 MHz

and

z1 = 399 MHz



Noise Analysis of Inverting Amplifiers

Noise model:

en22

en12

M2

M1

Noise

Free

MOSFETs

eout 2

V DD

vin

eeq2

M2

M1

Noise

Free

MOSFETs

eout 2

V DD

vin

Fig. 5.1-10

*

*

*

Approach:

1.) Assume a mean-square input-voltage-noise spectral density en2 in series with the

gate of each MOSFET.(This step assumes that the MOSFET is the common source configuration.)

2.) Calculate the output-voltage-noise spectral density, eout 2 (Assume all sources are

additive).

3.) Refer the output-voltage-noise spectral density back to the input to get equivalent

input noise eeq2.

4.) Substitute the type of noise source, 1/f or thermal.

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Noise Analysis of the Active Load Inverter

1.) See model to the right.

2.) eout 2 = en1

2

gm1

gm2

2+ en22

3.) eeq2 = en1

2

1 +

gm2

gm1

2

en2

en1

2

Up to now, the type of noise is not defined.

1/f Noise

Substituting en2=KF

2 fC oxWLK’ = B

fWL , into the above gives,

eeq(1/ f ) =

B1

fW 1 L1

1/2

1 +

K '2 B2

K '1 B1

L1

L2

2 1/2

To minimize 1/f noise, 1.) Make L2>> L1, 2.) increase the value of W 1 and 3.) choose M1

as a PMOS.

Thermal Noise

Substituting en2=

8kT

3gm into the above gives,

eeq(th) =

8kT

3[2K '1(W / L)1 I 1]1/2

1+

W 2 L1K '2

L2W 1K '11/2 1/2

To minimize thermal noise, maximize the gain of the inverter.

en22

en12

M2

M1

Noise

Free

MOSFETs

eout 2

V DD

vin

eeq2

M2

M1

Noise

Free

MOSFETs

eout 2

V DD

vin

Fig. 5.1-10

*

*

*



Noise Analysis of the Active Load Inverter - Continued

When calculating the contribution of en22 to eout 2, it was assumed that the gain wasunity. To verify this assumption consider the following model:

en22

gm2vgs2 r ds1vgs2

+

-

r ds2 eout 2

+

_

Fig. 5.1-11

*

We can show that,

eout 2

en22 =

gm2(r ds1||r ds2)

1 + gm2(r ds1||r ds2) 2 ≈ 1

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Noise Analysis of the Current Source Load Inverting Amplifier

Model:

en22

en12

M2

M1

Noise

Free

MOSFETs

eout 2

V DD

vineeq

2

M2

M1

Noise

Free

MOSFETs

eout 2

V DD

vin

Fig. 5.1-12.

V GG2

*

* *

The output-voltage-noise spectral density of this inverter can be written as,

eout 2 = (gm1r out )2en1

2 + (gm2r out )2en22

or

eeq2 = en1

2 +(gm2r out )2

(gm1r out )2en22 = en1

2

1 +

gm2

gm1

2 en2

2

en12

This result is identical with the active load inverter.Thus the noise performance of the two circuits are equivalent although the small-signalvoltage gain is significantly different.



Noise Analysis of the Push-Pull Amplifier

Model:

en22

en12

V DD

M2

M1

eout 2vin

Noise

Free

MOSFETs

Fig. 5.1-13.

*

*

The equivalent input-voltage-noise spectral density of the push-pull inverter can be foundas

eeq =

gm1en1

gm1 + gm2 2 +

gm2en2

gm1 + gm2 2

If the two transconductances are balanced (gm1 = gm2), then the noise contribution of

each device is divided by two.

The total noise contribution can only be reduced by reducing the noise contribution of each device.

(Basically, both M1 and M2 act like the “load” transistor and “input” transistor, sothere is no defined input transistor that can cause the noise of the load transistor to beinsignificant.)

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Summary of CMOS Inverting Amplifiers

InverterAC Voltage

GainAC OutputResistance

Bandwidth (CGB=0)Equivalent,

input-referred,mean-square noise voltage

p-channelactive loadinverter

-gm1gm2

1gm2

gm2CBD1+CGS1+CGS2+CBD2

en12 + en2

2

gm2

gm12

n-channel

active loadinverter

-gm1gm2+gmb2 1

gm2+gmb2

gm2+gmb2CBD1+CGD1+CGS2+CBS2

en12 + en2

2

gm2

gm12

Currentsource loadinverter

-gm1gds1+gds2

1gds1+gds2

gds1+gds2CBD1+CGD1+CDG2+CBD2

en12 + en2

2

gm2

gm12

n-channeldepletion

load inverter ~-gm1gmb2

1gmb2+gds1+gds2

gmb2+gds1+gds2CBD1+CGD1+CGS2+CBD2

en12 + en2

2

gm2

gm12

Push-Pullinverter

-(gm1+gm2)gds1+gds2 1

gds1+gds2

gds1+gds2CBD1+CGD1+CGS2+CBD2

gm1en1

gm1+ gm2

2+

gm1en1

gm1+ gm2

2

Inverting configurations we did not examine.



SECTION 5.2 - DIFFERENTIAL AMPLIFIERS

What is a Differential Amplifier?A differential amplifier is an amplifier that amplifies the

difference between two voltages and rejects the average orcommon mode value of the two voltages.

Differential and common mode voltages:

v1 and v2 are called single-ended voltages. They are

voltages referenced to ac ground.

The differential-mode input voltage, v ID, is the voltage difference between v1 and v2.

The common-mode input voltage, v IC , is the average value of v1 and v2 .

∴ v ID = v1 - v2 and v IC =v1+v2

2 ⇒ v1 = v IC + 0.5v ID and v2 = v IC - 0.5v ID

vOUT = AVDv ID ± AVC v IC = AVD(v1 - v2) ± AVC

v1 + v2

2

where

AVD = differential-mode voltage gain

AVC = common-mode voltage gain

+

- +

vOUT

-

+

v1

-

+

-

v2

Fig. 5.2-1A

+

- +

vOUT

-

v IC

v ID2

v ID2

Fig. 5.2-1B

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Differential Amplifier Definitions

• Common mode rejection rato (CMRR)

CMRR =

AVD

AVC

CMRR is a measure of how well the differential amplifier rejects the common-modeinput voltage in favor of the differential-input voltage.

• Input common-mode range ( ICMR)

The input common-mode range is the range of common-mode voltages over whichthe differential amplifier continues to sense and amplify the difference signal with thesame gain.

Typically, the ICMR is defined by the common-mode voltage range over which allMOSFETs remain in the saturation region.

• Output offset voltage (V OS (out))

The output offset voltage is the voltage which appears at the output of the differentialamplifier when the input terminals are connected together.

• Input offset voltage (V OS (in) = V OS )

The input offset voltage is equal to the output offset voltage divided by the differentialvoltage gain.

V OS =V OS (out)

AVD



Transconductance Characteristic of the Differential Amplifier

Consider the following n-channel differentialamplifier (sometimes called a source-coupledpair):

Where should bulk be connected? Consider ap-well, CMOS technology,

; y

D1 G1 S1

; y

S2 G2 D2

n+ n+ n+ n+ n+p+

p-well

n-substrate

V DD

Fig. 5.2-3

1.) Bulks connected to the sources: No modulation of V T but large common mode

parasitic capacitance.

2.) Bulks connected to ground: Smaller common mode parasitic capacitors, butmodulation of V T .

If the technology is n-well CMOS, there is no choice. The bulks must be connected toground.

I Bias

i D1 i D2

V DD

VBulk

M1 M2

M3M4 I SS

+

-

vG1

vGS 1+

-vGS 2

vG2

Fig. 5.2-2

v ID

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Transconductance Characteristic of the Differential Amplifier - Continued

Defining equations:

v ID = vGS 1 − vGS 2 =

2i D1

β 1/2

−

2i D2

β 1/2

and I SS = i D1 + i D2

Solution:

i D1 = I SS

2 + I SS

2

β v

2ID

I SS −

β 2v4ID

4 I

2

SS

1/2and i D2 =

I SS

2 − I SS

2

β v

2ID

I SS −

β 2v4ID

4 I

2

SS

1/2

which are valid for v ID < 2( I SS / β )1/2.

Illustration of the result:

Differentiating i D1 (or i D2)

with respect to v ID and

setting V ID =0V gives

gm = di D1

dv ID(V ID = 0) = (β I SS /4)1/2 =

K '1 I SS W 1

4 L1

1/2 (half the gm of an inverting amplifier)

i D /I SS

0.8

0.2

0.0

1.0

0.6

0.4

1.414 2.0-1.414-2.0

v ID(I SS /ß)0.5

i D1

i D2

Fig. 5.2-4



Voltage Transfer Characteristic of the Differential Amplifier

In order to obtain the voltage transfer characteristic, a load for the differential amplifiermust be defined. We will select a current mirror load as illustrated below.

V Bias

I SS

M1 M2

M3 M4

V DD

M5

vGS 1+

-vGS 2

+

-

vG2

-

vOUT

iOUT

vG1

-

i D1 i D2

i D3 i D4

-

+

Fig. 5.2-5

2µm1µm

2µm1µm

2µm1µm

2µm1µm

2µm1µm

V DD2

Note that output signal to ground is equivalent to the differential output signal due to thecurrent mirror.

The short-circuit, transconductance is given as

gm = diOUT

dv ID (V ID = 0) = (β I SS )1/2 =

K '1 I SS W 1

L1

1/2

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Voltage Transfer Function of the Differential Amplifer with a Current Mirror Load

Fig. 330-01

V Bias

I SS

M1 M2

M3 M4

V DD

M5

vGS 1+

- vGS 2+

-

vG2

-

vOUT

iOUT

vG1

-

i D1 i D2

i D3 i D4

-

+2µm1µm

2µm1µm

2µm1µm

2µm1µm

2µm

1µm

0

1

2

3

4

5

-1 -0.5 0 0.5 1v ID (Volts)

v O U T ( V o l t s )

M2 saturated

M2 active

M4 activeM4 saturated

V IC = 2V

= 5V

Regions of operation of the transistors:

M2 is saturated when,

v DS 2 ≥ vGS 2-V TN → vOUT -V S 1 ≥ V IC -0.5v ID-V S 1-V TN → vOUT ≥ V IC -V TN

where we have assumed that the region of transition for M2 is close to v ID = 0V.

M4 is saturated when,

vSD4 ≥ vSG4 - |V TP| → V DD-vOUT ≥ V SG4-|V TP| → vOUT ≤ V DD-V SG4+|V TP|The regions of operations shown on the voltage transfer function assume I SS = 100µA.

Note: V SG4 =2·5050·2 +|V TP| = 1 + |V TP| ⇒ vOUT ≤ 5 - 1 - 0.7 + 0.7 = 4V



Differential Amplifier Using p-channel Input MOSFETs

V Bias I DD

M1 M2

M3 M4

V DD

M5

vSG1

+

-vSG2

+

-

vG2

-

vOUT

iOUT

vG1

-

i D1 i D2

i D3 i D4

-

+

Fig. 5.2-7

++

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Input Common Mode Range (ICMR)

ICMR is found by setting v ID = 0 and varying v IC until one of the transistors leaves the saturation.

Highest Common Mode Voltage

Path from G1 through M1 and M3 to V DD:

V IC (max) =V G1(max) =V G2(max)

=V DD -V SG3 -V DS 1(sat) +V GS 1

or

V IC (max) = V DD - V SG3 + V TN 1

Path from G2 through M2 and M4 to V DD:

V IC (max)’ =V DD -V SD4(sat) -V DS 2(sat) +V GS 2

=V DD -V SD4(sat) + V TN 2

∴ V IC (max) = V DD - V SG3 + V TN 1

Lowest Common Mode Voltage (Assume a V SS

for generality)

V IC (min) = V SS +V DS 5(sat) + V GS 1 = V SS +V DS 5(sat) + V GS 2

where we have assumed that V GS 1 = V GS 2 during changes in the input common mode

voltage.

V Bias

I SS

M1 M2

M3 M4

V DD

M5

vGS 1+

-

vGS 2+

- vG2

-

vOUT

iOUT

vG1

-

i D1 i D2

i D3 i D4

-

+

Fig. 330-02

2µm1µm

2µm1µm

2µm1µm

2µm1µm

2µm1µm

V DD

2



Example 5.2-1 - Small-Signal Analysis of the Differential-Mode of the Diff. Amp

A requirement for differential-mode operation is that the differential amplifier is balanced†

.

gm3r ds3

1

r ds1

gm1vgs1

r ds2

gm2vgs2

i3i3

+

-

+

-

+G2

vid

vg1 vg2

G1

C 1

-

r ds5

S1=S2

r ds4

C 3

C 2

+

-

vout

D1=G3=D3=G4

S3 S4

D2=D4

gm3r ds3

1r ds1

gm1vgs1 r ds2gm2vgs2

i3

i3

+

-

+

-

+G2

vid

vgs1 vgs2

G1

C 1

-

S1=S2=S3=S4

r ds4

C 3C 2

+

-

vout

D1=G3=D3=G4 D2=D4iout '

I SS

M1 M2

M3 M4

VDD

M5

vout

iout

i D1 i D2

i D3 i D4

-

+

Fig. 330-03

V Bias

vid

Differential Transconductance:

Assume that the output of the differential amplifier is an ac short.

iout’ = gm1gm3r p1

1 + gm3r p1 vgs1 − gm2vgs2 ≈ gm1vgs1 − gm2vgs2 = gmd vid

where gm1 = gm2 = gmd , r p1 = r ds1r ds3 and i'out designates the output current into a shortcircuit.

† It can be shown that the current mirror causes this requirement to be invalid because the drain loads are not matched. However, we will continue to

use the assumption regardless.

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Small-Signal Analysis of the Differential-Mode of the Diff. Amplifier - Continued

Output Resistance: Differential Voltage Gain:

r out = 1

gds2 + gds4 = r ds2||r ds4 Av =

vout

vid =

gmd

gds2 + gds4

If we assume that all transistors are in saturation and replace the small signal

parameters of g m and r ds in terms of their large-signal model equivalents, we achieve

Av = voutvid = (K '1 I SS W 1 / L1)

1/2

(λ 2 + λ 4)( I SS /2) = 2λ 2 + λ 4

K '1W 1 I SS L11/2∝ 1

I SS

Note that the small-signal gain is inversely proportional to the square root of the biascurrent !

Example:

If W 1 / L1 = 2µm/1µm and I SS = 50µA

(10µA), then

Av(n-channel) = 46.6V/V (104.23V/V)

Av(p-channel) = 31.4V/V (70.27V/V)

r out = 1

gds2 + gds4 =

1

25µA·0.09V-1 = 0.444MΩ (2.22MΩ)

vin

vout

Fig. 330-04

Stong InversionWeak

Invers-

ionlog( I Bias)

≈ 1µA



Common Mode Analysis for the Current Mirror Load Differential Amplifier

The current mirror load differential amplifier is not a good example for common modeanalysis because the current mirror rejects the common mode signal.

-

+

vic

M1 M2

M4

M5

vout ≈ 0V

V DD

VBias+

-

M3 M 1 - M3-M

4

Fig. 5.2-8A

M2

Total common

mode Outputdue to vic

=

Common mode

output due toM1-M3-M4 path

-

Common mode

output due toM2 path

Therefore:

• The common mode output voltage should ideally be zero.

• Any voltage that exists at the output is due to mismatches in the gain between the twodifferent paths.

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Small-Signal Analysis of the Common-Mode of the Differential Amplifier

The common-mode gain of the differential amplifier with a current mirror load is ideallyzero.

To illustrate the common-mode gain, we need a different type of load so we will considerthe following:

vic

vo1

v1

vo2

v2

V Bias

I SS

V DD

M1 M2

M3 M4

M5

vo1

vid

V DD

M1 M2

M3 M4vo2 vo1

vic

vo2

V Bias

I SS

V DD

M1 M2

M3 M4

2

I SS M5x12

2

Differential-mode circuit Common-mode circuitGeneral circuit

2vid

2

Fig. 330-05

Differential-Mode Analysis:vo1

vid ≈ -

gm1

2gm3 and

vo2

vid ≈ +

gm2

2gm4

Note that these voltage gains are half of the active load inverter voltage gain.



Small-Signal Analysis of the Common-Mode of the Differential Amplifier – Cont’d

Common-Mode Analysis:

Assume that r ds1 is large and can be

ignored (greatly simplifies theanalysis).

∴ v gs1 = v g 1-v s1 = vic - 2 g m1r ds5v gs1

Solving for vgs1 gives

vgs1 =vic

1 + 2gm1r ds5

The single-ended output voltage, vo1, as a function of vic can be written as

vo1

vic = -

gm1[r ds3||(1/ gm3)]

1 + 2gm1r ds5 ≈ -

(gm1 / gm3)

1 + 2gm1r ds5 ≈ -

gds5

2gm3

Common-Mode Rejection Ratio (CMRR):

CMRR =|vo1 / vid |

|vo1 / vic| =

gm1 /2gm3gds5 /2gm3

= gm1r ds5

How could you easily increase the CMRR of this differential amplifier?

+

-

vic

vgs1+ -

2r ds5 r ds1

gm1vgs1

r ds3 gm31

+

-

vo1

Fig. 330-06

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Frequency Response of the Differential Amplifier

Back to the current mirror load differential amplifier:

gm31gm1vgs1 r ds2gm2vgs2

i3

i3

+

-

+

-

+G2

vid

vgs1 vgs2

G1

C 1

-

S1=S2=S3=S4

r ds4

C 3

C 2

+

-

vout

D1=G3=D3=G4 D2=D4iout '

Fig. 330-07

M1 M2

M3 M4

VDD

M5

vout

-

+

V Bias

vid

C L

C bd 1

C bd 2

C bd 3 C bd 4

C gd 2C gd 1

C gs3+C gs4

C gd 4

Ignore the zeros that occur due to C gd 1, C gd 2 and C gd 4.

C 1 = C gd 1 + C bd 1 + C bd 3 + C gs3 + C gs4,C 2 = C bd 2 + C bd 4 + C gd 2 + C L and C 3 = C gd 4If C 3 ≈ 0, then we can write

V out (s) ≈ gm1

gds2 + gds4

gm3

gm3 + sC 1 V gs1(s) - V gs2(s)

ω 2

s + ω 2 where ω 2 ≈

ggs2 + g ds4

C 2

If we further assume that g m3/C 1 >> ( g ds2+ g ds4)/C 2 = ω 2then the frequency response of the differential amplifier reduces to

V out(s)V id (s) ≅

gm1

gds2 + gds4

ω 2

s + ω 2(A more detailed analysis will be made in Chapter 6)



An Intuitive Method of Small Signal Analysis

Small signal analysis is used so often in analog circuit design that it becomes desirable tofind faster ways of performing this important analysis.

Intuitive Analysis (or Schematic Analysis)

Technique:

1.) Identify the transistor(s) that convert the input voltage to current (these transistorsare called transconductance transistors).

2.) Trace the currents to where they flow into an equivalent resistance to ground.

3.) Multiply this resistance by the current to get the voltage at this node to ground.

4.) Repeat this process until the output is reached.

Simple Example:

vin

vout

V DD

R1

gm1vin

V DD

vo1 gm2vo1

R2M1

M2

Fig. 5.2-10C

vo1 = -(gm1vin) R1 → vout = -(gm2vo1) R2 → vout = (gm1 R1gm2 R2)vin

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Intuitive Analysis of the Current-Mirror Load Differential Amplifier

V Bias

M1 M2

M3 M4

VDD

M5

vid +

- +

-v

out

gm2vid

-

+

Fig. 5.2-11

2

vid

2

2gm1vid

2

gm1vid

2gm1vid

2

+ -vid

r out

1.) i1 = 0.5gm1vid and i2 = -0.5gm2vid

2.) i3 = i1 = 0.5gm1vid

3.) i4 = i3 = 0.5gm1vid

4.) The resistance at the output node, r out , is r ds2||r ds4 or1

gds2 + gds4

5.) ∴ vout = (0.5gm1vid +0.5gm2vid )r out =gm1vin

gds2+gds4 =

gm2vingds2+gds4

⇒ vout vin

=gm1

gds2+gds4



Some Concepts to Help Extend the Intuitive Method of Small-Signal Analysis

1.) Approximate the output resistance of any cascode circuit as Rout ≈ (gm2r ds2)r ds1

where M1 is a transistor cascoded by M2.

2.) If there is a resistance, R, in series with the source of the transconductance transistor,let the effective transconductance be

gm(eff ) =

gm1+gm R

Proof:gm2(eff)vin

vin

V Bias

M2

M1 vinr ds1

M2

gm2(eff)ving

m2v

gs2vgs2

vin

+ -

r ds1

iout

Small-signal model

Fig. 5.2-11A

∴ v gs2 = v g 2 - v s2 = vin - (gm2r ds1)v gs2 ⇒ v gs2 =vin

1+gm2r ds1

Thus, iout =gm2vin

1+gm2rds1 = gm2(eff ) vin

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Slew Rate of the Differential Amplifier

Slew Rate (SR) = Maximum output-voltage rate (either positive or negative)

It is caused by, iOUT = C L

dvOUT dt . When iOUT is a constant, the rate is a constant.

Consider the following current-mirror load, differential amplifiers:

C L

V Bias

I SS

M1 M2

M3 M4

V DD

M5

vGS 1+

-vGS 2

+

-vG2

-

vOUT

iOUT

vG1

-

i D1 i D2

i D3 i D4

-

+

C L

V Bias I DD

M1 M2

M3 M4

V DD

M5

vSG1

+

-vSG2

+

-

vG2

-

vOUT

iOUT

vG1

-

i D1 i D2

i D3 i D4

-

+

Fig. 5.2-11B

++

Note that slew rate can only occur when the differential input signal is large enough tocause I

SS ( I DD

) to flow through only one of the differential input transistors.

SR = I SS C L

= I DDC L

⇒ If C L = 5pF and I SS = 10µA, the slew rate is SR = 2V/µs.

(For the BJT differential amplifier slewing occurs at ±100mV whereas for the MOSFETdifferential amplifier it can be ±2V or more.)



Noise Analysis of the Differential Amplifier

V Bias

M1 M2

M3 M4

V DD

M5

V out

ito2

Fig. 5.2-11C

en12

en42en32

en22 eeq2

V Bias

V DD

M5

M1 M2

M3 M4

M5

vOUT

* *

* *

*

Solve for the total output-noise current to get,ito

2 = gm1

2en1

2 + gm2

2en2

2 + gm3

2en3

2 + gm4

2en4

2

This output-noise current can be expressed in terms of an equivalent input noise voltage,

eeq 2, given asito2 = gm1

2eeq2

Equating the above two expressions for the total output-noise current gives,

eeq2 = en1

2 + en22 +

gm3

gm1 2 en3

2 + en42

1/f Noise (en12=en2

2 and en32=en4

2): Thermal Noise (en12=en2

2 and en32=en4

2):

eeq(1/ f )=2 BP

fW 1 L1 1 +

K’ N B N

K’P BP

L1

L3

2 eeq(th)=

16kT

3[2K '1(W / L)1 I 1]1/2

1+

W 3 L1K '3

L3W 1K '11/2

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Current-Source Load Differential Amplifier

Gives a truly balanced differential amplifier.V DD

I Bias

M1 M2

M3 M4

M5

X2

I 1 I 2

I 3 I 4

v1 v2

v3 v4

M6

M7X1

X1X1

X1

X1 X1

Fig. 5.2-12

I 5

Also, the upper input common-mode range is extended.

However, a problem occurs if I 1 ≠ I 3 or if I 2 ≠ I 4.

I 1 I 3

V DS 1<V DS (sat ) V DD0

0

Current

I 1 I 3

V SD3<V SD(sat ) V DD0

0

Current

Fig. 5.2-13(a.) I 1> I 3. (b.) I 3> I 1.

v DS 1 v DS 1



A Differential-Output, Differential-Input Amplifier

Probably the best way to solve the current mismatch problem is through the use of common-mode feedback.

Consider the following solution to the previous problem.

v1M1 M2

M3 M4

M5

V DD

V SS

I Bias

V CM

v4v3

v2

MC2A

MC2B

MC1

MC3

MC4

MC5MB

I 3 I 4

I C 4 I C 3

Fig. 5.2-14

Common-

mode feed-

back circuitSelf-

resistances

of M1-M4

Operation:

• Common mode output voltages are sensed at the gates of MC2A and MC2B andcompared to V CM .

• The current in MC3 provides the negative feedback to drive the common mode outputvoltage to the desired level.

• With large values of output voltage, this common mode feedback scheme has flaws.

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Design of a CMOS Differential Amplifier with a Current Mirror Load - Continued

Schematic-wise, the design procedure is illustrated asshown:

Procedure:

1.) Pick I SS to satisfy the slew rate knowing C L orthe power dissipation

2.) Check to see if Rout will satisfy the frequency

response, if not change I SS or modify circuit

3.) Design W 3 / L3 (W 4 / L4) to satisfy the upper ICMR

4.) Design W 1 / L1 (W 2 / L2) to satisfy the gain

5.) Design W 5 / L5 to satisfy the lower ICMR

6.) Iterate where necessaryALA20

-

+vin M1 M2

M3 M4

M5

vout

V DD

V SS

VBias+

-

C L

V SG4

+

-

gm1 Rout

Min. ICMR I 5

I 5 = SR·C L ,

ω-3dB , Pdiss

Max. ICMR



Example 5.2-2 - Design of a MOS Differential Amp. with a Current Mirror Load

Design the currents and W/L values of the current mirror load MOS differential amplifierto satisfy the following specifications: V DD = -V SS = 2.5V, SR ≥ 10V/µs (C L=5pF), f -3dB≥ 100kHz (C L=5pF), a small signal gain of 100V/V, -1.5V≤ ICMR≤2V and Pdiss ≤ 1mW.

Use the parameters of K N ’=110µA/V2, K P’=50µA/V2, V TN =0.7V, V TP=-0.7V,

λ N =0.04V-1 and λ P=0.05V-1.

Solution

1.) To meet the slew rate, I SS ≥ 50µA. For maximum Pdiss, I SS ≤ 200µA.

2.) f -3dB of 100kHz implies that Rout ≤ 318k Ω. Therefore Rout =2

(λ N +λ P) I SS ≤ 318k Ω

∴ I SS

≥ 70µA Thus, pick I SS

= 100µA

3.) V IC (max) = V DD - V SG3 + V TN 1 → 2V = 2.5 - V SG3 + 0.7

V SG3 = 1.2V =2·50µA

50µA/V2(W 3 / L3) + 0.7

∴ W 3 L3

=W 4 L4

=2

(0.5)2 = 8

4.) 100=gm1 Rout =gm1

gds2+gds4 =

2·110µA/V2(W 1 / L1)

(0.04+0.05) 50µA = 23.31

W 1 L1

→ W 1 L1

=W 2 L2

=18.4

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Large-Signal Characteristics of the Cascode Amplifier

0 1 2 3 4 5

I D ( m A )

vOUT

0 1 2 3 4 5

v O U T

vIN

M2

M1

v IN

vOUT

I D

5V

+

-

+

-

W3L3

=2µm1µm

W1L1

= 2µm1µm

Fig. 5.3-2

C

M3

2.3V

A B C

D

E

G H

I K

F

J

1

0

2

3

4

5

M3 saturated

EHI

K

J

M3 active

v IN =5.0V

v IN =4.0V

v IN =4.5V

v IN =1.0V

v IN =1.5V

v IN =2.0V

v IN =2.5V

0.0

0.1

0.2

0.3

0.4

0.5

v IN =3.5V

v IN =3.0V

D

A,B

G F

M2 activeM2 saturated

M1 sat-

urated

M1

active

3.4V

W2L2

= 2µm1µm

M3

M1 sat. when V GG 2-V GS 2 ≥ V GS 1-V T → v IN ≤ 0.5(V GG 2+V TN ) where V GS 1=V GS 2M2 sat. when V DS 2≥V GS 2-V TN → vOUT -V DS 1≥V GG2-V DS 1-V TN → vOUT ≥V GG2-V TN

M3 is saturated when V DD-vOUT ≥ V DD - V GG 3 - |V TP | → vOUT ≤ V GG 3 + |V TP |



Large-Signal Voltage Swing Limits of the Cascode Amplifier

Maximum output voltage, vOUT (max): vOUT (max) = V DD


Referencing all potentials to the negative power supply (ground in this case), we mayexpress the current through each of the devices, M1 through M3, as

i D1 = β 1

(V DD - V T 1)v DS 1 -v

2 DS 1

2 ≈ β 1(V DD - V T 1)v DS 1

i D2 = β 2

(V GG2 - v DS 1 - V T 2)(vOUT - v DS 1) -(vOUT - v DS 1)2

2≅ β 2(V GG2 - v DS 1 - V T 2)(vOUT - v DS 1)

and

i D3 = β 3

2 (V DD − V GG 3 − |V T 3|)2

where we have also assumed that both v DS 1 and vOUT are small, and vIN = V DD.Solving for vOUT by realizing that i D1 = i D2 = i D3 and β 1 = β 2 we get,

vOUT (min) = β 3

2β 2 (V DD − V GG3 − |V T 3|)2

1

V GG2 − V T 2 +

1V DD − V T 1

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Example 5.3-1 - Calculation of the Min. Output Voltage for the Cascode Amplifier

(a.) Assume the values and parameters used for the cascode configuration plotted in theprevious slide on the voltage transfer function and calculate the value of vOUT (min).

(b.) Find the value of vOUT (max) and vOUT (min) where all transistors are in saturation.

Solution

(a.) Using the previous result gives,

vOUT (min) = 0.50 volts.We note that simulation gives a value of about 0.75 volts. If we include the influence of the channel modulation on M3 in the previous derivation, the calculated value is 0.62volts which is closer. The difference is attributable to the assumption that both v DS 1 and

vOUT are small.

(b.) The largest output voltage for which all transistors of the cascode amplifier are insaturation is given as

vOUT (max) = V DD - V SD3(sat)

and the corresponding minimum output voltage is

vOUT (min) = V DS 1(sat) + V DS 2(sat) .

For the cascode amplifier of Fig. 5.3-2, these limits are 3.0V and 2.7V.

Consequently, the range over which all transistors are saturated is quite small for a 5Vpower supply.



Small-Signal Midband Performance of the Cascode Amplifier

Small-signal model:

gm1vgs1 r ds1

+

-

vout vin =vgs1

r ds2

r ds3

gm2vgs2= -gm2v1

+

-

Small-signal model of cascode amplifier neglecting the bulk effect on M2.

+

-

v1

G1 D1=S2 D2=D3

S1=G2=G3

gm1vin r ds1

+

-

vout vin

r ds2

r ds3

+

-

+

-

v1

G1 D1=S2 D2=D3

1gm2

C 2 gm2v1 C 3

Simplified equivalent model of the above circuit. Fig. 5.3-3

C 1

Using nodal analysis, we can write,

[gds1 + gds2 + gm2]v1 − gds2vout = −gm1vin

−[gds2 + gm2]v1 + (gds2 + gds3)vout = 0

Solving for vout / vin yields

vout

vin =

−gm1(gds2 + gm2)

gds1gds2 + gds1gds3 + gds2gds3 + gds3gm2 ≅

−gm1

gds3 = −

2K '1W 1 L1 I Dλ 23

The small-signal output resistance is,

r out = [r ds1 + r ds2 + gm2r ds1r ds2]||r ds3 ≅ r ds3

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Small-Signal Analysis of the Cascode Amplifier - Continued

It is of interest to examine the voltage gain of v1 / vin. From the previous nodal equations,

v1

vin =

−gm1(gds2+gds3)

gds1gds2+gds1gds3+gds2gds3+gds3gm2 ≈

gds2+gds3

gds3

−gm1

gm2 ≅

−2gm1

gm2 = −2

W 1 L2

L1W 2

If the W / L ratios of M1 and M2 are equal and gds2 = gds3, then v1 / vin is approximately −2.

Why is this gain -2 instead of -1?

Consider the small-signal model looking into thesource of M2:

The voltage loop is written as,

vs2 = (i1 - gm2vs2)r ds2 + i1r ds3

= i1(r ds2 + r ds3) - gm2 r ds2vs2 Solving this equation for the ratio of vs2 to i1gives

Rs2 =vs2

i1 =

r ds2 + r ds3

1 + gm2r ds2

We see that Rs2 equals 2/ gm2 if r ds2 ≈ r ds3. Thus, if gm1 ≈ gm2, the voltage gain v1 / vin ≈ -2.

Note that:r ds3 =0 that R s2≈1/ gm2 or r ds3=r ds2 that R s2≈2/ gm2 or r ds3≈r ds2gmr ds that R s2≈r ds!!!

Principle: The small-signal resistance looking into the source of a MOSFET depends onthe resistance connected from the drain of the MOSFET to ac ground.

r ds2

r ds3

gm2vs2

vs2

Rs2i1

i A

i B

Fig. 5.3-4



Frequency Response of the Cascode Amplifier

Small-signal model ( RS = 0):where

C 1 = C gd 1,

C 2 = C bd 1+C bs2+C gs2, and

C 3 = C bd 2+C bd 3+C gd 2+C gd 3+C L

The nodal equations now become:(gm2 + gds1 + gds2 + sC 1 + sC 2)v1 − gds2vout = −(gm1 − sC 1)vin

and−(gds2 + gm2)v1 + (gds2 + gds3 + sC 3)vout = 0

Solving for V out(s)/ V in(s) gives,V out(s)

V in(s) =

1

1 + as + bs2

−(gm1 − sC 1)(gds2 + gm2)

gds1gds2 + gds3(gm2 + gds1 + gds2)

where

a = C 3(gds1 + gds2 + gm2) + C 2(gds2 + gds3) + C 1(gds2 + gds3)

gds1gds2 + gds3(gm2 + gds1 + gds2)and

b = C 3(C 1 + C 2)

gds1gds2 + gds3(gm2 + gds1 + gds2)

gm1vin r ds1

+

-

vout vin

r ds2

r ds3

+

-

+

-

v1

G1 D1=S2 D2=D3

1gm2

C 2 gm2v1 C 3

Fig. 5.3-4A

C 1

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A Simplified Method of Finding an Algebraic Expression for the Two Poles

Assume that a general second-order polynomial can be written as:

P(s) = 1 + as + bs2 =

1 − s

p1

1 − s

p2 = 1 − s

1

p1 +

1 p2

+ s2

p1 p2

Now if | p2| >> | p1|, then P(s) can be simplified as

P(s) ≈ 1 − s

p1 +

s2

p1 p2

Therefore we may write p1 and p2 in terms of a and b as

p1 = −1a and p2 =

−ab

Applying this to the previous problem gives,

p1 = −[gds1gds2 + gds3(gm2 + gds1 + gds2)]

C 3(gds1 + gds2 + gm2) + C 2(gds2 + gds3) + C 1(gds2 + gds3) ≈ −gds3

C 3

The nondominant root p2 is given as

p2 = −[C 3(gds1 + gds2 + gm2) + C 2(gds2 + gds3) + C 1(gds2 + gds3)]

C 3(C 1 + C 2) ≈ −gm2

C 1 + C 2

Assuming C 1, C 2, and C 3 are the same order of magnitude, and gm2 is greater than gds3,then | p1| is smaller than | p2|. Therefore the approximation of | p2| >> | p1| is valid.

Note that there is a right-half plane zero at z1 = gm1 / C 1.



Driving Amplifiers from a High Resistance Source - The Miller Effect

Examine the frequencyresponse of a current-sourceload inverter driven from ahigh resistance source:

Assuming the input is I in,the nodal equations are,

[G1 + s(C 1 + C 2)]V 1 − sC 2V out = I in and (gm1−sC 2)V 1+[G3+s(C 2+C 3)]V out = 0where G1 = Gs (=1/ Rs), G3 = gds1 + gds2, C 1 = C gs1, C 2 = C gd 1 and C 3 = C bd 1+C bd 2 + C gd 2.

Solving for V out(s)/ V in(s) gives

V out(s)V in(s) = (sC 2−gm1)G1

G1G3+s[G3(C 1+C 2)+G1(C 2+C 3)+gm1C 2]+(C 1C 2+C 1C 3+C 2C 3)s2

or

V out(s)

V in(s) =

−gm1

G3

[1−s(C 2 / gm1)]

1+[ R1(C 1+C 2)+ R3(C 2+C 3)+gm1 R1 R3C 2]s+(C 1C 2+C 1C 3+C 2C 3) R1 R3s2

Assuming that the poles are split allows the use of the previous technique to get,

p1 = −1

R1(C 1+C 2)+ R3(C 2+C 3)+gm1 R1 R3C 2 ≅

−1gm1 R1 R3C 2

and p2 ≅ −gm1C 2

C 1C 2+C 1C 3+C 2C 3The Miller effect has caused the input pole, 1/ R1C 1, to be decreased by a value of gm1 R3.

vin Rs

V GG2

V DD

vout

M2

M1

Rs

Rs Rs

V inC 1

C 2

C 3 R3

C 1 ≈ C gs1

C 2 = C gd 1

C 3 = C bd 1 + C bd 2 + C gd 2

R3 = r ds1||r ds2

+

-

V out

Fig. 5.3-5

+

-

V 1gm1V 1

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How does the Cascode Amplifier Solve the Miller Effect?

The dominant pole of the inverting amplifier with a large source resistance was found tobe

p1(inverter) = −1

R1(C 1+C 2)+ R3(C 2+C 3)+gm1 R1 R3C 2

Now if a cascode amplifier is used, R3, can be approximated as 2/ gm of the cascoding

transistor (assuming the drain sees an r ds

to ac ground).

∴ p1(cascode) =−1

R1(C 1+C 2)+

2

gm(C 2+C 3)+gm1 R1

2

gmC 2

=−1

R1(C 1+C 2)+

2

gm(C 2+C 3)+2 R1C 2

≈ −1

R1(C 1+3C 2)

Thus we see that p1(cascode) >> p1(inverter).



High Gain and High Output Resistance Cascode Amplifier

If the load of the cascodeamplifier is a cascodecurrent source, then bothhigh output resistanceand high voltage gain isachieved.

The output resistance is,

r out ≅ [gm2r ds1r ds2][gm3r ds3r ds4] = I

-1.5D

λ 1λ 2

2K '2(W / L)2 +

λ 3λ 4

2K '3(W / L)3

Knowing r out, the gain is simply

Av = −gm1r out ≅ −gm1[gm2r ds1r ds2][gm3r ds3r ds4] ≅ 2K '1(W / L)1 I

-1D

λ 1λ 22K '2(W / L)2

+ λ 3λ 4

2K '3(W / L)3

V DD

V GG4

V GG3

V GG2

vin

vout

Rout

M3

M4

M2

M1

gm1vinr ds1

gm2v1 gmbs2v1 r ds2 gm3v4 gmbs3v4 r ds3

r ds4v1

+

-

v4

+

-

vout

+

-

G1 D1=S2 D4=S3

D2=D3

G2=G3=G4=S1=S4

vin

+

-

Fig. 5.3-6

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Example 5.3-2 - Comparison of the Cascode Amplifier Performance

Calculate the small-signal voltage gain, output resistance, the dominant pole, and thenondominant pole for the low-gain, cascode amplifier and the high-gain, cascodeamplifier. Assume that I D = 200 microamperes, that all W / L ratios are 2µm/1µm, andthat the parameters of Table 3.1-2 are valid. The capacitors are assumed to be: C gd = 3.5fF, Cgs = 30 fF, Cbsn = Cbdn = 24 fF, Cbsp = Cbdp = 12 fF, and C L = 1 pF.

Solution

The low-gain, cascode amplifier has the following small-signal performance:

Av = −37.1V/V

Rout = 125k Ω p1 ≈ -gds3 / C 3 → 1.22 MHz p2 ≈ gm2 /(C 1+C 2) → 605 MHz.

The high-gain, cascode amplifier has the following small-signal performance:

Av = −414V/V

Rout = 1.40 MΩ p

1≈ 1/ R

out C

3 → 108 kHz

p2 ≈ gm2 /(C 1+C 2) → 579 MHz

(Note at this frequency, the drain of M2 is shorted to ground by the load capacitance, C L)



Designing Cascode Amplifiers

Pertinent design equations for the simple cascode amplifier.

+v IN

-

+

vOUT

-

M2

M1

M3

V DD

V GG3

V GG2

Fig. 5.3-7

I

vOUT (min) =V DS 1(sat) + V DS 2(sat)

2 I K N (W 1 / L1)

vOUT (max) = V DD - V SD3(sat)

2 I K N (W 2 / L2)

+=

2 I K P(W 3 / L3)

=V DD -

I = Pdiss

V DD= (SR)·C out

|Av| = gm1gds3

= 2K N (W 1 / L1)

λP2 I

I = K PW 3

2 L3(V DD - V GG3-|V TP|)2

V GG2 = V DS 1(sat) + V GS 2

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Frequency Response of a Current Amplifier with Current Feedback

Consider the following current amplifier with resistivenegative feedback applied.

Assuming that the small-signal resistance looking intothe current amplifier is much less than R1 or R2,

io

= Ai

(i1-i

2) = A

i

vin

R1 - i

oSolving for io gives

io =

Ai

1+ Ai vin

R1 → vout = R2io =

R2

R1

Ai

1+ Ai vin

If Ai(s) = Ao

sω A + 1

, then

vout vin

= R2 R1

1

1+1

Ai(s)

= R2 R1

Ao

sω A

+(1+ Ao) =

R2 R1

Ao

1+ Ao

1

sω A

(1+ Ao) +1

∴ ω -3dB = ω A(1+ Ao)

R2i2io

Aii1

-

+

R1 vout

vin

Fig. 5.4-2



Bandwidth Advantage of a Current Feedback Amplifier

The unity-gainbandwidth is,

GB = | Av(0)| ω -3dB = R2 Ao

R1(1+ Ao) · ω A(1+ Ao) =

R2 R1

Ao·ω A = R2 R1

GBi

where GBi is the unity-gainbandwidth of the current amplifier.

Note that if GBi is constant, then increasing R2 / R1 (the voltage gain) increases GB.

Illustration:

Ao dB

ω A

R2 R1 >1

R2

R1

GB1 GB2

Current Amplifier

0dB

Voltage Amplifier,

log10(ω)

Magnitude dB

Fig. 7.2-10

(1+ Ao)ω A

GBi

= K

R1Voltage Amplifier, > K

R2

1+ Ao

Ao dB

1+ Ao

Ao dBK

Note that GB2 > GB1 > GBiThe above illustration assumes that the GB of the voltage amplifier realizing the voltagebuffer is greater than the GB achieved from the above method.

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Self-Biased Cascode Current Mirror Implementation of a Current Amplifier

V DD V DD

I 1 I 2iin iout

Current Amplifier

R

M1 M2

M3 M4

+

-

vout

+

-

vin

Fig. 5.4-4

Rin ≈ R +1

gm1, Rout ≈ r ds2gm4r ds4, and Ai =

W 2 / L2

W 1 / L1



Example 5.4 -2 - Current Amplifier Implemented by the Self-Biased, Cascode

Current MirrorAssume that I 1 and I 2 of the self-biased cascode current mirror are 100µA. R has

been designed to give a V ON of 0.1V. Thus R = 1k Ω. Find the value of Rin, Rout , and Ai if

the W/L ratios of all transistors are 182µm/1µm.

Solution

The input resistance requires gm1 which is 2·110·182·100 = 2mS

∴ Rin ≈ 1000Ω + 500Ω = 1.5k Ω

From our knowledge of the cascode configuration, the small signal output resistanceshould be

Rout ≈ gm4r ds4r ds2 = (2001µS)(250k Ω)(250k Ω) = 125MΩ

Because V DS 1 = V DS 2, the small-signal current gain is

Ai =W 2 / L2

W 1 / L1 = 1

Simulation results using the level 1 model for this example give

Rin=1.497k Ω, Rout = 164.7MΩ and Ai = 1.000 A/A.

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Summary

• Current amplifiers have a low input resistance, high output resistance, and a definedoutput-input current relationship

• Input resistances less than 1/ gm require feedback

However, all feedback loops have internal poles that cause the benefits of negativefeedback to vanish at high frequencies.

In addition, these feedback loops can have a slow time constant from a pole-zero pair.• Voltage amplifiers using a current amplifier have high values of gain-bandwidth

• Current amplifiers are useful at low power supplies and for switched currentapplications



SECTION 5.5 - OUTPUT AMPLIFIERS

General Considerations of Output AmplifiersRequirements:

1.) Provide sufficient output power in the form of voltage or current.

2.) Avoid signal distortion.

3.) Be efficient

4.) Provide protection from abnormal conditions (short circuit, over temperature, etc.)

Types of Output Amplifiers:

1.) Class A amplifiers2.) Source followers

3.) Push-pull amplifiers

4.) Substrate BJT amplifiers

5.) Amplifiers using negative shunt feedback

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Class A Amplifiers

Current source load inverter:

A Class A circuit has currentflow in the MOSFETs duringthe entire period of asinusoidal signal.

Characteristics of Class A amplifiers:

• Unsymmetrical sinking and sourcing

• Linear

• Poor efficiency

Efficiency = P RLPSupply

=

vOUT (peak)2

2 R L(V DD-V SS ) I Q

=

vOUT (peak)2

2 R L

(V DD -V SS )

(V DD-V SS )

2 R L

=

vOUT (peak)V DD -V SS 2

Maximum efficiency occurs when vOUT (peak) = V DD = |V SS | which gives 25%.

C L R L

M2

M1

V GG2

V DD

v IN

vOUT iOUT I Q

i D1

Fig. 5.5-1

i DV DD+|V SS |

V DD

vOUT

R L

I Q

I Q R L I Q R LV SS

R L dominates

as the load line

V SS



Optimum Value of Load Resistor

Depending on the value of RL, the signal swing can be symmetrical or asymmetrical.(This ignores the limitations of the transistor.)

Fig. 040-03

i D1

V DD+|V SS |

V DD

v DS 1

R L

I Q

I Q R L I

Q R

L

Minimum R L for

maximum swing

0

0

Smaller R L

Larger R L

V SS

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Specifying the Performance of a Class A Amplifier

Output resistance:

r out =1

gds1+ gds2 =

1(λ 1+λ 2) I D

Current:

• Maximum sinking current is,

I -OUT =

K '1W 12 L1

(V DD -V SS - V T 1)2 - I Q

• Maximum sourcing current is,

I +

OUT =K '2W 2

2 L2 (V DD - V GG2 - |V T 2|)2 ≤ I Q

Requirements:

• Want r out << R L

• | I OUT | > C L·SR

• | I OUT | > vOUT (peak) R L

The maximum current is determined by both the current required to provide thenecessary slew rate (C L) and to provide a voltage across the load resistor ( R L).



Small-Signal Performance of the Class A Amplifier

Although we have considered the small-signal performance of the Class A amplifier as thecurrent source load inverter, let us include the influence of the load.

The modified small-signal model:

gm1vinvin r ds1 r ds2 R L

+

-

+

-

vout C 2

C 1

Fig. 5.5-2

The small-signal voltage gain is:

vout vin = -gm1 gds1+gds2+G L

The small-signal frequency response includes:

A zero at

z =gm1C gd 1

and a pole at

p =-(gds1+gds2+G L)

C gd 1+C gd 2+C bd 1+C bd 2+C L

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Example 5.5-1 - Design of a Simple Class-A Output Stage

Use Table 3.1-2 to design the W / L ratios of M1 and M2 so that a voltage swing of ±2Vand a slew rate of ≅1 V/ µ s is achieved if R L = 20 k Ω and C L = 1000 pF. Assume V DD =|V SS | = 3V and V GG2 = 0V. Let L = 2 µ m and assume that C gd 1 = 100fF.

Solution

Let us first consider the effects of R L and C L.

iOUT (peak) = ±2V/20k Ω = ±100µA and C L·SR = 10-9

·106 = 1000µA

Since the slew rate current is so much larger than the current needed to meet the voltagespecification across R L, we can safely assume that all of the current supplied by theinverter is available to charge C L.

Using a value of ±1 mA,

W 1 L1

=2( I OUT -+ I Q)

K N ’(V DD+|V SS | -V TN )2 =

4000

110·(5.3)2 ≈ 3µm2µm

and

W 2

L2 =

2 I OUT +

K P ’(V DD-V GG 2-|V TP |)2 =

2000

50·(2.3)2 ≈

15µm

2µm

The small-signal performance is Av = -8.21 V/V (includes R L = 20k Ω) and r out = 50k Ω

The roots are, zero = gm1 / C gd 1 ⇒ .59GHz and pole = 1/[( R L||r out )C L)] ⇒ -11.14kHz



Broadband Harmonic Distortion

The linearity of an amplifier can be characterized by its influence on a pure sinusoidalinput signal.

Assume the input is,

V in(ω) = V p sin(ωt )

The output of an amplifier with distortion will be

V out (ω ) = a1V p sin (ω t ) + a2V p sin (2ω t ) +...+ anV p sin(nω t )

Harmonic distortion ( HD) for the ith harmonic can be defined as the ratio of themagnitude of the ith harmonic to the magnitude of the fundamental.

For example, second-harmonic distortion would be given as

HD2 = a2a1

Total harmonic distortion (THD) is defined as the square root of the ratio of the sum of allof the second and higher harmonics to the magnitude of the first or fundamental harmonic.

Thus, THD can be expressed as

THD = [a

22 + a

23 +...+ a

2

n]1/2

a1

The distortion of the class A amplifier is good for small signals and becomes poor atmaximum output swings because of the nonlinearity of the voltage transfer curve for

large-signal swing

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Class-A Source Follower

N-Channel Source Follower Voltage transfer curve:with current sink bias:

Maximum output voltage swings:

vOUT (min) ≈ V SS - V ON 2 (if R L is large) or vOUT (min) ≈ - I Q R L (if R L is small)

vOUT (max) = V DD - V ON 1 (if v IN > V DD) or vOUT (max) ≈ V DD - V GS 1

M3

Fig. 040-01

I Q

V DD

v IN

vOUT iOUT

M1

M2

V SS

V SS

V DD

V SS

R L

v IN

vOUT

Fig. 040-02

V GS 1

V DD-V ON 1

|V SS |+V ON 2

V DD-V ON 1+V GS 1

|V SS |+V ON 2+V GS 1

I Q R L<|V SS |+V ON 2

V DD-V GS 1

V DD

|V SS |

Triode

Triode



Output Voltage Swing of the Follower

The previous results do not include the bulk effect on V T 1 of V GS 1.Therefore,

V T 1 = V T 01 + γ [ 2|φ F | -v BS - 2|φ F |] ≈ V T 01+γ vSB = V T 01+γ 1 vOUT (max)-V SS

∴ vOUT (max)-V SS ≈V DD-V SS -V ON 1-V T 1 = V DD-V SS -V ON 1-V T 01-γ 1 vOUT (max)-V SS

Define vOUT (max)-V SS = vOUT ’(max)

which gives the quadratic,

vOU T ’(max)+γ 1 vOUT ’(max)-(V DD-V SS -V ON 1-V T 01)=0

Solving the quadratic gives,

vOUT ’(max) ≈ γ 12

4 -γ 12 γ 12+4(V DD-V SS -V ON 1-V T 01) +

γ 12+ 4(V DD-V SS -V ON 1-V T 01)

4

If V DD = 2.5V, γ N = 0.4V1/2, V TN 1= 0.7V, and V ON 1 = 0.2V, then vOUT ’(max) = 3.661V

and

vOUT (max) = 3.661-2.5 = 0.8661V

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Maximum Sourcing and Sinking Currents for the Source Follower

Maximum Sourcing Current (into a short circuit):

We assume that the transistors are in saturation andV DD = -V SS = 2.5V , thus

I OUT (sourcing) =K ’1W 1

2 L1 [V DD − vOUT − V T 1]2- I Q

where v IN is assumed to be equal to V DD.

If W 1 / L1 =10 and if vOUT = 0V, then

V T 1 = 1.08V ⇒ I OUT equal to 1.11 mA.

However, as vOUT increases above 0V, the current rapidly decreases.

Maximum Sinking Current:

For the current sink load, the sinking current is whatever the sink is biased to provide.

I OUT (sinking) = I Q

M3

Fig. 040-01

I Q

V DD

v IN

vOUT

iOUT

M1

M2

V SS

V SS

V DD

V SS

R L



Efficiency of the Source Follower

Assume that the source followerinput can swing to power supply.Plotting

i D =β 2 (v IN - vOUT - V T )

2

and

i D = I Q -vOUT

R L

Efficiency =

P RLPSupply

=

vOUT (peak)2

2 R L(V DD-V SS ) I Q

=

vOUT (peak)2

2 R L

(V DD -V SS )

(V DD-V SS )

2 R L

=

vOUT (peak)

V DD -V SS

2

Maximum efficiency occurs when vOUT (peak) = V DD = |V SS | which gives 25%.

Comments:

• Maximum efficiency occurs for the minimum value of R L which gives maximum swing.

• Other values of R L result in less efficiency (and smaller signal swings before clipping)

• We have ignored the fact that the dynamic Q point cannot travel along the full length of the load line because of minimum and maximum voltage limits.

i D

vOUT

V T 2V T 3V T V DD-V T -V T -2V T -3V T V DD

-V T -2V T 0 V T 2V T 3V T 4V T

v IN

V DDV SS

V SS -V T V SS

I Q I Q R L

Fig. 040-035

I Q R L = V SS

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Small Signal Performance of the Source Follower

Small-signal model:

V out V in

= gm1

gds1 + gds2 + gm1 + gmbs1+G L ≅

gm1gm1 + gmbs1+G L

≅ gm1 R L

1 +gm1 R L

If V DD = -V SS = 2.5V, V out = 0V, W 1 / L1 = 10µ m/1 µ m, W 2 / L2 = 1µ m/1 µ m,

and I D = 500 µ A, then

For the current sink load follower ( R L = ∞):V out

V in = 0.869V/V, if the bulk effect were ignored, then

V out

V in = 0.963V/VFor a finite load, R L = 1000Ω:

V out V in

= 0.512V/V

Fig. 040-04

gm1vgs1

vin r ds1 r ds2 R L

+

-

+

-

vout C 2

C 1

vgs1+ -

gmbs1vbs1

gm1vinvin r ds1 r ds2 R L

+

-

+

-vout C 2

C 1

vgs1+ -

gmbs1vout gm1vout



Small Signal Performance of the Source Follower - Continued

The output resistance is:

Rout =1

gm1 + gmbs1 + gds1 + gds2

For the current sink load follower:

Rout = 830Ω

The frequency response of the source follower:

V out(s)

V in(s) = (gm1 + sC 1)

gds1 + gds2 + gm1 + gmbs1 + G L + s(C 1 + C 2)

whereC 1 = capacitances connected between the input and output ≈ C GS 1

C 2 = C bs1 +C bd 2 +C gd 2(or C gs2) + C L

z = -gm1C 1

and p ≈ -gm1+G L

C 1+C 2

The presence of a LHP zero leads to the possibility that in most cases the pole and zerowill provide some degree of cancellation leading to a broadband response.

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Push-Pull Source Follower

Can both sink and sourcecurrent and provide a slightlylower output resistance.

Efficiency:

Depends on how thetransistors are biased.

• Class B - one transistorhas current flow for only 180° of the sinusoid (half period)

∴ Efficiency =P RL

PVDD =

vOUT (peak)2

2 R L

(V DD -V SS )

1

2

2vOUT (peak)

π R L

=π

2 vOUT (peak)

V DD -V SS

Maximum efficiency occurs when vOUT (peak) =V DD and is 78.5%

• Class AB - each transistor has current flow for more than 180° of the sinusoid.

Maximum efficiency is between 25% and 78.5%

V DD

v IN vOUT

iOUT

M1

M2 V DD

V Bias

V Bias

Fig. 060-01

V DD

v IN

vOUT iOUT

M1

M2 V DDV DD

V DD

V GG

M3

M4

M5

M6

R L R L

V SS

V SS V SS V SS

V SS

V SS



Illustration of Class B and Class AB Push-Pull, Source Follower

Output current and voltage characteristics of the push-pull, source follower ( R L = 1k Ω):

-2V

-1V

0V

1V

2V

-2 -1 0 1 2

V in(V)

1mA

0mA

-1mA

vout

vG1

vG2

i D1

i D2

Class B, push-pull, source follower

-2V

-1V

0V

1V

2V

-2 -1 0 1 2

V in(V)

1mA

0mA

-1mA

vout

vG1 i D1

i D2

Class AB, push-pull, source follower Fig. 060-02

vG2

Comments:

• Note that vOUT cannot reach the extreme values of V DD and V SS

• I OUT +(max) and I OUT -(max) is always less than V DD / R L or V SS / R L

• For vOUT = 0V, there is quiescent current flowing in M1 and M2 for Class AB

• Note that there is significant distortion at v IN =0V for the Class B push-pull follower

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Small-Signal Performance of the Push-Pull Follower

Model:

gm1vgs1

vin r ds1 r ds2 R L

+

-

+

-

vout C 2

C 1

Fig. 060-03

vgs1+ -

gmbs1vbs1 gm2vgs2

gm1vin

vin

r ds1 r ds2

R L

+

-

+

-

vout C 2

C 1

vgs1+ -

gmbs1vout gm1vout gm2

1

gmbs2vbs2

gm2vin gmbs2vout gm2vout

vout

vin =

gm1 + gm2

gds1+gds2+gm1+gmbs1+gm2+gmbs2+G L

Rout =1

gds1+gds2+gm1+gmbs1+gm2+gmbs2 (does not include R L)

If V DD = -V SS = 2.5V, V out = 0V, I D1 = I D2 = 500µA, and W/L = 20µm/2µm, Av = 0.787

( R L=∞) and Rout = 448Ω.

A zero and pole are located at

z =-(gm1+gm2)

C 1 p =

-(gds1+gds2+gm1+gmbs1+gm2+gmbs2+G L)

C 1+C 2 .

These roots will be high-frequency because the associated resistances are small.



Push-Pull, Common Source Amplifiers

Similar to the class A but can operate as class B providing higher efficiency.

C L R L

v IN vOUT

iOUT

V DD

V TR2

V TR1

M2

M1

Fig. 060-04V SS

Comments:

• The batteries V TR1 and V TR2 are necessary to control the bias current in M1 and M2.

• The efficiency is the same as the push-pull, source follower.

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What about the use of BJTs?

vout

C L

Q1

V DD

M2

vout

C L

Q1

V DD

M2

p-well CMOS n-well CMOS

i B

i B

Fig. 5.5-8A

M3

M3

V DD

V SS V SS V SS

Comments:

• Can use either substrate or lateral BJTs.

• Small-signal output resistance is 1/ gm which can easily be less than 100Ω.

• Unfortunately, only PNP or NPN BJTs are available but not both on a standard CMOStechnology.

• In order for the BJT to sink (or source) large currents, the base current, i B, must be

large. Providing large currents as the voltage gets to extreme values is difficult forMOSFET circuits to accomplish.

• If one considers the MOSFET driver, the emitter can only pull to within v BE +V ON of the

power supply rails. This value can be 1V or more.

We will consider the BJT as an output stage in more detail in Sec. 7.1.



Use of Negative, Shunt Feedback to Reduce the Output Resistance

Concept:

C L R L

v IN vOUT

iOUT

V DD

M2

M1

Fig. 060-07

+-

+-

Error

Amplifier

Error

Amplifier

V SS

Rout =r ds1||r ds2

1+Loop Gain

Comments:

• Can achieve output resistances as low as 10Ω.

• If the error amplifiers are not balanced, it is difficult to control the quiescent current inM1 and M2

• Great linearity because of the strong feedback

• Can be efficient if operated in class B or class AB

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Simple Implementation of Neg., Shunt Feedback to Reduce the Output Resistance

C L R

L

v IN vOUT

iOUT

V DD

M2

M1

Fig. 060-08

R1 R2

V SS

Loop gain ≈

R1

R1+ R2

gm1+gm2

gds1+gds2+G L

∴ Rout =r ds1||r ds2

1+

R1

R1+ R2

gm1+gm2

gds1+gds2+G L

Let R1 = R2, R L = ∞, I Bias = 500µA, W 1 / L1 = 100µm/1µm and W 2 / L2 = 200µm/1µm.

Thus, gm1 = 3.316mS, gm2 = 3.162mS, r ds1 = 50k Ω and r ds2 = 40k Ω.

∴ Rout =50k Ω||40k Ω

1+0.5

3316+3162

25+20

=22.22k Ω

1+0.5(143.9) = 304Ω ( Rout = 5.42k Ω if R L = 1k Ω)



Quasi-Complementary Output Stages

Quasi-complementary connections are used to improve the performance of the NMOS orPMOS transistor.

Composite connections:

Fig. 5.5-11

G

S

D

I D1

M1

Q2

I D

+

-

V SG

G

S

D

+

-

V SG

I DG

S

D

I D1

M1

Q2

I D

+

-

V GS

G

S

D

+

-V GS I D

NMOS Equivalent:

I D=(1+β 2) I D1=(1+β 2)

K P’W 1

2 L1 (V GS -V T )2

∴ The composite has an enhanced K N ’

PMOS Equivalent:

I D=(1+β 2) I D1=(1+β 2)

K P’W 1

2 L1 (V SG-V T )2

∴ The composite has an enhanced K P’

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Summary of Output Amplifiers

• The objectives are to provide output power in form of voltage and/or current.

• In addition, the output amplifier should be linear and be efficient.

• Low output resistance is required to provide power efficiently to a small load resistance.

• High source/sink currents are required to provide sufficient output voltage rate due tolarge load capacitances.

• Types of output amplifiers considered:Class A amplifier

Source follower

Class B and AB amplifier

Use of BJTs

Negative shunt feedback



SECTION 5.6 - HIGH-GAIN AMPLIFIER ARCHITECTURES

High-Gain Amplifiers used in Negative Feedback CircuitsConsider the general, single-loop, negative feedback circuit:

x = either voltage or current

A = x o x i

= high-gain amplifier

F = feedback network

Closed-loop gain:

A f = x o x s

= A1+ AF

If AF >> 1, then,

A f = x o x s

≈ 1F

Therefore, to precisely define the closed-loop gain, A f , we only need to make A large and A f becomes dependent on F which can be determined by passive elements.

A

F

x s x i x o

x f

Σ+

-

Fig. 5.6-1

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Types of Amplifiers

The gain of an amplifier is given as

A = x o x i

Therefore, since x can be voltage or current, there are four types of amplifiers assummarized below.

Types of Amplifers

Voltage-controlled,current-source

Voltage-controlled,voltage-source

Current-controlled,current-source

Current-controlled,voltage-source

x i variable* Voltage Voltage Current Current

x o variable Current Voltage Current Voltage

Desired Ri Large Large Small Small

Desired Ro Large Small Large Small

* The x i , x s, and x f must all be the same type of variable, voltage or current.



Voltage-Controlled, Current-Source (VCCS) Amplifier

Gmvivi Ri Ro

RS

+

-

io

R L

VCCS

vsDifferential

Amplifiervi

+

-

Second

Stage

io

VCCS Fig. 5.6-2

iov s

= G M = Gm Ro Ri

( Ri + RS )( Ro + R L)

This amplifier is sometimes called an operational transconductance amplifier (OTA).

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Voltage-Controlled, Voltage-Source (VCVS) Amplifier

Avvivi Ri

Ro

RS

+

-

vo R L

VCVS

vsDifferential

Amplifiervi

+

-

Second

Stage

vo

VCVS Fig. 5.

+

-

Output

Stage

vov s

= AV = Av Ri R L

( RS + Ri)( Ro + R L)

This amplifier is normally called an operational amplifier .



Current-Controlled, Current-Source (CCCS) Amplifier

Gmvi

ii

Ri Ro RS

io

R L

CCCS

is

Current

Differential

Amplifier

Second

Stage

io

CCCSFig. 5.6-4

ii

i1

i2

ioi s

= A I = Ai RS Ro

( RS + Ri)( Ro + R L)

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Current-Controlled, Voltage-Source (CCVS) Amplifier

Rmvivi Ri

Ro+

-

vo R L

CCVS

Current

Differential

Amplifier

Second

Stage

vo

CCVSFig. 5.6-5

+

-

Output

Stage

ii

RS is ii

i1

i2

voi s

= R M = Rm RS RL

( Ri + RS )( Ro + R L)


SECTION 5.7 - SUMMARY

This chapter presented the following subjects:5.1 Inverting Amplifiers

Class A (diode load and current sink/source load)

Class AB of B (push-pull)

5.2 Differential Amplifiers

Need good common mode rejection

An excellent input stage for integrated circuit amplifiers

5.3 Cascode Amplifiers

Useful for controlling the poles of an amplifier5.4 Current Amplifiers

Good for low power supplies

5.5 Output Amplifiers

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Chapter05-2UP(2_25_03)