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FSM Modeling FSM Design PostScript FSM Analysis Analysis of a Moore Machine
Chapter 9Introduction to Finite State Machines
SKEE2263 Digital Systems
Mun’im/Ismahani/Izam
FEE, Universiti Teknologi Malaysia
April 14, 2016
FSM Modeling FSM Design PostScript FSM Analysis Analysis of a Moore Machine
Table of Contents
1 FSM Modeling
2 FSM Design
3 PostScript
4 FSM Analysis
5 Analysis of a Moore Machine
FSM Modeling FSM Design PostScript FSM Analysis Analysis of a Moore Machine
General Structure of Finite State Machines (FSM)
StateMemory
Inputs OutputsOutputLogic
Combinational Logic
Flip-flops
Next
State
Present
State
Clock
Next StateLogic
FSM Modeling FSM Design PostScript FSM Analysis Analysis of a Moore Machine
Components & Types
Components:State memory to store present state and has 2n distinctstates which n represents the number of flip-flops used.Next state logic to determine the next state when statetransition occurs.Output logic to determine the output as a function ofcurrent state and inputs.
Two widely known types of FSM models are Mealy and Moore.
FSM Modeling FSM Design PostScript FSM Analysis Analysis of a Moore Machine
General Structure of Moore FSM
Next StateLogic
Registers
OutputLogic Outputs
Inputs
State
Moore model: The output depends only on the presentstate of the flip-flops. present inputs.
FSM Modeling FSM Design PostScript FSM Analysis Analysis of a Moore Machine
General Structure of Mealy FSM
Next StateLogic
Registers
OutputLogic Outputs
Inputs
State
Mealy model: The output depends on the present state ofthe flip-flops and the present inputs.
FSM Modeling FSM Design PostScript FSM Analysis Analysis of a Moore Machine
FSM Timing
ClockClock
State time
Inputs
Outputs
FSM Modeling FSM Design PostScript FSM Analysis Analysis of a Moore Machine
State Diagrams
A[0]
B[1] 10
1
0
Input Output
State name
Moore.
A B 1/00/0
1/0
0/1
Input Output
State name
Mealy.
FSM Modeling FSM Design PostScript FSM Analysis Analysis of a Moore Machine
State Table
Present State Input Next State Output CommentsA B
S0 0 S0 0 Remain idle in starting state1 S1 Go to next state
S1 0 S0 1 Go back to starting state1 S1 Remain in current state
FSM Modeling FSM Design PostScript FSM Analysis Analysis of a Moore Machine
State Encoding
No Binary Gray Johnson One-Hot Almost One-Hot
0 000 000 0000 00000001 00000001 001 001 0001 00000010 00000012 010 011 0011 00000100 00000103 011 010 0111 00001000 00001004 100 110 1111 00010000 00010005 101 111 1110 00100000 00100006 110 101 1100 01000000 01000007 111 100 1000 10000000 1000000
FSM Modeling FSM Design PostScript FSM Analysis Analysis of a Moore Machine
FSM Design Procedure
1 Conceptualize – Understand the statement of the specification:
Define all inputs and outputsDetermine system constrains
2 Translate the concept into a state diagram:
Determine the number of states required by the systemDetermine the required transitions
3 Assign a unique binary number to each state.
4 Create the state table.
5 Extract the equations: Express the logic circuits as Booleanequations.
6 Implement the FSM: Enter and verify the design.
FSM Modeling FSM Design PostScript FSM Analysis Analysis of a Moore Machine
Level to Pulse Converter Top Level
Whenever input L goes
from low to high...
... output P produces a
single pulse,
one clock period wide.
Clock
Level to
Pulse
ConverterL P
Reset
FSM Modeling FSM Design PostScript FSM Analysis Analysis of a Moore Machine
Level to Pulse Converter Block Diagram
Clock
Unsynchronized
human inputQD
Synchronizer Edge Detector
Level to
Pulse
ConverterL PQD
FSM Modeling FSM Design PostScript FSM Analysis Analysis of a Moore Machine
Level to Pulse Converter Moore State Diagram
00
0
1 1
1Zero[0]
Edge[1]
One[0]
FSM Modeling FSM Design PostScript FSM Analysis Analysis of a Moore Machine
Level to Pulse Converter State Table
Present In Next Out CommentsState State
Q1 Q0 L Q+1 Q+
0 P
0 0 0 0 0 0Waiting for rising edge
0 0 1 0 1 0
0 1 0 0 0 1Edge detected
0 1 1 1 1 1
1 1 0 0 0 0Waiting for falling edge
1 1 1 1 1 0
FSM Modeling FSM Design PostScript FSM Analysis Analysis of a Moore Machine
Level to Pulse Converter Kmaps
LQ 0
10
11
00
01
1Q0
1
x x
1
1
Q+1 = LQ0
LQ 0
10
11
00
01
1Q0
1
x x
1
1
1
Q+0 = L
Q
Q 0
0
1
1
0
x
1
1
P = Q′1Q0
FSM Modeling FSM Design PostScript FSM Analysis Analysis of a Moore Machine
Level to Pulse Converter Schematic: Moore Type
P
DL
Clock
Q
Q
D Q
Q1
Q0
Q1+
Q0+
Next state logic State memory Output logic
FSM Modeling FSM Design PostScript FSM Analysis Analysis of a Moore Machine
Level to Pulse Converter Moore Alternate StateDiagram
00P=0
01P=1
11P=0
L
L'
L
LL'
L'
FSM Modeling FSM Design PostScript FSM Analysis Analysis of a Moore Machine
Level to Pulse Converter Mealy State Diagram
0/0
1/1
Zero One 1/0
0/0
FSM Modeling FSM Design PostScript FSM Analysis Analysis of a Moore Machine
Level to Pulse Converter Mealy State Table
Current In Next Out CommentsState State
Q L Q+ P
0 0 0 0Waiting for rising edge
0 1 1 1
1 0 0 0Waiting for falling edge
1 1 1 0
Q+ = L
P = Q′L
FSM Modeling FSM Design PostScript FSM Analysis Analysis of a Moore Machine
Level to Pulse Converter Schematic: Mealy Type
P
L
Clock Q
D QQ+
FSM Modeling FSM Design PostScript FSM Analysis Analysis of a Moore Machine
Moore vs Mealy
Mealy: output = f (state, inputs)Moore: output = f (state only)
P(Moore)
L
Clock
State (Moore)
Zero One Zero
P(Mealy)
State (Mealy)
Zero One ZeroEdge
Moore vs Mealy level to pulse converter.
FSM Modeling FSM Design PostScript FSM Analysis Analysis of a Moore Machine
Synchronous Mealy
Mealy responds to inputs faster than Moore, but...Mealy has glitchy outputs
outputs can change in the middle of a clock periodi.e. asynchronous outputs
Solution: pass the output through a register
Nex
t Sta
teLo
gic
Sta
teR
egis
ters
Out
put
Logi
c
Outputs
Inputs
State
Out
put
Reg
iste
rs
