State%of%the%art*Electron*Devices:*Moore*and*more*things…*

Ted*Johansson*

Electronic*Circuits*and*Systems,*ISY

There are more things in heaven and earth, Horatio, Than are dreamt of in your philosophy. In Shakespeare’s Hamlet

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Chapters*covered*from*the*book:****21*Devices*for*the*Post*CMOS*Era****11*VLSI*Technology*and*Circuits**(partly)

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Outline: - Moore’s law, Dennard scaling, ITRS roadmap - scaling technology down to 8 nm - new channel materials and devices - some closing remarks

NB.*references*given*in*short*form*down*here.*If*not*given,*either*from*the*book*(chapter*21)*or*commercial*internet*sites.

Moore’s*law:*not*about*scaling,*but*economics3

G.*E.*Moore,*Electronics,*1965.

Moore*1965**(slope*=*2*years*per*doubling)

ISSCC*until*2011*(slope*=*1.5*years*per*doubling) 4

5Average*transistor*price*by*year

Moore,*ISSCC*2003

Dennard:*MOSFET*scaling6

• Voltage, current, dopings scale with gate length. As transistors get smaller their power density stays constant (prop. to area).

• Around 2005–2007, Dennard scaling appears to have broken down. At small sizes, current leakage poses greater challenges, and also causes the chip to heat up, which creates a threat of thermal runaway and therefore further increases energy costs.

• Greater focus on multicore processors but less efficient scaling than Dennard. No further increase in clock-speed (4 GHz apparently max achievable) because of thermal restrictions.

• ”Dark silicon” = not the full chip can be powered on due to thermal restrictions.

en.wikipedia.org/wiki/Dennard_scaling

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Dennard*et*al.,*Proc*IEEE,*1999.*

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2013 Overall Roadmap Technology Characteristics (ORTC) Table9

www.itrs.net

New*features*when*scaling*below*the*130*nm*CMOS*node

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• 90 nm: Channel strain (increased mobility, different strain required by NMOS and PMOS).

• 90 nm: PD-SOI (increase switching performance corresponding to one node but more expensive substrates).

• 45 nm: High-k dielectric replace SiO2 as gate material (reduced gate leakage)

• 28 nm: FD-SOI (no channel doping) • 22 nm: FinFETs (better charge control) • 22 nm: Metal-gate (less VT variations)

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Device*architecture*progression

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Bulk,*PD%SOI*and*FD%SOI

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28*nm*FD%SOI*(STM)*%*PDK*installed

Lg=24*nm,*Tox=1.8*nm,*Vsup=1.0*V*ultra%thin*silicon:*7*nm*ultra%thin*buried*oxide:*25*nm

High%k*dielectric*Metal%gate*electrode*S/D:*epitaxy*raised*Undoped*channel*Bulk/SOI*integration

For*stacked*PA*design:*Lg=150*nm,*Tox=2.8*nm,*Vsup=1.8*V*(+10*%)

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ETSOI

Cheng*et*al.*,*IEDM*2009

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The*Tri%Gate*or*FinFET

First*concept:*Huang*et*al.,*IEDM*1999

Intel*22*nm*with*extensions*for*SoC*design*(Jan*et*al.,*IEDM*2012)

Moore,*ISSCC*2003

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This*computer:*14*nm*FinFET*(i7@3.1*GHz)!

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Nanowire*device

Requirements*on*switching*devices18

• Signal drive (Ion for CMOS), but do not forget external parts (parasitics and contacts)

• On/Off ratio (Ion/Ioff: 104 - 106) • Gain (signal restoration) • Isolated input/outputs (gain, noise margin) • Connectivity between devices without significant

dissipative loss

• CMOS can be used down to 0.5 V but with reduced performance.

19Tunnel*FETMOSFET:*carriers*are*injected*over*a*barrier*into*the*channel.*SubVT%slope*limited*to*60*mV/dec*at*RT.*

Tunnel*FET:*carriers*are*injected*into*the*channel*by*band%to%band*tunneling*at*a*proper*alignment*of*conduction*and*valence*band*edges.*

Ion/Ioff*~*104

Ion/Ioff*~*104*%*106

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New*Channel*Materials*and*Devices

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• Requirements: • Fit into existing fab infrastructure • Work below 500 mV supply • Potential of continued performance growth

• Carbon Nanotubes • Spin devices • Graphene

Carbon*Nanotubes*(CNTs)23

• Clear device concept • CMOS compatible • Demonstrated down to 10 nm

A*carbon*nanotube*is*essentially*rolled*up*graphene

en.wikipedia.org/wiki/Carbon_nanotube_field%effect_transistor

CNTs

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• bandgap directly affected by chirality and diameter • no boundary scattering (quasi-1D materials) • chemically inert • can transport high currents • good heat conductor • little energy needed for a switch

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Backgated*CNTFETs

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Topgated*CNTFETs

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Wrap%around*gate*CNTFETs

Graphene

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• 2D-layer of carbon • similar transport properties as CNT but missing a

bandgap => • no pinch-off at high currents, • Ion/Ioff <10 at RT

• Suited for RF applications (but not logic?) • A bandgap can be created using patterns

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CMOS%compatible*graphene*process*(IBM)

200*mm*wafer*0.4*mm2*chip*Lg*=*0.9*um*fc*=*4.2*GHz

Han*et*al.,*Nature*2014

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Closing*remarks**(wrt.*technology*status*as*of*early*2012)

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• Conventional device will allow scaling to the 8 nm node: SOI, FinFET, maybe tubes.

• Trade-off high performance devices vs. low-power, low-cost etc.

• Below 8 nm: ? • Lot of speculations in the book. • From system’s point-of-view: equally important

with good strategies on higher system levels, not only devices (and contacts) (chapter 11)

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*The*combined*need*for*digital*and*non%digital*functionalities*in*an*integrated*system*is*translated*as*a*dual*trend*in*the*ITRS*roadmap:*miniaturization*of*the*digital*functions*(“More*Moore”)*and*functional*diversification*(“More%than%Moore”). www.itrs.net

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System%level*improvement:*3D%IC

Wide*I/O*controller*IP*solution*(CEA%LETI,*ST%Ericsson,*Cadence):*memory%on%logic*3D*stack*with*TSVs

www.liu.se

End*of*lecture.*

End*of*PhD%course.

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