Chapter 2 (cont.)

An Introduction to the 80x86 Microprocessor Family

Objectives:

The different addressing modes and instruction types available

The usefulness of interrupts

Some of the differences between the 8086 and the 80286, 80386, 80486 and Pentium microprocessors

EE314Microprocessor Systems

Based on "An Introduction to the Intel Family of Microprocessors" by James L. Antonakos

2.7 Addressing modes

F0000

E0000

D0000

C0000

B0000

A0000

90000

80000

70000

60000

50000

40000

30000

20000

10000

00000

FFFFF

00000

Real-Mode Addressing space

The addressing space of the processor in the real mode: •20 address bits used•1Mbyte wide•address 00000 to FFFFF•Logically Byte organized

A particular way to split memory in segments: non-overlapping

A segment is a 64KB memory block, beginning at a multiple-of-16 (10H) address

Overlapping segments

Superposed segments

The segment 38130H-4812FHThe content of the used segment register is 3813H.

Interrupt pointer

table

003FF

00000

Reset instruction

area

FFFFF

FFFF0

MOV CL,[ BP - 4]

2.7 Addressing modesSpecify the operand to be used. To generate an address, a segment register is used also.Immediate addressing: the operand is a number included in the instruction body.

MOV CX,1024Register addressing: the operand is a register.

ADD AL , BL

Direct addressing: the operand address is a number in [] or the value of a symbol (no [].)

MOV AX,[3000] MOV BL,COUNTER

Register indirect addressing: the register enclosed in [ ] specifies the operand address.

MOV BX,[SI]Indexed addressing: the operand address is the sum of the value of the index register and a number, both enclosed in [ ].

MOV BX,[ SI + 10]

Based addressing: is similar to indexed, but using BP (base pointer) register.Based-indexed addressing: the operand address is the sum of the values of BP and one of the index registers (SI or DI). MOV DS:[ BP + DI],AX

Based-indexed with displacement addressing: ads to the former an offset value.MOV DL,[ BP][ DI + 2] or MOV DL,[ BP + DI + 2]

Port addressing: used by input/output instructions. The address of the source port for IN or destination port for OUT is a number or a register content.

OUT 80H , AL IN AL, DX

The displacement is a signed 2’s complement byte or word

Segment overriding

2.7 Addressing modes32-Bit Addressing Mode

Base register

EAX EBX ECX EDXEBP ESI EDI ESP

+

Segment register

CS DS ESFS GS SS

Scale factor 1 2 4 8

Displacementnone8-bit32-bit

+Index register

EAX EBX ECX EDXEBP ESI EDI

*

+

Effective address

Ex: MOV EAX,[EBX][ECX*4+6]

0010 B4 09 MOV AH, 90012 8D 16 0000 R LEA DX, TABLE0016 CD 21 INT 21H0018 B4 09 MOV AH, 9001A 66 8D 1E 0000 R LEA EBX, TABLE001F 66 BA 00000002 MOV EDX, 20025 67 8D 14 93 LEA DX, [EBX][EDX*4]0029 CD 21 INT 21H

Prefixes to allow using 32-bit registers in real mode

2.8 InterruptsHardware and Software Interrupts

The nonmaskable interrupt is generated by en external device, via the NMI pin.Cannot be ignored by the microprocessor.

The maskable interrupts (0…FFH) can be generated by:

• an external device, via the INTR pin (the external device has to specify the interrupt number).(IF (interrupt flag) in FLAGS

register enables or disables the P to accept maskable interrupts.)

• microprocessor itself (i.e. when trying to divide by 0), (the interrupt number is hardware defined).

Software interrupts using the INT instruction (followed by the interrupt number).

The Interrupt Vector Table(or Interrupt Pointer Table)

The memory block from address 00000 to 003FF. There are 1024 bytes, each of the 256 maskable interrupts uses four bytes to store the address where the corresponding ISR (Interrupt Service Routine) begins. The ISR address for interrupt number xx is stored beginning at address xx*4, in form CS:IP. From low to high address, the bytes are stored in the order: IP low, IP high, CS low and CS high (byte swapping).

Example: The pointer for INT 21 is located at address: 21H*4=84H.C> debug-d 0:80 L 100000:0080 94 10 16 01 B4 16 26 07-4f 03 FB 0A 8A 03 FB 0A-q

CS=0726H IP=16B4H

INT 21 ISR:08914H

Hardwareinterrupts

2.9 The 8086: the first 80x86 Machine8088 and 8086 pin assignments

GNDA14A13A12A11A10A9A8

AD7AD6AD5AD4AD3AD2AD1AD0NMI

INTRCLKGND

VccA15A16/S3A17/S4A18/S5A19/S6

___

SS0 (HIGH)

___

MN/MX

___

RD

___ ____

HOLD (RQ/GT0)

___ ____

HLDA (RQ/GT1)

___ ______

WR (LOCK)

__ __

IO/M (S2)

__ __

DT/R (SI)

____ __

DEN (S0)ALE (QS0)

_____

INTA (QS1)

_____

TESTREADYRESET

1 40

8088

20 21

GNDAD14AD13AD12AD11AD10AD9AD8AD7AD6AD5AD4AD3AD2AD1AD0NMI

INTRCLKGND

VccAD15A16/S3A17/S4A18/S5A19/S6

____

BHE/S7

___

MN/MX

___

RD

___ ____

HOLD (RQ/GT0)

___ ____

HLDA (RQ/GT1)

___ ______

WR (LOCK)

__ __

IO/M (S2)

__ __

DT/R (SI)

____ __

DEN (S0)ALE (QS0)

_____

INTA (QS1)

_____

TESTREADYRESET

1 40

8086

20 21

2.9 The 8086: the first 80x86 Machine8086 8088 80286 80386 80486 Pentium

Gen. p. Reg. 8/16bit 8/16bit 8/16bit 8/16/32bit 8/16/32bit 8/16/32bitData BUS 16 8 16 32 32 64Address BUS 20 20 24 32 32 32Mem. Space 1MB 1MB 16MB 4GB 4GB 4GBModesCoprocessor 8087 8087 80287 80387 Internal Internal (80-bit)

MultitaskingVirtual mem. 1GB 64TB 64TBVirtual address.

Internal cache 8KB 8KB data / 8KB instructionArhitecture CISC/RISC

ALU Pipeline2 (two integer opp. or one floating point at a time)

BUS Pipeline two BUS cycles at a timeBurst R/W 32 bytes

Prefetch Buffer32 bytes read at once from

cacheBranch prediction (i.e.

CALL)

Real/Protected

Memory Menagement & Protection / Integrated Memory Menagement

adrress unit, segment descriptors, gate descriptorsMachine Status Word

Page Fault Liniar AddressControll Reg. Page Directory Base Add.

CISC=Complex Instruction Set Computer

Real