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Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-1
Chapter 16: Design for Testability
Prof. Soo-Ik Chae
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-2
Objectives
After completing this chapter, you will be able to:
Describe various fault models
Understand the fundamentals of fault detection
Understand the difficulties of sequential circuit tests
Understand the basic principles of test vector generation
Describe the basic principles of testable circuit design
Understand the principle of boundary scan standard
(IEEE1149.1)
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-3
Terminology Definition
A defect means the unintended difference between the
implemented hardware and its design.
Process defects
Material defects
Age defects
Package defects
An error is the wrong output signal produced by a defective
circuit.
A fault is a representation of a defect at an abstracted
function level.
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-4
Fault Models --- Stuck-at/Bridge Faults
The most common fault models used today:
A stuck-at-0 fault is modeled by assigning a fixed value
of 0 to a signal line or net in the circuit.
A stuck-at-1 fault is modeled by assigning a fixed value
of 1 to a signal line or net in the circuit.
A bridge fault is a shorting between
any set of lines (nets).
(a) Stuck-at-0 fault
s-a-0
0fa
b
(b) Stuck-at-1 fault
s-a-1
1a
b
f
f '
x
y
f
w
z
pMOS
circuit
S1
S2
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-5
Fault Models --- Stuck-Open/Closed Faults
A stuck-open fault is modeled as a switch being
permanently in open state.
A stuck-closed (stuck-on) fault is
modeled as a switch being
permanently in shorted state.
x
y
VDD
Q2p
Q1p
Q1n
Q2n
f (t+1) =
(x + y)'+x'yf(t) The effect of stuck-open fault is to
produce a floating state at the
output of the faulty logic circuit.
The effect of stuck-closed fault is
produce a power supply to ground
conducting path.
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-6
Fault Equivalence/Collapse/Coverage
Fault equivalence means two faults of a logic circuit
transform the circuit such that two faulty circuits have the
same output functions.
Fault collapse means the process to select one fault from
each equivalence set.
Collapse ratio = |set of collapsed faults| / |set of faults|
To achieve a world-class quality level, the fault coverage of
a circuit has in excess of 98.5%.
Fault coverage = number of detected faults / total number of
faults
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-7
Defe
ct
level
(dp
m)
Stuck-at fault coverage (%)
Clustered
faults, β = 0.083
Unclustered
faults, β =
(1 – 0.7623)×106
(1 – 0.7348)×106
Defect level
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-8
Fault Detection --- A Basic Model of CUT
The controllability of a particular node in a logic circuit is a
measure of the ease of setting the node to a 1 or a 0 from the
inputs.
The observability of a particular node in a logic circuit is the
degree to which you can observe the node at the outputs.
Circuit under
test (CUT)
Input
signals
Output
signals
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-9
Fault Detection --- Detectable and Undetectable Faults
A testable fault means that at least one input assignments can
be found to make the outputs different between the fault-free
and faulty circuits.
An untestable fault means a fault for which no test can be
found.
A redundant gate will cause some nets associated with it
to be untestable.x
y
zf
Redundant gate
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-10
Fault Detection --- An Example of Complete Test Set
With test vectors of {(0,1), (1,0), (1,1),
all stuck-at faults can be tested.
ab f
s-a-0
ab f
s-a-1
(a)
(b)(c)
a b ffault_free
ffaulty
Detectable faults
0 0
0 1
1 0
1 1
1
1
1
0
0
0
0
1 /0, /0,/1
/1,0
/1, /0
/0
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-11
Verification of state table
Transfer the machine into a known state: a homing sequence
Test all transitions form that state
Verify each transition by first taking the machine to a specific initial state, applying the input to perform the transition and then verifying the finalstate.
Difficulty of Sequential Circuit Test
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-12
Homing Sequence
A homing sequence is an input sequence that produces an
output response that uniquely indicates the state of a
machine after the homing sequence has been applied.
A preset homing sequence is a homing sequence that does
not employ the output response to determine subsequent
inputs in the sequence.
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-13
Example
PSNS, z
x0 1
A
B
C
D
B,0
B,0
D,0
B,0
A,1
A,0
C,1
C,1
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-14
Example: Homing Sequence
Initial
state
A
B
C
D
Input sequence
00 01 11
00 B
00 B
00 B
00 B
00 A
00 A
01 C
00 A
11 A
01 A
11 C
10 C
(ABCD)
(BD) (AC)
(B) (BD)
0
0 0
1
1 1
(A),(C) (A),(C)
PSNS, z
x0 1
A
B
C
D
B,0
B,0
D,0
B,0
A,1
A,0
C,1
C,1
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-15
Difficulty of Sequential Circuit Test
Initial
state
A
B
C
D
Input sequence
00 01 11
00 B
00 B
00 B
00 B
00 A
00 A
01 C
00 A
11 A
01 A
11 C
10 C
(ABCD)
(BD) (AC)
(B) (BD)
0
0 0
1
1 1
(A),(C) (A),(C)
PSNS, z
x0 1
A
B
C
D
B,0
B,0
D,0
B,0
A,1
A,0
C,1
C,1
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-16
Difficulty of Sequential Circuit Test
A transfer sequence for state Si and Sj of a sequential
machine is the shortest input sequence that will take the
machine from state Si to Sj.
A circuit is strongly connected if and only if there exists for
each ordered pair of states (Si, Sj) of the circuit an input
sequence that will transfer the circuit from state Si to Sj.
So what are the difficulties of testing sequential circuits?
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-17
Sequential Circuit Test
For a strongly connected state diagram, a proper sequence
can transfer the state diagram form one to another state.
What if not strongly connected?
Difficult to test it
Adding extra circuit that directly sets the state of the circuit.
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-18
Test Vector Generation
Four basic test vector generation approaches:
Fault tables
Fault simulation
Boolean differences
Path sensitization
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-19
Fault Tables
A fault table is a table that displays a set of faults and a set of
test inputs.
xy
z
af
x y z
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
f
1
0
1
0
1
0
0
0
fx0
fx1
fy0
fy1
fz0
fz1
fa0
fa1
ff0
ff1
1 1 1
0 0 0
1 0 1
0 0 0
1 1 1
0 0 0
1 0 1
0 0 0
1
0
1
0
0
0
0
0
1 0 1
1 0 0
1 0 1
1 0 0
1 0 1
1 0 0
0 0 1
0 0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Truth table Single stuck-at-fault truth table
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-20
Fault Tables
A fault detection table is a table that identifies which input
combinations detect a certain faults.
It is formed by performing the XOR of each output
column in fault table with the output of fault-free circuit.
x y z
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
f
1
0
1
0
1
0
0
0
0 0 0
0 0 0
0 1 0
0 0 0
0 0 0
0 0 0
1 0 1
0 0 0
0
0
0
0
1
0
0
0
0 1 0
1 0 0
0 1 0
1 0 0
0 1 0
1 0 0
0 0 1
0 0 0
1
0
1
0
1
0
0
0
1
0
1
0
1
0
0
0
0
1
0
1
0
1
1
1
Equivalent
faults
May delete
two rows
x0
x1
y0
y1
z0
z1
a0
a1
f0
f1
Equivalent faults
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-21
Fault Tables
A reduced fault table is a fault table that combines equivalent
faults and deletes the redundant rows in the fault detection
table.
The test vectors are: {(0,0,1), (0,1,0), (1,0,0), (1,1,0)}.
g = {x0, y
0, a
0}
h = {z1, a
1, f
0}
x y z
0 0 0
0 0 1
0 1 0
1 0 0
1 1 0
1 1 1
f
1
0
1
1
0
0
g x1
y1
z0 h f
1
0 0
0 0
0 1
0 0
1 0
0 0
0
0
0
1
0
0
0 1
1 0
0 1
0 1
0 0
0 0
0
1
0
0
1
1
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-22
Fault Simulation
The basic concept of fault simulation approach to test pattern
generation is to select a primary input combination and
determine its fault detection capabilities by simulation. The
process is repeated until:
All faults are covered,
At least an acceptable number of faults are covered, or
Some predefined stopping point is reached.
Simulation of
fault-free circuit
Simulation of
faulty circuit
ComparePrimary inputsDetected/
undetected
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-23
Fault Simulation
Types of fault simulation:
The row method
The column method
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-24
Fault Simulation
The row method
Test vectors = {(0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,1,0)}.
xy
z
af
0 0 0
1
Truth table
x y z
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
f
1
0
1
0
1
0
0
0
fx0
fx1
fy0
fy1
fz0
fz1
fa0
fa1
ff0
ff1
1 1 1
0 0 0
1 0 1
0 * 0
1 * 1
0 * 0
* 1
* * *
1
0
1
0
0
*
*
*
1 1
1 * 0
* * 1
* * 0
* * 1
* * 0
* * 1
* * *
*
*
*
*
*
*
*
*
*
*
*
*
*
*
1
1
*
*
*
*
*
*
Faults detected
z1, a1, f0
z0, f1
x1
y1
x0, y0, a0
* --- not simulated for this input pattern.
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-25
Fault Simulation
The column method
Test vectors = {(0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1),
(1,1,0)}.
xy
z
af
0 0 0
0
1
Truth table
x y z
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
f
1
0
1
0
1
0
0
0
fx0
fx1
fy0
fy1
fz0
fz1
fa0
fa1
ff0
ff1
1 1 *
0 0 *
1 1
0 * 0
1 * 1
0 * 0
0 1
* 0 *
1
0
1
0
0
*
0
0
* 1
* * 0
* * 1
* * 0
1 * 1
1 0 0
* 0 1
* 0 *
*
*
*
*
*
0
0
*
*
*
*
*
*
*
1
1
*
*
*
*
*
*
* --- not simulated for this input pattern.
Faults detected
z1, a1, f0
f1
x1
y1
x0, y0, a0
z0
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-26
Boolean Differences
Boolean difference of a switching function f(xn-1, …, x1, x0)
is defined as:
Boolean difference sometimes is called Boolean partial
derivative.
Boolean difference is not an effective way to compute
test patterns for large circuits.
)1()0(
),...,,1,,...,(),...,,0,,...,()(
01110111
ii
iiniin
ff
xxxxfxxxxfdx
Xdf
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-27
Boolean Differences
Example:
To test stuck-at-0 fault at net xi, it is required to compute:
To test stuck-at-1 fault at net xi, it is required to compute:
1)(
ii
dx
Xdfx
1)(
' i
idx
Xdfx
f X x x x( ) 1 2 3
32332332
33232321
'''
01)(
xxxxxxxx
xxxxxxxdx
Xdf
xi=1일때 output이다른경우가 test vector
xi=0일때 output이다른경우가 test vector
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-28
Boolean Differences
Stuck-at-0 fault at net is
The test vector set is {(0, 0, 1, 1), (1, f, 1, 0), (f, 1, 1, 0)}.
x1
x2
x3
x4
f
N1
N2
N3
N4
N5
N6
N7
N8
N9N10
G1
G2
G3
G4
G5
43321 ')( xxxxxXf
4324314321
3333
3
''''
)1()0(1)(
xxxxxxxxxx
ffxdx
Xdfx
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-29
Boolean Differences
Stuck-at-0 fault at net is
The test vector set is {(1, f, 0, f), (f, 1, 0, f)}.
x1
x2
x3
x4
f
N1
N2
N3
N4
N5
N6
N7
N8
N9N10
G1
G2
G3
G4
G5
21 xxy
433'),( xxyxyXf
3231321
343343
'''
''),(
xxxxxxx
yxxxxxxydy
yXdfy
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-30
Path Sensitization
Basic operations of path sensitization method:
Fault sensitization: A stuck-at fault is activated by forcing
the signal driving it to an opposite value from the fault
value.
Fault propagation: The fault effect is propagated through
one or more paths to a primary output of the circuit.
Line justification (Consistency operation): The internal
signal assignments previously made to sensitize a fault or
propagate its effect are justified by setting primary inputs
of the circuit.
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-31
Path Sensitization
Sensitized path is a path that can propagate the net value of
the primary inputs with a consistency operation for a stuck-
at-fault
Otherwise, unsensitized path
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-32
Path Sensitization
Sensitized path
Unsensitized path
x1
x2
x3
x4
fa
b
g
Sensitized path
x1
x2
x3
x4
f2
f1
h
s-a-0 Sensitizable path
Unsensitizable path1
2
1
0
0
1
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-33
Path Sensitization
(a) Single sensitized path
x1
f
x2
x3
x'2
x'3
a (s-a-0)
1
0
0
01
Inconsistence
1
(b) Multiple sensitized paths
x1
f
x2
x3
x'2
x'3
a (s-a-0)
1
1
0
0
1
DD’D’
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-34
A Simplified D Algorithm
pdcf (primitive D-cube of fault) of the five most commonly
used gates.
(a) AND gate (b) OR gate
(c) NAND gate (d) NOR gate (e) NOT gate
x y z Faults covered
0 0 D'
0 1 D'
1 0 D'
1 1 D
z/1
x/1, z/1
y/1, z/1
x/0, y/0, z/0
x y z Faults covered
0 0 D'
0 1 D
1 0 D
1 1 D z/0
x/0, z/0
y/0, z/0
x/1, y/1, z/1
x y z Faults covered
0 0 D
0 1 D
1 0 D
1 1 D'
z/0
x/1, z/0
y/1, z/0
x/0, y/0, z/1
x y z Faults covered
0 0 D
0 1 D'
1 0 D'
1 1 D' z/1
x/0, z/1
y/0, z/1
x/1, y/1, z/0
x
0
1
z Faults covered
D
D' x/0, z/1
x/1, z/0
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-35
A Simplified D Algorithm
pdc (propagation of D-cube): error propagation
sc (singular cover): fixed output
x y z
0 f 0
f 0 0
1 1 1
AND gate
x y z
1 1
1 1
0 0 0
OR gate
x y z x y z
NAND gate NOR gate NOT gate
x z
1 0
0 1
f
f
0 f 1
f 0 1
1 1 0
1 0
1 0
0 0 1
f
f
x y z
D' 1 D'
1 D' D'
D 1 D
1 D D
AND gate
x y z
D' 0 D'
0 D' D'
D 0 D
0 D D
OR gate
x y z
D' 1 D
1 D' D
D 1 D'
1 D D'
x y z
D 0 D'
0 D D'
D 0 D'
0 D D'
NAND gate NOR gate NOT gate
x z
D' D
D D'
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-36
A Simplified D Algorithm
A simplified D algorithm
1. Fault sensitization: Select a pdcf for the fault for which
a test pattern is to be generated.
2. D-drive: Use pdcs to propagate the D signal to at least
one primary outputs of the circuit.
3. Consistency operations: Use the sc of each logic module
to perform the consistency operation.
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-37
A Simplified D Algorithm
x1
x2
x3
x4
f
N1
N2
N3
N4
N5
N6
N7
N8
N9N10
G1
G2
G3
G4
G5
N1 N2 N3 N4 N5 N6 N7 N8 N9 N10
1 1 Dpdcf of G4
D0 Dpdc of G5 D-drive
1 f 1
f 1
sc of G1
10
0 0f
sc of G2
sc of G3
Consistency
operations
Fault sensitization
s-a-0
D
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-38
Testable Circuit Design
Testable circuit design is also called design for testability (DFT).
Ad hoc testing
uses some means to increase both observability and controllability of the circuits.
Scan-path methods
provide the observability and controllability at each register.
Built-in self-test (BIST)
relies on augmenting circuits to allow them to perform operations so as to prove the correct operation of the circuit.
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-39
Ad hoc Testing
Basic principles are to increase both the observability and
controllability of circuits.
Providing more control and test points
Using multiplexers to increase the number of internal
control and test points
Breaking feedback paths
Using state registers to reduce the additional of I/O pins
required for testing signals.
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-40
Ad hoc Testing
An example of exhaustive test: 8-but up/down counter with
two 4-bit up/down counters
256 cycles vs 16 cycles
T/N: test/normal
PL
MR QD
QC
QB
QA
TCU
PD
PC
PB
PA
TCD
CPU
CPD
PL
MR QD
QC
QB
QA
TCU
PD
PC
PB
PA
TCD
CPU
CPD
PD
PC
PB
PA
PH
PG
PF
PE
QD
QC
QB
QAQ
HQ
GQ
FQ
E
PL'
Clear
Up count
Down count
(Parallel load)
T/NTCD
CPD
TCU
CPU
01Y
01Y
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-41
Scan-Path Methods
An example of scan-path method
CP
YA
ARA=0
B
C
S
YB
YC
CLRS
LRCLR
INCCNT
SHRA
DCK
Q
Q'
preset
D
CK
Q
Q'clear
D
CK
Q
Q'clear
reset
RA[0]
ScanIn
ScanOutT/N
0
1
Y
0
1
Y
0
1
Y
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-42
BIST Principles
(a) ATE (Automatic test equipment)
Pass/fail
Compare
Capture
result
Expected
result
Circuit under
test (CUT)
Test vectors
P
StimuliResponse
signals
(b) Built-in self test (BIST)
Pass/fail
CompareResponse
compression
Fault-free
signature
Test vectors
(ATPG)
StimuliResponse
signals
Circuit under
test (CUT)
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-43
Automatic Test Pattern Generation (ATPG)(ALFSR)
PR-sequence generator
(b) Modular format
(a) Standard format
D
CK
Q
Q'
D
CK
Q
Q'
D
CK
Q
Q'
D
CK
Q
Q'n-1 n-2 1 0a2a
1a
0a
n-1a
n
clk
D
CK
Q
Q'
D
CK
Q
Q'
D
CK
Q
Q'
D
CK
Q
Q' 01n-2 an-2
an-1a
na
1a
0
clk
n-1
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-44
Automous linear feedback shift register (ALFSR)
A sample primitive polynomials for n from 1 to 60.
n f(x)
1, 2, 3, 4, 6,
7, 15, 22, 601+x+xn
1+x2+xn5, 11, 21, 29
10, 17, 20, 25,
28, 31, 41, 521+x3+xn
1+x4+xn9
23, 47 1+x5+xn
18
1+x2+x3+x4+xn
12
13
1+x+x4+x6+xn
1+x+x3+x4+xn
n f(x)
14, 16 1+x3+x4+x5+xn
1+x+x2+x5+xn19, 27
1+x+x2+x7+xn24
26 1+x+x2+x6+xn
1+x+x2+x23+xn30
32 1+x+x2+x22+xn
8
1+x7+xn
33
34
35
36
37
38
39
40
1+x13+xn
1+x+x14+x15+xn
1+x2+xn
1+x11+xn
1+x2+x10+x12+xn
1+x+x5+x6+xn
1+x4+xn
1+x2+x19+x21+xn
42 1+x+x22+x23+xn
n f(x)
1+x+x5+x6+xn43
44, 50 1+x+x26+x27+xn
1+x+x3+x4+xn45
46 1+x+x20+x21+xn
48
49
51, 53
54
55
56,59
57
58
1+x9+xn
1+x+x15+x16+xn
1+x24+xn
1+x+x21+x22+xn
1+x7+xn
1+x19+xn
1+x+x27+x28+xn
1+x+x36+x37+xn
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-45
Signature Generators
(b) MISR circuit example
D
CK
Q
Q'
D
CK
Q
Q'
D
CK
Q
Q'
D
CK
Q
Q'
CLK
D3 D2 D1 D0
(a) SISR Circuit example
D
CK
Q
Q'
D
CK
Q
Q'
D
CK
Q
Q'
D
CK
Q
Q'
CLK
Serial data
input
Serial input signature register
Multiple input signature register
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-46
A Signature Application Example
(b) A numerical example
of signature
(a) Logic diagram
Circuit under test
xy
z
SISR circuit
CLK
D
CK
Q
Q'
D
CK
Q
Q'
D
CK
Q
Q'
D
CK
Q
Q'
x y zInput Fault-free output Faulty output
f/0
and f/0
f/1
f
0 0 1
0 1 0
1 0 0
1 0 1
0
1
1
0
0101
0
1
1
0
0001
0
1
0
0
1100
1 1 0
1 1 1
0
0
1
0
0
0
f/1
0
0
0
0
0
0
0000
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-47
Signature Capability
For a particular fault-response, there are 2m-n - 1 erroneous
bit streams that will produce the same signature.
Theorem: For an input data stream of length m, if all possible
error patterns are equally likely, then the probability that an
n-bit signature generator will not detect an error is
where 2m - 1 is the total possible erroneous streams. For m
>> n, P(M) will approach 2-n.
12
2)(
m
nm
MP
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-48
A BILBO (built-in block observer) Example
(a) Logic diagram
(b) Function selection (c) Application example
D
CK
Q
Q'
D
CK
Q
Q'
D
CK
Q
Q'
D
CK
Q
Q'
M1M0
SCin
CLK
0
1
s
D3 D2 D1 D0
Q0Q1Q2Q3
SCout
M1 M0 Function
0 0
0 1
1 0
1 1 Parallel load
Scan mode
MISR
Clear register
PR
SG
Sig
nat
ure
gen
erat
or
Combinational
logic
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-49
IEEE 1149.1 --- The Boundary Scan Standard
The goals of the boundary scan standard are to :
provide a data transfer standard between ATE and the
devices on a PCB,
provide a method of interconnecting devices on a PCB,
provide a way of using test bus standard or BIST
hardware to find the faulty devices on a PCB.
Functions of boundary scan standard:
interconnection test
normal operation data observation
each device test
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-50
IEEE 1149.1 --- An Application Example
A boundary scan architecture used to test the entire board-
level module.
TDI
TDO
Application logic
Application logicApplication logic
Application logic
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-51
IEEE 1149.1 --- The Structure
The boundary scan standard mainly include five parts:
test access port (TAP),
data registers,
TDO driver,
instruction register and decoder
TAP controller.
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-52
IEEE 1149.1 --- The TAP Structure
TAP (test access port) consists of:
Test data registers (test DRs)
Instruction register and decoder
TAP controller
TDO driver
TDI
TMS
TCK
TDO
TRST(optional)
TA
P p
ort
TAP
controller
Instruction register
Instruction decoder
Reset_n
ClockIR
ShiftIR
UpdateIR
Enable
ClockDR
ShiftDR
UpdateDR
Mu
x
Mu
x
D
CK
Q
Q'
TCK_n
ShiftDR
TDO_ir
TDO driver
DRsBoundary scan register
Bypass register
Device identification register
Design specification register
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-53
IEEE 1149.1 --- Control Signals
Four control signals:
TCK (test clock, input) clocks tests into and out of the
chip.
TDI (test data input, input) input test data into the chip.
TDO (test data output, output) output test data out of the
chip.
TMS (test mode select, input) controls the test operations.
One optional reset signal
TRST_n (test reset) is an optional active-low
asynchronous reset signal, used to reset TAP controller
externally.
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-54
IEEE 1149.1 --- Control Signals
In the normal mode, TRST_n and TCK are held low and
TMS is held high to disable boundary scan.
To prevent race conditions, inputs are sampled on the
positive edge of TCK and output toggle on the negative edge.
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-55
IEEE 1149.1 --- The State Machine
Test-logic-reset
Run-test-idle
TMS = 0TMS = 1
Select-DR-scan Select-IR-scan
Capture-DR Capture-IR
Shift-DR Shift-IR
Exit1-DR Exit1-IR
Pause-DR Pause-IR
Exit2-DR Exit2-IR
Update-DR Update-IR
TMS = 0
TMS = 1
TMS = 1
TMS = 1
TMS = 1TMS = 1
TMS = 1
TMS = 1TMS = 1
TMS = 1
TMS = 1TMS = 1
TMS = 1TMS = 1
TMS = 1
TMS = 1
TMS = 0 TMS = 0
TMS = 0 TMS = 0
TMS = 0
TMS = 0
TMS = 0
TMS=0
TMS = 0
TMS=0
TMS= 0
TMS = 0
TMS = 0
TMS = 0
1111
1100 0111
0110
0010
0001
0011
0000
0101
0100
1110
1010
1001
1011
1000
1101
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-56
IEEE 1149.1 --- Instruction and Bypass Registers
Instruction register cell
Shift register
Instruction register
Bypass register structureD
CK
Q
Q'
TDI TDO_bp
ClockDR
ShiftDR
DinD
CK
Q
Q'
D
CK
Q
Q'
0
1Y
S
Qout
ScanOut
ScanIn
ClockIRShiftIR UpdateIR
QA
QB
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-57
IEEE 1149.1 --- A TDO Driver
TDO Driver
TMS is sampled at the positive edge of TCK.
TDO is sampled at the negative edge of TCK.
D
CK
Q
Q'
TDO_ir
TDO
Bypass TCK_nShiftDR
TDO_bs
TDO_bp
0
1Y
0
1Y
Enable
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-58
IEEE 1149.1 --- A Boundary Scan Cell
Operation modes of boundary scan cell (BSC):
Normal mode
Capture mode
Scan mode
Update mode
D
CK
Q
Q'
D
CK
Q
Q'
0
1Y
S
0
1Y
S
DinQout
ScanOut
ScanIn
ClockDRShiftDR UpdateDR
Mode
Normal mode
Scan modeCapture
mode
Update mode
QA
QB
BSC
4
Control: ShiftDR, ClockDR,
UpdateDR, Mode
Din Qout
ScanIn ScanOut
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-59
IEEE 1149.1 --- A Boundary Scan Cell
Boundary scan input pad configuration
Boundary scan output pad configuration
BSC
4
Input pad
To chip logic
From previous
cellTo next cell
Control
BSC
4
Output padFrom chip
logic
From previous
cellTo next cell
Control
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-60
IEEE 1149.1 --- A Boundary Scan Cell
Boundary scan
bidirectional pad
configuration
Boundary scan tri-state pad
configuration
BSC
4
Bidirectional
PADFrom chip
logic
From previous
cell
To next cell
Control
BSCTristate
BSC
Control
To chip logic
BSC
4
Tristate PADFrom chip
logic
From previous
cell
To next cell
Control
BSCTristate
Chapter 16: Design for Testability
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 16-61
IEEE 1149.1 --- A Complete Example
TDI
TMS
TCK
TDOTDO
driver
Application logic
I/O pads
Boundary scan path
Boundary scan cellsTRST_n(optional)
Bypass
register
Boundary scan path
Instruction register
TD
O_
ir
By
pas
s
En
able
TAP controller
TAP controller and IR
