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Chapter - 4
AN IMPROVED SPACE VECTOR PULSE WIDTH MODULATION
BASED ALGORITHMS FOR MULTILEVEL INVERTERS
4.1 INTRODUCTION
In the previous chapter, the conventional space vector pulse
width modulation algorithm and a novel approach for the generation
of space vector pulse width modulation for multilevel inverters based
on fractals are presented. But, the number of level increases, the
location of reference voltage vector, optimum switching sequence and
dwelling time calculations and the control algorithm becomes more
and more complex. To improve the performance of the multilevel
inverters, in this chapter an improved space vector pulse width
modulation algorithms are proposed and analyzed.
At first, a qualitative space vector pulse width modulation
algorithm for neutral point clamped multilevel inverter is presented. In
this method the duty cycles of reference voltage vectors are corrected
accordingly for identifying the location of the reference voltage vector
in each region. The appropriate switching sequence of the region and
calculation of the switching ON times for each state is estimated. This
scheme can be extended to high-level inverters. The results have been
presented and analyzed for inverters from two-level to seven-level
inverters. The total harmonic distortion have been calculated and
compared with lower levels also.
Then, an analytical space vector pulse width modulation
method for multi-level VSI is proposed based on the intrinsic relation
118
between multi-level and two-level space vector pulse width
modulation. In this method, the dwelling time of vector calculation is
derived from two-level inverter. By using a linear transformation, the
dwelling time of vectors for two-level VSI can be transformed into
multilevel VSI. A novel classification of voltage vectors is proposed to
determine switching pattern of PWM sequence and used upto the
eleven-level inverter, which can be extended to n-level inverter as well.
Finally, a space vector pulse width modulation algorithm using
decomposition method is presented for seven-level inverter. In this
method, the space vector diagram of the seven-level inverter is
decomposed into six space vector diagrams of four-level inverters. In
turn, each of these six space vector diagrams of four-level inverter is
decomposed into six space vector diagrams of three-level inverters and
each of these six space vector diagrams of three-level inverter are
decomposed into six space vector diagrams of two-level inverters. To
proceed with the switching state determination, the first one of these
hexagons is selected, based on the location of the target voltage
vector. Secondly, the original voltage reference vector is decremented
by the voltage vector that locates the origin of the selected two-level
hexagon. This, then, allows the determination of switching sequence
and calculation of the voltage vector duration to be done in the same
manner as for a conventional two-level inverter. The proposed method
reduces the algorithm complexity and the execution time. It can be
applied to the multi-level inverters above the seven-level also.
119
4.2 A QUALITATIVE SPACE VECTOR PULSE WIDTH MODULATION
ALGORITHM FOR MULTILEVEL INVERTERS
The sector identification can be done by using co-ordinate
transformation of the reference vector into a two dimensional co-
ordinate system. The sector can also be determined by resolving the
reference phase vector along a, b and c axis and by repeated
comparison with discrete phase voltages. After identifying the sector,
the voltage vectors at the vertices of the sector are to be determined.
Once the switching voltage space vectors are determined the switching
sequences can be identified using lookup tables. The calculations of
the duration of the voltage vectors can be simplified by mapping the
identified sector correspond to a sector of two-level inverter. To obtain
optimum switching, the voltage vectors are to be switched for their
respective durations, in a sequence such that only one switching
occurs as the inverter moves from one switching state to another.
The duty cycles of reference voltage vector will be m1, m2 and 1-
(m1+m2). The values of m1 and m2 are useful in identifying the region
where reference vector is located, which is the major problem in case
of multi-level inverters.
In this method, a correction to the duty cycles of reference
vector is applied to easily identify the location of reference vector in
each region of a multilevel inverter. Once the region is identified, the
appropriate switching sequence of the region can be identified. The
ON time period for each state can be calculated with the obtained
duty cycles.
120
4.2.1 Seven-level Neutral Point Clamped Inverter
The circuit diagram and space vector diagram of seven-level
neutral point clamped inverter are as shown in Fig. 4.1 and Fig. 4.2.
In case of seven-level inverter six switches from each phase-leg will be
ON at any point time to produce predetermined output at phases. The
possible switching combinations will be 343 with 216 redundant
states.
Fig. 4.1 Seven-level NPC inverter topology.
The space vector (Vref) constituted by the pole voltages of inverter
Vao, Vbo and Vco with 1200 phase displacement is defined;
3
4πj
co3
2πj
boaoref .eV.eVVV ++= (4.1)
P
n
Vdc2
Vdc1
Vdc1
Vdc3
Vdc2
Vdc3
bc
a
Ta1
Ta10
Ta9
Ta11
Ta12
Ta4
Ta5
Ta6
Ta7
Ta8
Ta2
Ta3
Tb1
Tb10
Tb9
Tb11
Tb12
Tb4
Tb5
Tb6
Tb7
Tb8
Tb2
Tb3
Tc1
Tc10
Tc9
Tc11
Tc12
Tc4
Tc5
Tc6
Tc7
Tc8
Tc2
Tc3
z
121
The dwelling time periods T1, T2 and T0 are
)3/sin(
)3/sin(1 π×
α−π××=
dc
sref
V
TVT (4.2)
)3/sin(
sin2 π×
α××=
dc
sref
V
TVT (4.3)
)( 210 TTTT s +−= (4.4)
Fig. 4.2 Space vector diagram of seven-level inverter.
In Multilevel inverters the reference voltage vector can be
reproduced in the average sense by switching amongst the inverter
states situated at the vertices, which are in the closest proximity to it.
In case of two-level inverter, the identification of reference vector
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655544433322211100
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622511400
611500
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466355244133022
366255144033
266155044
166055
665554443332221110
654543432321210
643532421310
632521410
621510
610
565454343232121010
465354243132021
365254143032
265154043
165054
065
564453342231120
664553442331220
653542431320
642531420
631520
620
464353242131020
364253142031
264153042
164053
064
563452341230
663552441330
652541430
641530
630463352241130
363252141030
263152041
163052
063
462351240
562451340
662551440
651540
640362251140
262151040
162051
062
461350
561450
661550
650361250
261150
161050
061
060 160 260 360 460 560 660
656545434323212101
645534423312201
634523412301
623512401
612501
601
556445334223112001
456345234123012
356245134023
256145034
156045
056
122
location in a sector is straight forward. However, in higher level
inverter, the existence of more than one number of regions in sector
will require additional mathematical computation to identify the
region where the reference vector is located. The duty cycles (ON time
for each state) will be found by equating volt-seconds of reference
voltage with the nearest three states.
332211 VdVdVdm ++= (4.5)
where d1, d2 and d3 are duty cycles of the nearest voltage vectors
V1, V2 and V3 and ‘m’ is the voltage reference vector.
4.2.1.1 Calculation of duty cycles
The vector states at vertices of each region can be identified
from space vector diagrams. Consider the space vector diagram of
sector-I of Seven-level inverter, shown in Fig. 4.3.
Fig. 4.3 Sector-I of seven-level inverter.
006 106 206 306 406 506 606
416305
516405
616504
605316205
216105
116005
016
426315204
526415304
626515404
625504
604326215104
226115004
126015
026
536425314203
636525414303
625514403
614503
603436325214103
336225114003
236125014
136025
063
546435323213102
646535424313202
635524413302
624513402
613502
602
446335224113002
346235124013
246135024
146035
046
656545434323212101
645534423312201
634523412301
556445334223112001
456345234123012
356245134023
26
30
28
27
34
33
32
31
36
35
m7
m6
m31
m61
m71
m32
m72
m62
0 V/2 VV/6
4
21
1 2m
3
29
3
123
The reference vector m3 is located in region 2 of three-level
inverter. The m6 and m7 are reference vectors located in region 21 of
six-level inverter and region 29 of seven-level inverter respectively. mx1
and mx2 (x=3 or 6 or 7) are projections of reference vectors on to zero
axis and sixty degrees axis (angle ‘θ’ is angle made by reference vector
from zero axis i.e., starting of sector 1; be noted m3, m6 and m7 have
different angle ‘θ’ value).
The reference vector can be synthesized by sequential switching
operation of nearest three switching states (vertices of the region in
which reference vector is located).
The lengths of new vectors can be found using the equations as
( )( )3/sin2
3/sincos
2
1
θ××=
θ−θ×=
mm
mm (4.6)
The values of m1 and m2 for reference vector in each region can
be calculated with Eq. (4.6). The duty cycles of vertices of reference
voltage will be m1, m2 and [1-(m1+m2)]. For example, with reference to
m3 (reference vector in region 2), the reference vector can be
synthesized by switching vectors V1, V2 and V3. It shall be important to
note that duty cycle for switching state V1 shall be length of the vector
joining V3 and V1, whereas, m1 is the projection of reference vector m3
from the origin. As such, the corrected duty cycle for switching state
V1 in present case would be (m1-0.167). The length of vector joining V3
and V2 is m2. As such, corrected duty cycles for switching states V1, V2
and V3 would be (m1-0.167), m2 and (0.833-m1-m2) respectively.
The values of m1 and m2 are useful in identifying the region
where reference vector is located, which is the major problem in
124
multilevel inverters. The conditions for identifying reference vector
location in each region and the corrected duty cycles for each of the
level of inverter are shown in Table 4.1. Once the region is identified,
the appropriate switching sequence of that region can be identified.
The ON time period for each state can be calculated with duty
cycles obtained:
TON for state1 = Ts x m1
TON for state2 = Ts x m2
TON for state3 = Ts x [1- (m1+m2)] (4.7)
4.2.1.2 A Qualitative SVPWM Algorithm
1. Find the sector in which Vref lies.
2. Calculate m1, m2 from Eq. (4.6) and compute (m1+m2) of reference
voltage.
3. Find the region in which Vref is located.
4. Identify the nearest three vectors (vertices of region) of the Vref.
5. Select appropriate switching sequences.
6. Compute ON time for each switching state.
7. Place the inverter states in the respective states for the calculation
of switching ON times.
4.2.1.3 Flowchart
125
Fig. 4.4 Flowchart of qualitative space vector pulse width modulation for multilevel inverter.
Start
Read the inputs: dc voltage (Vdc
), reference voltage (Vref
),
sampling time (Ts) and modulation index (m)
Calculate actual Vref
= Vdc
* m
Find the sector in which Vref
is located
Calculate lengths of Vref
on -axis and 600 line
Identify the region of Vref
Calculate corrected duty cycles of three vertices of region
Identify the optimum switching sequence
Calculate T1, T
2 and T
0 for each
switching state (Ts * duty cycle for vector)
Generate control signals for corresponding ON times and place the switches in ON state
End
Is sector completed?
Is cycle completed?
Yes
Yes
No
No
126
4.2.1.4 Location of Reference Vector and Correction of Duty
cycles
The conditions for identifying reference vector location in seven-
level inverter and the corrections required to duty cycles are indicated
in Table 4.1. The switching ON and OFF sequences are as shown in
Table 4.2.
Table 4.1 Location of reference vector and corrected duty cycles
Region Condition for location
of reference vector
Corrected m1, m2 and m3
for switching states
26
0.834<m1<1 ;
m2<0.167;
(m1+ m2)<1
m1= m1-0.833;
m2= m2;
m3=1- m1- m2
27
0.667 < m1<0.834;
m2<0.167 ;
(m1+ m2)>0.834
m1=0.833-m1;
m2=0.167- m2;
m3= m1+ m2-0.834
28
0.667 <m1<0.834;
0.167 < m2<0.333;
(m1+ m2)<1
m1=m1-0.667;
m2=m2-0.167;
m3=1- m1- m2
29
0.5< m1<0.667;
0.167< m2<0.333;
(m1+ m2)>0.834
m1=0.667-m1;
m2=0.333- m2;
m3= m1+ m2-0.834
30
0.5< m1<0.667 ;
0.333< m2<0.5;
(m1+ m2)<1
m1= m1-0.5;
m2= m2-0.333;
m3=1- m1- m2
31
0.333<m1<0.5;
0.333< m2<0.5;
(m1+ m2)>0.834
m1=0.5 -m1;
m2=0.5- m2;
m3= m1+ m2-0.834
32
0.333<m1<0.5;
0.5< m2<0.667;
(m1+ m2)<1
m1= m1-0.333;
m2= m2-0.5;
m3=1- m1- m2
127
33
0.167<m1<0.333;
0.5<m2<0.667;
(m1+m2)>0.834
m1= 0.5-m1;
m2= 0.667-m2;
m3=m1+ m2-0.834
34
0.167<m1<0.333;
0.667<m2<0.834;
(m1+m2)<1
m1= m1-0.167;
m2= m2-0.667;
m3=1- m1- m2
35
m1<0.167;
0.667<m2<0.834;
(m1+m2)>0.834
m1= 0.167-m1.;
m2= 0.834-m2;
m3=m1+ m2-0.834
36
m1<0.167;
0.834<m2<1;
(m1+m2)<1
m1= m1;
m2= m2-0.834;
m3=1- m1- m2
Table 4.2 Switching sequence of seven-level inverter
Sector Region ON SequenceOFF Sequence
1 26 500 600 610 611 611 610 600 500
27 500 510 610 611 611 610 510 500
28 510 610 620 621 621 620 610 510
29 510 520 620 621 621 620 520 510
30 520 620 630 631 631 630 620 520
31 520 530 630 631 631 630 530 520
32 530 630 640 641 641 640 630 530
33 530 540 640 641 641 640 540 530
34 540 640 650 651 651 650 640 540
35 540 550 650 651 651 650 550 540
36 550 650 660 661 661 660 650 550
2 47 050 060 160 161 161 160 060 050
46 050 150 160 161 161 160 150 050
45 150 160 260 261 261 260 160 150
44 150 250 260 261 261 260 250 150
43 250 260 360 361 361 360 260 250
128
42 250 350 360 361 361 360 350 250
41 350 360 460 461 461 460 360 350
40 350 450 460 461 461 460 450 350
39 450 460 560 561 561 560 460 450
38 450 550 560 561 561 560 550 450
37 550 560 660 661 661 660 560 550
3 48 050 060 061 161 161 061 060 050
49 050 051 061 161 161 061 051 050
50 051 061 062 162 162 062 061 051
51 051 052 062 162 162 062 052 051
52 052 062 063 163 163 063 062 052
53 052 053 063 163 163 063 053 052
54 053 063 064 164 164 064 063 053
55 053 054 064 164 164 064 054 053
56 054 064 065 165 165 065 064 054
57 054 055 065 165 165 065 055 054
58 055 065 066 166 166 066 065 055
4 69 005 006 016 116 116 016 006 005
68 005 015 016 116 116 016 015 005
67 015 016 026 126 126 026 016 015
66 015 025 026 126 126 026 025 015
65 025 026 036 136 136 036 026 025
64 025 035 036 136 136 036 035 025
63 035 036 043 146 146 043 036 035
62 035 045 043 146 146 043 045 035
61 045 046 056 156 156 056 046 045
60 045 055 056 156 156 056 055 045
59 055 056 066 166 166 066 056 055
5 70 005 006 106 116 116 106 006 005
71 005 105 106 116 116 106 105 005
129
72 105 106 206 216 216 206 106 105
73 105 205 206 216 216 206 205 105
74 205 206 306 316 316 306 206 205
75 205 305 306 316 316 306 305 205
76 305 306 406 416 416 406 306 305
77 305 405 406 416 416 406 405 305
78 405 406 506 516 516 506 406 405
79 405 505 506 516 516 506 505 405
80 505 506 606 616 616 606 506 505
6 91 500 600 601 611 611 601 600 500
90 500 501 601 611 611 601 501 500
89 501 601 602 612 612 602 601 501
88 501 502 602 612 612 602 502 501
87 502 602 603 613 613 603 602 502
86 502 503 603 613 613 603 503 502
85 503 603 604 614 614 604 603 503
84 503 504 604 614 614 604 504 503
83 504 604 605 615 615 605 604 504
82 504 505 605 615 615 605 505 504
81 505 605 606 616 616 606 605 505
4.2.2 Results and Discussions
To validate the proposed qualitative space vector pulse width
modulation algorithm for multilevel inverters, the simulation studies
have been carried out for two-level, three-level, four-level, five-level,
six-level and seven-level inverters. The simulation parameters and
specifications of induction motor used in this method are given in
Appendix-III. The results for two-level inverter are shown in Fig. 4.5 to
Fig. 4.10. The phase voltages and line voltages of two-level inverter are
130
shown in Fig. 4.5 and Fig. 4.6. The output line voltage and its
harmonic spectrum are shown in Fig. 4.7. The stator currents, rotor
speed and torque responses of two-level inverter fed induction motor
are shown in Fig. 4.8 to Fig. 4.10. The results for three-level inverter
are shown in Fig. 4.11 to Fig. 4.16. The phase and line voltages are
shown in fig. 4.11 and Fig. 4.12. The output line voltage and its
harmonic spectrum are shown in Fig. 4.13. The stator currents, rotor
speed and torque responses of three-level inverter fed induction motor
are shown in Fig. 4.14 to Fig. 4.16. The results of four-level inverter
are shown in Fig. 4.17 to Fig. 4.22. The phase voltages, line voltages,
output line voltage and its harmonic spectrum are shown in Fig. 4.17
to Fig.4.19. The stator currents, rotor speed and torque responses of
four-level inverter fed induction motor are shown in Fig. 4.20 to Fig.
4.22. The results of five-level inverter are shown in Fig. 4.23 to Fig.
4.28. The phase voltages, line voltages, output voltage harmonic
spectrum and THD are shown in Fig. 4.23 to Fig.4.25. The stator
currents, rotor speed and torque of five-level inverter fed induction
motor are shown in Fig. 4.26 to Fig. 4.28. The results of six-level
inverter are shown in Fig. 4.29 to Fig. 4.34. The phase voltages, line
voltages, output line voltage and its harmonic spectrum are shown in
Fig. 4.29 to Fig.4.31. The stator currents, rotor speed and torque
responses of six-level inverter fed induction motor are shown in Fig.
4.32 to Fig. 4.34. The results of seven-level inverter are shown in Fig.
4.35 to Fig. 4.40. The phase voltages, line voltages and its harmonic
spectrum are shown in Fig. 4.35 to Fig.4.37. The stator currents, rotor
131
speed and torque responses of seven-level inverter fed induction motor
are shown in Fig. 4.38 to Fig. 4.40 The output line voltage harmonic
spectrum of two-level, three-level, four-level, five-level, six-level and
seven-level inverters are shown in Fig. 4.7, Fig. 4.13, Fig. 4.19, Fig.
4.25, Fig. 4.31 and Fig. 4.37 respectively which show the reduction of
THD with increase level of inverter. The improvement in the stator
currents of two-level, three-level, four-level, five-level, six-level and
seven-level inverter fed induction motor is shown in Fig. 4.8, Fig. 4.14,
Fig. 4.20, Fig. 4.26, Fig. 4.32 and Fig. 4.38 respectively. The torque
response of two-level, three-level, four-level, five-level, six-level and
seven-level inverter fed induction motor can be observed in Fig. 4.10,
Fig. 4.16, Fig. 4.22, Fig. 4.28, Fig. 4.34 and Fig. 4.40. From these
results, it is observed that as the level of the inverter is increased, the
THD is decreased and torque ripples also greatly reduced.
4.2.2.1 Two-level Inverter
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-300
-150
0
150
300
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-300
-150
0
150
300
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-300
-150
0
150
300
Time (s)
Pha
se v
olta
ges
Van
, Vbn
, Vcn
(V
)
Fig. 4.5 Phase voltages of two-level inverter.
132
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-400
-200
0
200
400
Line
vol
tage
s V
ab, V
bc, V
ca (
V)
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-400
-200
0
200
400
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-400
-200
0
200
400
Time (s)
Fig. 4.6 Line-to-line voltages of two-level inverter.
0 0.02 0.04 0.06 0.08-400
-200
0
200
400
Time (s)
FFT window: 5 of 50 cycles of selected signal
0 200 400 600 800 10000
5
10
15
20
25
Frequency (Hz)
Fundamental (50Hz) = 341.6 , THD= 42.48%
Mag
(%
of F
unda
men
tal)
Fig. 4.7 Output line voltage and its harmonic spectrumof two-level inverter.
133
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-60
-40
-20
0
20
40
60
Time (S)
Sta
tor
curr
ents
Ias,
Ibs,
Ics
(A)
Fig. 4.8 Stator currents of two-level inverter fed induction motor.
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
0
20
40
60
80
100
120
140
160
Time (s)
Rot
or s
peed
Wm
(ra
d/s)
Fig. 4.9 Speed response of two-level inverter fed induction motor.
134
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-10
0
10
20
30
40
50
60
70
Time (s)
Tor
que
Te
(N-m
)
Fig. 4.10 Torque response of two-level inverter fed induction motor.
4.2.2.2 Three-level Inverter
Fig. 4.11 Phase voltages of three-level inverter.
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-300
-150
0
150
300
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-300
-150
0
150
300
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-300
-150
0
150
300
Time (s)
Phase voltages Van, Vbn, Vcn (V)
135
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-400
-200
0
200
400
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-400
-200
0
200
400
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-400
-200
0
200
400
Time (s)
Line
vol
tage
s V
ab, V
bc, V
ca (
V)
Fig. 4.12 Line-to-voltages of three-level inverter.
0 0.02 0.04 0.06 0.08-400
-200
0
200
400
Time (s)
FFT window: 5 of 50 cycles of selected signal
0 200 400 600 800 10000
2
4
6
8
10
12
Frequency (Hz)
Fundamental (50Hz) = 306.4 , THD= 24.99%
Mag
(%
of F
unda
men
tal)
Fig. 4.13 Output line voltage and its harmonic spectrum of three-level inverter.
136
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-60
-40
-20
0
20
40
60
Time (S)
Sta
tor
curr
ents
Ias,
Ibs,
Ics
(A)
Fig. 4.14 Stator currents of three-level inverter fed induction motor.
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
0
20
40
60
80
100
120
140
160
Time (s)
Rot
or s
peed
Wm
(ra
d/s)
Fig. 4.15 Speed response of three-level inverterfed induction motor.
137
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-10
0
10
20
30
40
50
Time (s)
<Electromagnetic torque Te (N*m)>
Tor
que
Te
(N-m
)
Fig. 4.16 Torque response of three-level inverter fed induction motor.
4.2.2.3 Four-level Inverter
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-300
-150
0
150
300
Pha
se v
olta
ges
Van
, Vbn
, Vcn
(V
)
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-300
-150
0
150
300
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-300
-150
0
150
300
Time (s)
Fig. 4.17 Phase voltages of four-level inverter.
138
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-400
-200
0
200
400
Line
vol
tage
s V
ab, V
bc, V
ca (
V)
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-400
-200
0
200
400
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-400
-200
0
200
400
Time (s)
Fig. 4.18 Line-to line voltages of four-level inverter.
0 0.02 0.04 0.06 0.08-400
-200
0
200
400
Time (s)
FFT window: 5 of 50 cycles of selected signal
0 200 400 600 800 10000
2
4
6
8
Frequency (Hz)
Fundamental (50Hz) = 332.1 , THD= 17.05%
Mag
(%
of F
unda
men
tal)
Fig. 4.19 Output line voltage and its harmonic spectrum of four-level inverter.
139
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-60
-40
-20
0
20
40
60
Time (S)
Sta
tor
curr
ents
Ias,
Ibs,
Ics
(A)
Fig. 4.20 Stator currents of four-level inverter fed induction motor.
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
0
20
40
60
80
100
120
140
160
Time (s)
Rot
or s
peed
Wm
(ra
d/s)
Fig. 4.21 Speed response of four-level inverterfed induction motor.
140
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-10
0
10
20
30
40
50
60
Time (s)
Tor
que
Te
(N-m
)
Fig. 4.22 Torque response of four-level inverterfed induction motor.
4.2.2.4 Five-level Inverter:
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-300
-150
0
150
300
Pha
se v
olta
ges
Van
, Vbn
, Vcn
(V
)
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-300
-150
0
150
300
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-300
-150
0
150
300
Time (s)
Fig. 4.23 Phase voltages of five-level inverter.
141
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-400
-200
0
200
400
Line
vol
tage
s V
ab, V
bc, V
ca (
V)
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-400
-200
0
200
400
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-400
-200
0
200
400
Time (s)
Fig. 4.24 Line-to-line voltages of five-level inverter.
0 0.02 0.04 0.06 0.08-400
-200
0
200
400
Time (s)
FFT window: 5 of 50 cycles of selected signal
0 200 400 600 800 10000
1
2
3
4
5
6
Frequency (Hz)
Fundamental (50Hz) = 198.3 , THD= 11.57%
Mag
(%
of F
unda
men
tal)
Fig. 4.25 Output line voltage and its harmonic spectrumof five-level inverter.
142
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-60
-40
-20
0
20
40
60
Time (S)
Sta
tor
curr
ents
Ias,
Ibs,
Ics
(A)
Fig. 4.26 Stator currents of five-level inverterfed induction motor.
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
0
20
40
60
80
100
120
140
160
Time (s)
Rot
or s
peed
Wm
(ra
d/s)
Fig. 4.27 Speed response of five-level inverter fed induction motor.
143
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-10
0
10
20
30
40
50
60
Time (s)
Tor
que
Te
(N-m
)
Fig. 4.28 Torque response of five-level inverterfed induction motor.
4.2.2.5 Six-level Inverter
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-300
-150
0
150
300
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-300
-150
0
150
300
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-300
-150
0
150
300
Time (s)
Pha
se v
olta
ges
Van
, Vbn
, Vcn
(V
)
Fig. 4.29 Phase voltages of six-level inverter.
144
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-400
-200
0
200
400
Line
vol
tage
s V
ab, V
bc, V
ca (
V)
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-400
-200
0
200
400
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-400
-200
0
200
400
Time (s)
Fig. 4.30 Line-to-line voltages of six-level inverter.
0 0.02 0.04 0.06 0.08-400
-200
0
200
400
Time (s)
FFT window: 5 of 50 cycles of selected signal
0 200 400 600 800 10000
1
2
3
4
Frequency (Hz)
Fundamental (50Hz) = 365.1 , THD= 6.71%
Mag
(%
of F
unda
men
tal)
Fig. 4.31 Output line voltage and its harmonic spectrumof six-level inverter.
145
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-60
-40
-20
0
20
40
60
Time (s)
Sta
tor
curr
ents
Ia, I
b, Ic
(A
)
Fig. 4.32 Stator currents of six-level inverter fed induction motor.
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-20
0
20
40
60
80
100
120
140
160
Time (s)
Rot
or s
peed
Wm
(ra
d/s)
Fig. 4.33 Speed response of six-level inverter fed induction motor.
146
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-10
0
10
20
30
40
50
60
70
Time (s)
Tor
que
Te
(N-m
)
Fig. 4.34 Torque response of six-level inverterfed induction motor.
4.2.2.6 Seven-level Inverter
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-300
-150
0
150
300
Pha
se v
olta
ges
Van
, Vbn
, Vcn
(V
)
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-300
-150
0
150
300
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-300
-150
0
150
300
Time (s)
Fig. 4.35 Phase voltages of seven-level inverter.
147
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-400
-200
0
200
400
Line
vol
tage
s V
ab, V
bc, V
ca (
V)
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-400
-200
0
200
400
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-400
-200
0
200
400
Time (s)
Fig. 4.36 Line-to-line voltages of seven-level inverter.
0 0.02 0.04 0.06 0.08-400
-200
0
200
400
Time (s)
FFT window: 5 of 50 cycles of selected signal
0 200 400 600 800 10000
0.5
1
1.5
2
2.5
Frequency (Hz)
Fundamental (50Hz) = 375.9 , THD= 4.67%
Mag
(%
of F
unda
men
tal)
Fig. 4.37 Output line voltage and its harmonic spectrum of seven-level inverter.
148
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-60
-40
-20
0
20
40
60
Time (s)
Sta
tor
curr
ents
Ia, I
b, Ic
(A
)
Fig. 4.38 Stator currents of seven-level inverterfed induction motor.
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-20
0
20
40
60
80
100
120
140
160
Time (s)
Rot
or s
peed
Wm
(ra
d/s)
Fig. 4.39 Speed response of seven-level inverter fed induction motor.
149
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-10
0
10
20
30
40
50
60
70
Time (s)
Tor
que
Te
(N-m
)
Fig. 4.40 Torque response of seven-level inverter fed induction motor.
Table 4.3 Total harmonic distortion of Multi-level Inverters
Inverter THDTwo-level inverter 42.48%
Three-level inverter 24.99%Four-level inverter 17.05%Five-level inverter 11.57%Six-level inverter 6.71%
Seven-level inverter 4.67%
4.3 AN ANALYTICAL SPACE VECTOR PWM METHOD FOR
MULTILEVEL INVERTER BASED ON TWO-LEVEL INVERTER
150
In space vector pulse width modulation, the required voltage
vector is synthesized from a number of voltage vectors of various
switching states. The nearest three vectors algorithm is the optimal
solution for the synthesis of required voltage vector. These nearest
three vectors give the excellent spectral quality.
4.3.1 Relation between Three-Level and Two-Level SVPWM
The first step of the nearest three vector algorithm is to
determine the sub-section in which the reference vector located and
the second step is to calculate the dwelling times of each vector. As
the number of inverter levels increases, the sub-section becomes very
small. In this section, an analytical SVPWM algorithm for multi-level
inverters is explained.
4.3.1.1 SVPWM for two-level inverter
The two-level inverter space vector diagram is as shown in Fig.
4.41. The reference voltage vector is described
3
π4j
C3
π2j
BA eVeVVV ++= *
(4.8)
The switching times of the SVPWM based inverter can be
calculated by using volt-sec. relation. The volt-sec. balance equation
in matrix form is
=
T
TjV
TV
T
t
t
100
0jVjV
0VV
y
x
2
1
y2y1
x2x1*
*
'
'
''
''
(4.9)
The switching times of vectors are
151
θ)3
πmTsin(t 1
' −=
)sin(2' θ=mTt (4.10)
2'
1'
0' ttTt −−=
Where m = modulation index, ‘θ’ is angle of rotation, t'1, t'2 and
t'0 are switching times of voltage vectors V'1, V'2 and V'0 respectively.
Fig. 4.41 Space vector diagram of two-level inverter.
4.3.1.2 Switching times Calculation for three-level inverter
Fig. 4.42 shows the space vector diagram of three-level inverter
in sextant-I. The relation between the switching times and voltage
vectors are given by
TVVtVtVt 332211*=++
Tttt 321 =++ (4.11)
In the matrix form
=
T
TjV
TV
t
t
t
jVjVjV
VVV
y
x
yyy
xxx*
*
3
2
1
321
321
111
(4.12)
The relation between two-level and three-level voltage vectors is
given by
( ) ( )y21
1y11
1x21
1x11
121
111
11 VbVajVbVaVbVaV +++=+=
V'0
V*
V'1
V'2
θ
152
( ) ( )yyxx VbVajVbVaVbVaV 21
211
221
211
221
211
22 +++=+=
( ) ( )yyxx VbVajVbVaVbVaV 21
311
321
311
321
311
33 +++=+=
(4.13)
Describing Eq. (4.13) matrix form and substituting in Eq. (4.12)
gives
=
T
TjV
TV
t
t
t
bbb
aaa
jVjV
VV
y
x
yy
xx*
*
3
2
1
321
321
21
11
21
11
111100
0
0
(4.14)
Comparing Eq. (4.14) with Eq. (4.9) and considering that the
first left matrix is reversible, and then, the switching times for three-
level inverter is described
=
T
t
t
t
t
t
bbb
aaa
2'
1'
3
2
1
321
321
111
(4.15)
From Eq. (4.15), the switching times for three-level inverter can
be described
=
−
3
2
1
2'
1'1
321
321
111 t
t
t
T
t
t
bbb
aaa
(4.16)
The switching times of three-level inverter can be obtained from
the solution of Eq. (4.16). Thus from a linear transformation between
two-level and three-level inverter, the switching times of three-level
inverters can be derived. This method can be extended to n-level
inverter.
4.3.2 Switching States and Switching Sequence
153
4.3.2.1 Three-level Inverter
The switching states of three-level inverter can be classified into
four groups based on their magnitudes and represented by a space
vector diagram as shown in Fig. 4.42. They can be classified into zero
vectors, small vectors (vertices of inner hexagon), medium vectors
(mid-points of sides of outer hexagon), and large vectors (vertices of
outer hexagon). Both the zero and small vectors have redundant
switching states.
Fig. 4.42 Space vector diagram of three-level inverter in sextant-I.
The space vector diagram of the three-level inverter is divided
into six sextants, and each sextant is divided into four triangular
regions in order to show the vectors nearest to the reference. The
three-level inverter consists of zero voltage vectors (ZVV), lower Small
voltage vectors (LSVV), upper small voltage vectors (USVV), middle
voltage vectors (MVV) and large voltage vectors (LVV) as shown in
Table 4.4.
A new method is proposed for the generation of voltage vectors
2 0 0, Y
2 2 0, Y
2 1 0, Y1 0 0, X
0 0 01 1 12 2 2
2 2 1, X1 1 0, Y 2 1 0, X
Ta
Tc
Ta
Ta
Tc
Tb
A4
A2
A1
A3
154
switching pattern. The voltage vectors are divided into X and Y groups
as shown in Table 4.5. If one vector belongs to X group, then the
vector with one level only changing in one phase belongs to the Y
group. Thus, all middle voltage vectors belong to X group and all large
voltage vectors belong to Y group. The lower small voltage vectors and
upper small voltage vectors belong to X group and Y group
respectively. Thus, the output vector always alternate between X-
group and Y-group. After odd times varying, vector reach the other
group, and even times varying, vector reach the same group.
Table 4.4 Classification of voltage vectors
Voltage vector Symbols
ZVV (000),(111),(222)
LSVV (100),(010),(001), (110),(101),(011)
USVV (211),(121),(112), (221),(212),(112)
MVV (210),(120),(021), (012),(102),(201)
LVV (200),(220),(020), (022),(002),(202)
Table 4.5 Classification of three-level inverter switching states
X(111) (1,00),(010),(001),
(221),(212),(122)
(210),(120),(021),
(012),(102),(201)
Y(000),(222) (110),(101),(011),
(211),(121),(112)
(200),(220),(020),
(022),(002),(202)
Table 4.6 Switching sequence of A2, A3 and A4 regions
Region (ON-Sequence) (OFF- Sequence)
155
A2 211-210-200-100 100-200-210-211
A3 221-220-210-110 110-210-220-221
A4 211-210-110-100 110-210-211-221
Table 4.7 Switching sequence of three-level inverter in sector-I
Samples States Switching sequence
1 5-17-16-4 211-210-200-100
2 4-16-17-5 100-200-210-211
3 4-16-17-5 100-200-210-211
4 5-17-16-4 211-210-200-100
5 5-17-7-4 211-210-110-100
6 4-7-17-5 100-110-210-211
7 6-18-17-7 221-220-210-110
8 7-17-18-6 110-210-220-221
9 7-17-18-6 110-210-220-221
10 7-17-18-6 110-210-220-221
11 6-18-17-7 221-220-210-110
4.3.2.2 Eleven-level Inverter
The schematic diagram of eleven-level inverter is shown in Fig.
4.43. The dc bus voltage is split into eleven levels by using ten dc
capacitors, C1, C2, C3, C4, C5, C6, C7, C8, C9 and C10. Each capacitor has
Vdc/10 volts and each voltage stress will be limited to one capacitor
level through clamping diodes.
156
The space vector diagram of the eleven-level inverter is divided
into six sextants, and each sextant is divided into one hundred
triangular regions in order to show the vectors nearest to the reference
voltage. The voltage vectors of eleven-level inverter are divided into X
group and Y group, as shown in Table 4.8.
157
Fig. 4.43 Eleven-level NPC inverter topology.
Ta18
Ta17
Ta19
Ta20
Ta12
Ta13
Ta14
Ta15
Ta16
Ta11
Ta8
Ta7
Ta9
Ta10
Ta2
Ta3
Ta4
Ta5
Ta6
Ta1
Tb18
Tb17
Tb19
Tb20
Tb12
Tb13
Tb14
Tb15
Tb16
Tb11
Tb8
Tb7
Tb9
Tb10
Tb2
Tb3
Tb4
Tb5
Tb6
Tb1
Tc18
Tc17
Tc19
Tc20
Tc12
Tc13
Tc14
Tc15
Tc16
Tc11
Tc8
Tc7
Tc9
Tc10
Tc2
Tc3
Tc4
Tc5
Tc6
Tc1
abc
Vdc2
Vdc3
Vdc5
Vdc1
Vdc2
Vdc4
Vdc5
Vdc4
Vdc3
Vdc1
z
P
n
158
The procedure of selecting the voltage vector of X and Y groups
are similar to that of three-level inverter. Table 4.9 shows the
switching ON sequence and OFF sequence for all the regions of
sextant-I of eleven-level inverter.
Fig. 4.44 Sub-sections of eleven-level inverter in sextant-I.
Table 4.8 Classification of eleven-level inverter switching states
X
(9,0,0) (10,2,1) (9,2,0) (10,4,1) (9,4,0) (10,6,1) (9,6,0) (10,8,1) (9,8,0) (10,10,1) (8,9,0) (8,10,1) (6,9,0) (6,10,1) (4,9,0) (4,10,1) (2,9,0) (2,10,1) (0,9,0) (1,10,2) (0,9,2) (1,10,4) (0,9,4) (1,10,6) (0,9,6) (1,10,8) (0,9,8) (1,10,10) (0,8,9) (1,8,10) (0,6,9) (1,6,10) (0,4,9) (1,4,10) (0,2,9 (1,2,10) (0,0,9) (2,1,10) (2,0,9) (4,1,10) (4,0,9) (6,1,10) (6,0,9) (8,1,10) (8,0,9) (10,1,10) (9,0,8) (10,1,8) (9,0,6) (10,1,6) (9,0,4) (10,1,4) (9,0,2) (10,1,2) (10,1,0) (10,3,0) (10,5,0) (10,7,0) (10,9,0) (9,10,0) (7,10,0) (5,10,0) (3,10,0) (1,10,0) (0,10,1) (0,10,3) (0,10,5) (0,10,7) (0,10,9) (0,9,10) (0,7,10) (0,5,10) (0,3,10) (0,1,10) (10,1,0) (3,0,10) (5,0,10) (7,0,10) (9,0,10) (10,0,9) (10,0,7) (10,0,5) (10,0,3) (10,0,1)
Y
(10,1,1) (9,1,0) (10,3,1) (9,3,0) (10,5,1) (9,5,0) (10,7,1) (9,7,0) (10,9,1) (9,9,0) (9,10,1) (7,9,0) (7,10,1) (5,9,0) (5,10,1) (3,9,0) (3,10,1) (1,9,0) (1,10,1) (0,9,1) (1,10,3) (0,9,3) (1,10,5) (0,9,5) (1,10,7) (0,9,7) (1,10,9) (0,9,9) (1,9,10) (0,7,9) (1,7,10) (0,5,9) (1,5,10) (0,3,9) (1,3,10) (0,1,9) (1,1,10) (1,0,9) (3,1,10) (3,0,9) (5,1,10) (5,0,9) (7,1,10) (7,0,9) (9,1,10) (9,0,9) (10,1,9) (9,0,7) (10,1,7) (9,0,5) (10,1,5) (9,0,3) (10,1,3) (9,0,1) (10,0,0) (10,2,0) (10,4,0) (10,6,0) (10,8,0) (10,10,0) (8,10,0) (6,10,0) (4,10,0) (3,10,0) (0,10,0) (0,10,2) (0,10,4) (0,10,6) (0,10,8) (0,10,10) (0,8,10) (0,6,10) (0,4,10) (0,2,10) (0,0,10) (2,0,10) (4,0,10) (6,0,10) (8,0,10) (10,0,10) (10,0,8) (10,0,6) (10,0,4) (10,0,2)
Table 4.9 Switching sequence of eleven-level inverter in sector-I
11.19
10,10,0 Y
11.111.2
11.311.4
11.511.611.7
11.8
11.9
11.1811.1711.16
11.1511.14
11.1311.12
11.1111.10
10,9,0 X
10,8,0 Y
10,7,0 X
10,6,0 Y
10,5,0 X
10,4,0 Y
10,3,0 X
10,2,0 Y
10,1,0 X
10,0,0 Y
X 10,10,1 Y 9,9,0
Y 10,9,1 X 9,8,0
X 10,8,1 Y 9,7,0
Y 10,7,1 X 9,6,0
X 10,6,1 Y 9,5,0
Y 10,5,1 X 9,4,0
X 10,4,1 Y 9,3,0
Y 10,3,1 X 9,2,0
X 10,2,1 Y 9,1,0
Y 10,1,1 X 9,0,0
159
Region ON-Sequence and
OFF-Sequence
11.1 10,1,1 – 10,1,0 – 10,0,0 – 9,0,0
9,0,0 – 10,0,0 – 10,1,0 – 10,1,1
11.2 10,1,1 – 10,1,0 – 9,1,0 – 9,0,0
9,1,0 – 10,1,0 – 10,1,1 – 10,2,1
11.3 10,2,1 – 10,2,0 – 10,1,0 – 9,1,0
9,1,0 – 10,1,0 – 10,2,0 – 10,2,1
11.4 10,2,1 – 10,2,0 – 9,2,0 – 10,2,1
9,2,0 – 10,2,0 – 10,2,1 – 10,3,1
11.5 10,3,1 – 10,3,0 – 10,2,0 – 9,2,0
9,2,0 – 10,2,0 – 10,3,0 – 10,3,1
11.6 10,3,1 – 10,3,0 – 9,3,0 – 9,2,0
9,3,0 – 10,3,0 – 10,3,1 – 10,4,1
11.7 10,4,1 – 10,4,0 – 10,3,0 – 9,3,0
9,3,0 – 10,3,0 – 10,4,0 – 10,4,1
11.8 9,3,0 – 10,4,0 – 10,5,1 – 10,4,1
9,4,0 – 10,4,0 – 10,4,1 – 10,5,1
11.9 9,4,0 – 10,4,0 – 10,5,0 – 10,5,1
10,5,1 – 10,5,0 – 10,4,0 – 9,4,0
11.10 10,5,1 – 10,5,0 – 9,5,0 – 9,4,0
9,5,0 – 10,5,0 – 10,5,0 – 10,6,1
11.11 10,6,1 – 10,6,0 – 10,5,0 – 9,5,0
9,5,0 – 10,5,0 – 10,6,0 – 10,6,1
11.12 10,6,1 – 10,6,0 – 10,7,1 – 9,5,0
9,6,0 – 10,6,0 – 10,6,1 – 10,7,1
11.13 10,7,1 – 10,7,0 – 10,6,0 – 9,6,0
9,6,0 – 10,6,0 – 10,7,0 – 10,7,1
11.14 10,7,1 – 10,7,0 – 9,7,0 – 9,6,0
9,7,0 – 10,7,0 – 10,7,1 – 10,8,1
11.15 10,8,1 – 10,8,0 – 10,7,0 – 9,7,0
9,7,0 – 10,7,0 – 10,8,0 – 10,8,1
11.16 10,8,1 – 10,8,0 – 9,8,0 – 9,7,0
160
9,8,0 – 10,8,0 – 10,8,1 – 10,9,1
11.17 10,9,1 – 10,9,0 – 10,8,0 – 9,8,0
9,8,0 – 10,8,0 – 10,9,0 – 10,9,1
11.18 10,9,1 – 10,9,0 – 9,9,0 – 10,9,1
9,9,0 – 10,9,0 – 10,9,1 – 0,10,1
11.19 10,10,1–10,10,0– 10,9,0 – 9,9,0
9,9,0– 10,9,0– 10,10,0 – 10,10,1
4.3.3 Algorithm for N-Level Inverter
The first step is to identify the triangle in which the reference
voltage vector is located. Then the reference voltage vector is
synthesized from the vectors that present at the vertices of this
triangle and the dwelling times of these vectors can be calculated. The
triangle can be defined a three dimension array
( ) ]1-Nfloor[t 1,2 ×=1λ
( ) ]1-Nfloor[t 2,2 ×=2λ (4.17)
( ) ]1-Nfloor[t 0,2 ×=0λ
Fig. 4.45 Space vector diagram of eleven-level inverter in sector-IThe following conclusions are made from the space vector
900 810 720 630 540 450 360 270 180 090800 710 620 530 440 350 260 170 080
801 711 621 531 441 351 261 171 081701 611 521 431 341 251 161 071
702 612 522 432 342 252 162 072602 512 422 332 242 152 062
603 513 423 333 243 153 063503 413 323 233 143 053
504 414 324 234 144 054404 314 224 134 044
405 315 225 135 045 305 215 125 035
306 216 126 036206 116 026
207 117 027107 017
108 018008
009
161
diagram of eleven-level inverter shown in Fig. 4.45.
• There is only one bit changed between names of adjacent triangles.
• The last bit in each row is the same.
• If λ1 + λ2 + λ0 = N-1, the reference vector is located on vertices of
triangle.
• If λ1+λ2+λ0=N-2, the voltage vectors are in the same direction with
the voltage vectors of two-level inverter triangle.
• If λ1 + λ2 + λ0 = N-3, the triangle has the opposite direction with the
voltage vectors of two-level inverter triangle.
Fig. 4.46 Relation between the voltage vectors of N-level and two-level inverter.
After identifying the triangle in which the reference vector is
located, the nearest three voltage vectors are chosen to compound
reference vector. As shown in Fig. 4.46, according to volt-second
balancing principle, the relation of synthesizing of voltage vector to
reference vector is
sNNNN TVVtVtVt *,3,3,2,211 =++
sNNN Tttt =++ ,3,2,1 (4.18)
That is
V'0 V'
1
V'2
V2
V1
V3
V*
θ
162
=
s
y
x
N
N
N
NyNyNy
NxNxNx
T
TjV
TV
t
t
t
jVjVjV
VVV*
*
,3
,2
,1
,3,2,1
,3,2,1
111
(4.19)
In N-level there is a mapping relation between the three nearest
vector used to synthesize vector and the two non-zero vector of the
two-level, which is
2,212,111 VbVaV +=
2,222,122 VbVaV +=
2,232,133 VbVaV += (4.20)Changing Eq. (4.20) into matrix and put it into (4.19). In complex
plane, we can conclude that
=
s
y
x
N
N
N
yy
xx
T
TjV
TV
t
t
t
bbb
aaa
jVjV
VV*
*
,3
,2
,1
321
321
2,22,1
2,22,1
111100
0
0
(4.21)
From two-level to N-level inverter, the voltage vector transition
matrix is defined
=
111321
32
bbb
aaa
R1
[4.22]
The matrix R is reversible.
=
sN
N
N
T
t
t
t
t
t
bbb
aaa
2,2
2,1
,3
,2
,1
321
321
111
(4.23)
21
2,2
2,1
,3
,2
,1
TR
T
t
t
R
t
t
t
T
s
-1
N
N
N
N−=
=
=
(4.24)
From the solution of these above equations, the dwelling time of
the each vector can be obtained. Thus there is a simple linear
mapping relation between the dwelling time of vectors of the N-level
163
inverter and two-level inverter.
Fig. 4.47 Positive and negative triangles of N-level inverter space vector diagram.
In a triangle, any voltage vector of N-level inverter can be given as
]}111[]110[]100[{1 γβα ++=N
V
Then, the nearest three vectors of positive and negative triangles
have the following relationship.
]}111[]110[]100[{1
121,1 γλλ ++
−=
NV N
]}111[]110[]100)[1{(1
121,2 γλλ +++
−=
NV N
(4.25)
]}111[]110)[1(]100[{1
121,3 γλλ +++
−=
NV N
The direction and length of the voltage in N-level inverter are
represented by the coefficients λ1 and λ2. The parameter γ controls the
redundancy vector. The matrix R is the voltage vector transform
matrix, but the matrix R-1 is the time transition matrix from two-level
to N-level inverter respectively. These positive triangle transition
matrices are given by
−+
−−
−−+
−=
1111
1
11
11
1
1222
111
NNN
NNN
R positiveλλλ
λλλ
V1N
V3N
V2N
V2N
V1N
V3N
164
(4.26)
−−−−
++−−−−=−
2
1
121
)1(0
0)1(
)1()1()1(
λλλλ
N
N
NN
R positive
(4.27)
The negative triangle transition matrices can be obtained from
the following relationship
]}111[]110[]100[{1
121,1 γλλ ++
−=
NV N
]}111[]110)[1(]100)[1{(1
121,2 γλλ +++−
−=
NV N
]}111[]110)[1(]100[{1
121,3 γλλ +++
−=
NV N
(4.28)
−+
−+
−
−−−
−=
1111
1
1
1
1
11
1
1222
111
NNN
NNN
R negative
λλλ
λλλ
(4.29)
+−−−−−
+−−=−
21
1
21
()1()1(
0)1(
)1()1(0
λλλ
λ
NN
N
N
Rnegative
(4.30)
165
Fig. 4.48 Flow chart of N-level inverter.
Thus, the analytical space vector pulse width modulation
algorithm for N-level inverter can be deduced from the two-level.
4.3.4 Results and Discussions
The proposed method is verified by designing a model for N-level
inverter and simulated using MATLAB/Simulation software for three-
level, five-level, seven-level, nine-level and eleven-level inverters. The
simulation parameters and specifications of induction motor used in
this method are given in Appendix-IV. Fig. 4.49 to Fig. 4.54 shows the
results of three-level inverter. The phase voltages, line voltages and its
harmonic spectrum are shown in Fig. 4.49 to Fig. 4.51. The stator
currents, rotor speed and torque responses of three-level inverter fed
induction motor are shown in Fig. 4.52 to Fig. 4.54. Fig. 4.55 to Fig.
4.60 shows the results of five-level inverter. The phase voltages, line
voltages and its harmonic spectrum are shown in Fig. 4.55 to Fig.
4.57. The stator currents, rotor speed and torque responses of five-
Set Modulation index (M)
Calculate t12
, t22
, t02
based on two-level
Determine the voltage parameters λ0, λ
1 and λ
2
Determine the voltage vectors V1N
, V2N
and V3N
for reference voltage vector
Calculate the voltage vector dwell times t1N
, t2N
and
t3N
for reference voltage vector
166
level inverter fed induction motor are shown in Fig. 4.58 to Fig. 4.60.
The seven-level inverter results are shown in Fig. 4.61 to Fig. 4.66.
The phase voltages, line voltages and its harmonic spectrum are
shown in Fig. 4.61 to Fig. 4.63. The stator currents, rotor speed and
torque responses of seven-level inverter fed induction motor are
shown in Fig. 4.64 to Fig. 4.66. The results of nine-level inverter are
shown in Fig. 4.67 to Fig. 4.72. The phase voltages, line voltages and
its harmonic spectrum are shown in Fig. 4.67 to Fig. 4.69. The stator
currents, rotor speed and torque responses of nine-level inverter fed
induction motor are shown in Fig. 4.70 to Fig. 4.72. The results of
eleven-level inverter are shown in Fig. 4.73 to Fig. 4.78. The phase
voltages, line voltages and its harmonic spectrum are shown in Fig.
4.73 to Fig. 4.75. The stator currents, rotor speed and torque
responses of eleven-level inverter fed induction motor are shown in
Fig. 4.76 to Fig. 4.78.
From the harmonic spectrum of three-level, five-level, seven-
level, nine-level and eleven-level inverters is shown in Fig. 4.51, Fig.
4.57, Fig. 4.63, Fig. 4.69 and Fig. 4.75 respectively. From these
figures it is observed that as the inverter level increases the THD
decreases. As the switching timings of multilevel inverters are derived
from a linear transformation between two-level and multilevel inverter,
a significant harmonic component along the fundamental is observed.
The improvement in stator currents of three-level, five-level, seven-
level, nine-level and eleven-level inverter fed induction motor are
observed from the Fig. 4.52, Fig. 4.58, Fig. 4.64, Fig. 4.70 and Fig.
167
4.76 respectively. As the level of inverter increases, the torque ripples
decreases. This can be observed from Fig. 4.54, Fig. 4.60, Fig. 4.66,
Fig. 4.72 and Fig. 4.78 for a three-level, five-level, seven-level, nine-
level and eleven-level inverter fed induction motor.
The speed response, torque ripples and total harmonic
distortion of three-level, five-level, seven-level, nine-level and eleven-
level inverter are shown in Table 4.10. It is observed that as level of
inverter increases THD, torque ripples decreases and speed response
increases. The obtained line voltages and harmonic spectrum of
inverters show the effectiveness of this SVPWM algorithm and it also
shows that as the level of inverter is increasing the line voltage is
nearly standard sine wave. The THD, RMS current and torque ripples
are decreasing as the level of inverter increases. In the simulation
analysis to the more level, it just modifies the level setting number N,
therefore it indicates the algorithm is flexible and transplantable.
4.3.4.1 Three-level Inverter:
168
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-500
-250
0
250
500
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-500
-250
0
250
500
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-500
-250
0
250
500
Time (S)
Pha
se v
olta
ges
Van
, Vbn
. Vcn
(V
)
Fig. 4.49 Phase voltages of three-level inverter.
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-500
0
500 Vab
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-500
0
500
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-500
0
500
Time (S)
Line
vol
tage
s V
ab, V
bc, V
ca (
V)
Fig. 4.50 Line-to-line voltages of three-level inverter.
169
0 200 400 600 800 10000
20
40
60
80
100
Frequency (Hz)
Fundamental (50Hz) = 499.7 , THD= 16.92%
Mag
(%
of F
unda
men
tal)
Fig. 4.51 Output line voltage harmonic spectrum of three-level inverter.
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-60
-40
-20
0
20
40
60
Time (S)
Sta
tor
curr
ents
Ias,
Ibs,
Ics
(A)
Fig. 4.52 Stator currents of three-level inverter fed Induction motor.
170
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-20
0
20
40
60
80
100
120
140
160
Time (S)
Rot
or s
peed
Wm
(ra
d/s)
<Rotor speed (wm)>
Fig. 4.53 Speed response of three-level inverter fed induction motor.
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-20
-10
0
10
20
30
40
50
60
70
80
Time (S)
Tor
que
(N-m
)
Fig. 4.54 Torque response of three-level inverter fed induction motor.
171
4.3.4.2 Five-level Inverter
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-500
-250
0
250
500
Pha
se v
olta
ges
Van
, Vbn
, Vcn
(V
)
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-500
-250
0
250
500
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-500
-250
0
250
500
Time (S)
Pha
se v
olta
ges
Van
, Vbn
, Vcn
(V
)
Fig. 4.55 Phase voltages of five-level inverter.
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-400
-300
-200
-100
0
100
200
300
400
Time (S)
Line
vol
tage
Vab
(V
)
Vab
Fig. 4.56 Line-to-line voltage of five-level inverter.
172
0 200 400 600 800 10000
20
40
60
80
100
Frequency (Hz)
Fundamental (50Hz) = 367 , THD= 4.35%
Mag
(%
of F
unda
men
tal)
Fig. 4.57 Output line voltage harmonic spectrumof five-level inverter.
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-60
-40
-20
0
20
40
60
Time (S)
Sta
tor
curr
ents
Ias,
Ibs,
Ics
(A)
Fig. 4.58 Stator currents of five-level inverter fed Induction motor.
173
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-20
0
20
40
60
80
100
120
140
160
Time (S)
Rot
or s
peed
(ra
d/s)
Fig. 4.59 Speed response of five-level inverterfed induction motor.
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-10
0
10
20
30
40
50
60
70
80
Time (S)
Tor
que
(N-m
)
<Electromagnetic torque Te (N*m)>
Fig. 4.60 Torque response of five-level inverterfed induction motor.
174
4.3.4.3 Seven-level Inverter
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-500
-250
0
250
500
Pha
se v
olta
ges
Van
, Vbn
, Vcn
(V
)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-500
-250
0
250
500
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-500
-250
0
250
500
Time (S)
Fig. 4.61 Phase voltages of seven-level inverter.
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-400
-300
-200
-100
0
100
200
300
400
Time (S)
Line
vol
tage
Vab
(V
)
Vab
Fig. 4.62 Line-to-line voltage of seven-level inverter.
175
0 200 400 600 800 10000
20
40
60
80
100
Frequency (Hz)
Fundamental (50Hz) = 361.7 , THD= 2.45%M
ag (
% o
f Fun
dam
enta
l)
Fig. 4.63 Output line voltage harmonic spectrumof seven-level inverter.
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-60
-40
-20
0
20
40
60
Time (S)
Sta
tor
curr
ents
Ias,
Ibs,
Ics
(A)
Fig. 4.64 Stator currents of seven-level inverterfed Induction motor.
176
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-20
0
20
40
60
80
100
120
140
160
Time (S)
Rot
or s
peed
(ra
d/s)
Fig. 4.65 Speed response of seven-level inverterfed induction motor.
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-10
0
10
20
30
40
50
60
70
80
Time (S)
Tor
que
(N-m
)
Fig. 4.66 Torque response of seven-level inverterfed induction motor.
177
4.3.4.4 Nine-level Inverter
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-400
-200
0
200
400
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-400
-200
0
200
400
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-400
-200
0
200
400
Time (S)
Pha
se v
olta
ges
Van
, Vbn
, Vcn
(V
)
Fig. 4.67 Phase voltages of nine-level inverter.
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-400
-300
-200
-100
0
100
200
300
400
Time
Line
vol
tage
Vab
(V
)
Fig. 4.68 Line-to-line voltage of nine-level inverter.
178
0 200 400 600 800 10000
20
40
60
80
100
Frequency (Hz)
Fundamental (50Hz) = 138.2 , THD= 2.26%M
ag (
% o
f Fun
dam
enta
l)
Fig. 4.69 Output line voltage harmonic spectrumof nine-level inverter.
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-60
-40
-20
0
20
40
60
Time (S)
Sta
tor
curr
ents
Ias,
Ibs,
Ics
(A)
Fig. 4.70 Stator currents of nine-level inverterfed Induction motor.
179
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-20
0
20
40
60
80
100
120
140
160
Time (S)
Rot
or s
peed
(ra
d/s)
Fig. 4.71 Speed response of nine-level inverterfed induction motor.
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-10
0
10
20
30
40
50
60
70
80
Time (S)
Tor
que
(N-m
)
Fig. 4.72 Torque response of nine-level inverterfed induction motor.
180
4.3.4.5 Eleven-level Inverter
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-500
-250
0
250
500P
hase
vol
tage
s V
an, V
bn, V
cn (
V)
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-500
-250
0
250
500
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-500
-250
0
250
500
Time (s)
Fig. 4.73 Phase voltages of eleven-level inverter.
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-500
-250
0
250
500
Line
vol
tage
s V
ab, V
bc, V
ca (
V)
Vab
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-500
-250
0
250
500
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-500
-250
0
250
500
Time (s)
Fig. 4.74 Line-to-line voltages of eleven-level inverter.
181
0 200 400 600 800 10000
20
40
60
80
100
Frequency (Hz)
Fundamental (50Hz) = 116 , THD= 2.13%M
ag (
% o
f Fun
dam
enta
l)
Fig. 4.75 Output line voltage harmonic spectrumof eleven-level inverter.
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-80
-60
-40
-20
0
20
40
60
80
Time (s)
Sta
tor
curr
ents
Ias,
Ibs,
Ics
(A)
Fig. 4.76 Stator currents of eleven-level inverterfed Induction motor.
182
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-20
0
20
40
60
80
100
120
140
160
180
Time (s)
Rot
or s
peed
(ra
d/s)
<Rotor speed (wm)>
Fig. 4.77 Speed response of eleven-level inverterfed induction motor.
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-20
0
20
40
60
80
100
120
Time (s)
Tor
que
(N-m
)
Fig. 4.78 Torque response of eleven-level inverterfed induction motor.
183
Table 4.10 Performance of Multi-level inverters
S. No. Inverter THD% Speed (rpm) Torque ripple%
1 Three-level 16.92 1415 9.2
2 Five-level 4.35 1440 7.8
3 Seven-level 2.45 1445 6.5
4 Nine-level 2.26 1450 4.2
5 Eleven-level 2.13 1453 3.8
4.4 SPACE VECTOR PULSE WIDTH MODULATION FOR MULTI-
LEVEL INVERTER USING DECOMPOSITION METHOD
The space vector pulse width modulation algorithm for
multilevel inverters using decomposition method is proposed. In this
method, the space vector diagram of multilevel inverter is decomposed
in several steps, into the space vector diagrams of two-level inverter. To
proceed with the switching state determination, the first one of the
two-level hexagons is selected based on the location of the target
voltage vector and the original voltage reference vector is decremented
by the voltage vector that locates the origin of the selected two-level
hexagon. This then, allows the determination of switching sequence
and calculation of the switching times as for a conventional two-level
inverter. This method has been explained in detail and results have
been presented and analyzed for three-level inverter, five-level inverter
and seven-level inverters.
184
4.4.1 Seven-level Inverter
Fig. 4.79 shows diagram of a seven-level diode clamping
inverter. Each leg is composed of six upper and lower switches with
anti-parallel diodes. Six series dc link capacitors split the dc bus
voltage in half and thirty six clamping diodes confine the voltages
across the switches within the voltages of the capacitors. The
necessary conditions for the switching states for the seven-level
inverter are that the dc link capacitors should not be shorted, and the
output current should be continuous.
Fig. 4.79 Seven-level NPC inverter topology.
The three dc voltages are labeled as Vdc1, Vdc2, Vdc3 to distinguish
them in the inverter output, although in the most of the cases Vdc1=
P
n
Vdc2
Vdc1
Vdc1
Vdc3
Vdc2
Vdc3
bc
a
Ta1
Ta10
Ta9
Ta11
Ta12
Ta4
Ta5
Ta6
Ta7
Ta8
Ta2
Ta3
Tb1
Tb10
Tb9
Tb11
Tb12
Tb4
Tb5
Tb6
Tb7
Tb8
Tb2
Tb3
Tc1
Tc10
Tc9
Tc11
Tc12
Tc4
Tc5
Tc6
Tc7
Tc8
Tc2
Tc3
z
185
Vdc2= Vdc3. The phase leg switch states required to achieve the seven
output levels can be determined by connecting say phase leg b to the
negative dc bus by triggering all switches in the lower portion of its
phase leg. Then the phase leg a output voltage with respect to the
negative dc rail, Van can be identified for various switch combinations,
as shown in Table 4.11 and Fig. 4.80 shows the space vector diagram
for seven-level inverter.
TABLE 4.11 SWITCHING STATES AND CURRENT PATH FOR SEVEN-LEVEL INVERTER
Switch
statePhase leg ‘a’ voltage Van
Devicestuned ‘ON’
Current pathwith
Ia positive
Current Path with
Ia Negative
1 Van=0 Ta1 to Ta6 Ta6>Ta5>Ta4>Ta3>Ta2>Ta1
Ta6>Ta5>Ta4>Ta3> Ta2> Ta1
2 Van=Vdc3 Ta2 to Ta7 Da7>Ta7 Ta6>Ta5>Ta4>Ta3>Ta2>Da2
3 Van=Vdc3+Vdc2 Ta3 to Ta8 Da8>Ta8>Ta7 Ta6>Ta5>Ta4>Ta3>Da3
4 Van=Vdc3+Vdc2
+Vdc1
Ta4 to Ta9 Da9>Ta9>Ta8
>Ta7
Ta6>Ta5>Ta4>Da4
5 Van=Vdc3+Vdc2
+2Vdc1
Ta5 to Ta10 Da10>Ta10>Ta9
>Ta8>Ta7
Ta6>Ta5>Da5
6 Van=Vdc3+2(Vdc2
+Vdc1)Ta6 to Ta11 Da11>Ta11>Ta10
>Ta9>Ta8>Ta7
Ta6>Da6
7 Van=2(Vdc3+Vdc2
+Vdc1)Ta7 to Ta12 Ta12>Ta11>Ta10
>Ta9>Ta8>Ta7
Ta7>Ta8>Ta9> Ta10>Ta11>Ta12
186
Fig. 4.80 Space vector diagram of seven-level inverter
4.4.2 SVPWM Algorithm using Decomposition Method
4.4.2.1 Basic Principle of Decomposition Method
The space vector diagram of multilevel inverter can be divided
into different forms of sub-diagrams, in such a manner that the
SVPWM becomes more simple and easy to implement. The
decomposition method is a simple and fast one that divides the space
vector diagram of seven-level inverter, within three steps, into several
small hexagons, each hexagon being space vector diagram of two-level
inverter, as shown in Fig. 4.81 to Fig. 4.83. Thus, the space vector
666555444333222111000
655544433322211100
644533422311200
633522411300
622511400
611500
600066
566455344233122011
466355244133022
366255144033
266155044
166055
665554443332221110
654543432321210
643532421310
632521410
621510
610
565454343232121010
465354243132021
365254143032
265154043
165054
065
564453342231120
664553442331220
653542431320
642531420
631520
620
464353242131020
364253142031
264153042
164053
064
563452341230
663552441330
652541430
641530
630463352241130
363252141030
263152041
163052
063
462351240
562451340
662551440
651540
640362251140
262151040
162051
062
461350
561450
661550
650361250
261150
161050
061
060 160 260 360 460 560 660
006 106 206 306 406 506 606
416305
516405
616504
605316205
216105
116005
016
426315204
526415304
626515404
625504
604326215104
226115004
126015
026
536425314203
636525414303
625514403
614503
603436325214103
336225114003
236125014
136025
063
546435323213102
646535424313202
635524413302
624513402
613502
602
446335224113002
346235124013
246135024
146035
046
656545434323212101
645534423312201
634523412301
623512401
612501
601
556445334223112001
456345234123012
356245134023
256145034
156045
056
187
diagram of seven-level inverter becomes very simple and similar to
that of two-level space vector diagram. This simplification of multilevel
space vector diagram into two-level space vector diagram can be done
in two steps. At first, from six hexagons of two-level inverter, one
hexagon has to be selected based on the reference voltage vector
location. Secondly, the origin of reference voltage vector has to be
shifted towards the centre of the selected hexagon.
Fig. 4.81 Decomposition of space vector diagram of seven-level inverter into space vector diagram of four-level inverter.
Fig. 4.82 Decomposition of space vector diagram of four-level inverter into space vector diagram of three-level inverter.
188
Fig. 4.83 Decomposition of space vector diagram of three-level inverter into space vector diagram of two-level inverter.
Fig. 4.84 Division of overlapped regions.
189
4.4.2.2 The First Correction of Reference Voltage Vector
After identifying the location of a given reference voltage vector,
one hexagon has to be selected among the six small hexagons that
contain the seven-level space vector diagram as shown in Fig. 4.81.
But it is observed that some regions of two adjacent hexagons are
overlapped each other. For this reason, the overlapped regions are
equally divided between the two adjacent hexagons as shown in Fig.
4.84. Each hexagon is identified by a number‘s’ as in Table 4.12.
Table 4.12 Selection of hexagon based on reference angle (θ)
Hexagon ‘S’Location of reference voltage vector
phase angle ‘θ’
1-π/6< θ < π/6
2π/6< θ < π/2
3π/2< θ < 5π/6
45π/6< θ < 7π/6
57π/6< θ < 3π/2
63π/2< θ < -π/6
After selection of one hexagon, the translation of the reference
vector V7* has to be done towards the center of this hexagon, as
indicated in Fig. 4.85. This translation has done by subtracting the
center vector of the selected hexagon from the actual reference voltage
vector. Table 4.13 gives the components d and q of the reference
voltage V4* after translation, for all the six hexagons. The index (3) or
(4) or (7) above the components indicate three or four or seven-level
cases respectively.
190
Fig. 4.85 First translation of reference voltage vector
Table 4.13 First correction of reference voltage vector
S *4dV *4
qV
1)0c o s (
2
1 0*7 −dV )0s i n (2
1 0*7 −qV
2)3/c o s (
2
1*7 π−dV )3/s i n (2
1*7 π−qV
3)3/2c o s (
2
1*7 π−dV )3/2s i n (2
1*7 π−dV
4)c o s (
2
1*7 π−dV )s i n (2
1*7 π−dV
5)3/4c o s (
2
1*7 π−dV )3/4s i n (2
1*7 π−dV
6)3/5c o s (
2
1*7 π−dV )3/5s i n (2
1*7 π−dV
4.4.2.3 The Second Correction of Reference Voltage Vector
191
Having the selected four-level inverter diagram and the location
of the translated vector, one hexagon is selected among the six small
hexagons that contains this four-level diagram as shown in Fig. 4.82.
Here also the regions which are overlapped are equally divided
between the two adjacent hexagons. After selection of one hexagon,
translation of the reference vector V4* has done towards the center of
this hexagon, as indicated in Fig. 4.86. This translation has done by
subtracting the center vector of the selected hexagon from the actual
reference voltage vector. Table 4.14 gives the components d and q of
the reference voltage V3* after translation, for all the six hexagons.
Fig. 4.86 Second translation of reference voltage vector
Table 4.14 Second correction of reference voltage vector
S *3dV *3
qV
1)0c o s (
6
1 0*4 −dV )0s i n (6
1 0*4 −qV
2)3/c o s (
6
1*4 π−dV )3/s i n (6
1*4 π−qV
192
3)3/2c o s (
6
1*4 π−dV )3/2s i n (6
1*4 π−qV
4)c o s (
6
1*4 π−dV )s i n (6
1*4 π−qV
5)3/4c o s (
6
1*4 π−dV )3/4s i n (6
1*4 π−qV
6)3/5c o s (
6
1*4 π−dV )3/5s i n (6
1*4 π−qV
4.4.2.4 The Third Correction of Reference Voltage Vector
After selection of three-level inverter diagram and the location of
the translated vector, one hexagon is selected among the six small
hexagons that contain this three-level diagram as shown in Fig. 4.83.
Here also the regions which are overlapped are equally divided
between the two adjacent hexagons. After selection of one hexagon,
the translation of the reference vector V3* has done towards the center
of this hexagon, as indicated in Fig. 4.87. This translation has done by
subtracting the center vector of the selected hexagon from the actual
reference voltage vector. Table 4.15 gives the components d and q of
the reference voltage V2* after translation, for all the six hexagons.
193
Fig. 4.87 Third translation of reference voltage vector
Table 4.15 Third correction of reference voltage vector
S *2dV *2
qV1
)0c o s (6
1 0*3 −dV )0s i n (6
1 0*3 −qV
2)3/c o s (
6
1*3 π−dV )3/s i n (6
1*3 π−qV
3)3/2c o s (
6
1*3 π−dV )3/2s i n (6
1*3 π−qV
4)c o s (
6
1*3 π−dV )s i n (6
1*3 π−qV
5)3/4c o s (
6
1*3 π−dV )3/4s i n (6
1*3 π−qV
6)3/5c o s (
6
1*3 π−dV )3/5s i n (6
1*3 π−qV
4.4.2.5 Determination of Switching Times
Once the corrected reference voltage V2* and the corresponding
hexagon are determined, the switching times can be easily calculated
based on the conventional two-level space vector pulse width
194
modulation method. The only difference between the two-level SVPWM
and the five-level SVPWM is the factor 6 appearing at the first two
equations of five-level inverter as shown in Eq. 4.31. The remaining
necessary procedure for five-level inverter can be implemented like
conventional two-level inverter SVPWM method and two-level
equivalent pulses are obtained.
( )
TTTT
TV
T
TV
T
s
s
s
210
,,,*2
2
,,,*2
1
3s i n
s i n
*6
3s i n
3s i n
*6
−−=
π
θ⋅⋅=
π
θ−π⋅⋅
=
→
→
(4.31)
4.4.2.6 Switching Sequence
This process is implemented by the first considering each four-
level decomposed space vector diagram of seven-level space vector
diagram based on value of ‘s’. Secondly, each four-level space vector
diagram is further decomposed into six three-level space vector
diagrams. Finally, each three-level space vector diagram is further
decomposed into six two-level space vector diagrams and the
switching states of seven-level space vector diagram are changed into
its equivalent two-level switching states. To minimize the total
switching transitions an optimum sequence of these three states is
195
selected, which optimizes the harmonic content of output voltage.
According to the two-level space vector modulation theory, these
switching sequences should be reversed in the next switching interval
for reducing harmonic impact.
4.4.3 Results and Discussions
The space vector pulse width modulation algorithm for
multilevel inverters using decomposition method is proposed. In this
method, the space vector diagram of multilevel inverter is decomposed
into several space vector diagrams of two-level inverters. The validity of
proposed method is verified for three-level, five-level and seven-level
inverters by simulation. The simulation parameters and specifications
of induction motor used in this method are given in Appendix-V. The
results of three-level inverter are shown in Fig. 4.88 to Fig. 4.94. The
pole voltages, phase voltages and line voltages are shown in Fig. 4.88
to Fig. 4.90. The stator currents, rotor speed and torque responses of
three-level inverter fed induction motor are shown in Fig. 4.91 to Fig.
4.93. The output line voltage and its harmonic spectrum of three-level
inverter are shown in Fig. 4.94.
The results of five-level inverter are shown in Fig. 4.95 to Fig.
4.101. The pole voltages, phase voltages and line voltages are shown
in Fig. 4.95 to Fig. 4.97. The stator currents, rotor speed and torque
responses of five-level inverter fed induction motor are shown in Fig.
4.98 to Fig. 4.100. The output line voltage and its harmonic spectrum
of five-level inverter are shown in Fig. 4.101. The results of seven-level
inverter are shown in Fig. 4.102 to Fig. 4.108. The pole voltages,
phase voltages and line voltages are shown in Fig. 4.102 to Fig. 4.104.
196
The stator currents, rotor speed and torque response of seven-level
inverter fed induction motor are shown in Fig. 4.105 to Fig. 4.107.
The output line voltage and its harmonic spectrum of five-level
inverter are shown in Fig. 4.108. The line voltages of three-level, five-
level and seven-level inverters are shown in Fig. 4.90, Fig. 4.97 and
Fig. 104 respectively. These figures show that as the inverter level
increases, the output voltage is near to standard sine wave.
The stator currents of three-level, five-level and seven-level
inverters are shown in Fig. 4.91, Fig. 4.98 and Fig. 105 respectively.
From these figures it is observed that as the inverter level increases
the speed response of induction motor greatly increased. Fig. 4.93,
Fig. 4.100 and Fig. 107 show the output line voltage harmonic
spectrum of three-level, five-level and seven-level inverter. From these
figures it is observed that as level of inverter is increased, the THD
decreases.
The obtained THD for three-level, five-level and seven-level
inverter is 5.93%, 2.79% and 1.51% respectively. This algorithm can
be easily extended to any level of inverter.
4.4.3.1Three-level Inverter
197
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10
200
400
Pol
e vo
ltage
s V
ao, V
bo, V
co (
V)
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10
200
400
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10
200
400
Time (s)
Fig. 4.88 Pole voltages of three-level Inverter.
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-300-200-100
0100200300
Pha
se v
olta
ges
Van
, Vbn
, Vcn
(V
)
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-300-200-100
0100200300
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-300-200-100
0100200300
Time (s)
Fig. 4.89 Phase voltages of three-level inverter.
198
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
-400
-200
0
200
400
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
-400
-200
0
200
400
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
-400
-200
0
200
400
Time (s)
Line
vol
tage
s V
ab, V
bc, V
ca (
V)
Fig. 4.90 Line-to-line voltages of three-level inverter.
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-60
-40
-20
0
20
40
60
Time (s)
Sta
tor
curr
ents
Ia, I
b, Ic
(A
)
Fig. 4.91 Stator currents of three-level inverterfed induction motor.
199
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-200
0
200
400
600
800
1000
1200
1400
1600
Time (s)
Rot
or s
peed
Wm
(rp
m)
Fig. 4.92 Speed response of three-level inverterfed induction motor.
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-20
-10
0
10
20
30
40
50
60
70
80
Time (s)
Tor
que
Te
(N-m
)
Fig. 4.93 Torque response of three-level inverterfed induction motor.
200
0 0.02 0.04 0.06 0.08-500
0
500
Time (s)
FFT window: 5 of 50 cycles of selected signal
0 200 400 600 800 10000
0.5
1
1.5
2
2.5
Frequency (Hz)
Fundamental (50Hz) = 383.8 , THD= 5.93%
Mag
(%
of F
unda
men
tal)
Fig. 4.94 Output line voltage and its harmonic spectrumof three-level inverter.
4.4.3.2 Five-level Inverter
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10
200
400
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10
200
400
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10
200
400
Time (s)
Pol
e vo
ltage
s V
ao, V
bo, V
co (
V)
Fig. 4.95 Pole voltages of five-level Inverter.
201
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-400
-200
0
200
400
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-400
-200
0
200
400
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-400
-200
0
200
400
Time (s)
Pha
se v
olta
ges
Van
, Vbn
, Vcn
(V
)
Fig. 4.96 Phase voltages of five-level inverter.
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
-400
-200
0
200
400
Line
vol
tage
s V
ab, V
bc, V
ca (
V)
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
-400
-200
0
200
400
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
-400
-200
0
200
400
Time (s)
Fig. 4.97 Line-to-line voltages of five-level inverter.
202
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-60
-40
-20
0
20
40
60
Time (s)
Sta
tor
curr
ents
Ia, I
b, Ic
(A
)
Fig. 4.98 Stator currents of five-level inverterfed induction motor.
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-200
0
200
400
600
800
1000
1200
1400
1600
Time (s)
Rot
or s
peed
Wm
(rp
m)
Fig. 4.99 Speed response of five-level inverterfed induction motor.
203
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-10
0
10
20
30
40
50
60
70
80
Time (s)
Tor
que
Te
(N-m
)
Fig. 4.100 Torque response of five-level inverterfed induction motor.
0.5 0.52 0.54 0.56 0.58-400
-200
0
200
400
Time (s)
FFT window: 5 of 50 cycles of selected signal
Line
vol
tage
(V
)
0 200 400 600 800 10000
0.5
1
1.5
2
Frequency (Hz)
Fundamental (50Hz) = 372.6 , THD= 2.79%
Mag
(%
of F
unda
men
tal)
Fig. 4.101 Output line voltage and its harmonic spectrumof five-level inverter.
204
4.4.3.3 Seven-level Inverter
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10
200
400
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10
200
400
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10
200
400
Time (s)
Pol
e vo
ltage
s V
ao, V
bo, V
co (
V)
Fig. 4.102 Pole voltages of seven-level Inverter.
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-400
-200
0
200
400
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-400
-200
0
200
400
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1-400
-200
0
200
400
Time (s)
Pha
se v
olta
ges
Van
, Vbn
, Vcn
(V
)
Fig. 4.103 Phase voltages of seven-level Inverter.
205
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
-400
-200
0
200
400
Line
vol
tage
s V
ab, V
bc, V
ca (
V)
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
-400
-200
0
200
400
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
-400
-200
0
200
400
Time (s)
Fig. 4.104 Line-to-line voltages of seven-level Inverter.
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-60
-40
-20
0
20
40
60
Time (s)
Sta
tor
curr
ents
Ia, I
b, Ic
(A
)
Fig. 4.105 Stator currents of seven-level inverterfed induction motor.
206
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-200
0
200
400
600
800
1000
1200
1400
1600
Time (s)
Rot
or s
peed
Wm
(rp
m)
Fig. 4.106 Speed response of seven-level inverterfed induction motor.
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-10
0
10
20
30
40
50
60
70
Time (s)
Tor
que
Te
(N-m
)
Fig. 4.107 Torque response of seven-level inverterfed induction motor.
207
0 0.02 0.04 0.06 0.08-400
-200
0
200
400
Time (s)
FFT window: 5 of 50 cycles of selected signal
0 200 400 600 800 10000
0.2
0.4
0.6
0.8
Frequency (Hz)
Fundamental (50Hz) = 369.6 , THD= 1.51%
Mag
(%
of F
unda
men
tal)
Fig. 4.108 Output line voltage and its harmonic spectrumof seven-level inverter.
4.5 CONCLUSIONS
In this chapter, the first algorithm, a qualitative space vector
pulse width modulation algorithm has been proposed and described
for three-level, four-level, five-level, six-level and seven-level inverters.
In this proposed scheme, the duty cycles of reference voltage vectors
are corrected to, easily, identify the location of the reference voltage
vector in each region. The appropriate switching sequence of the
region and switching time calculation are also proposed. From the
results, it is observed that the generated voltage spectrum is very
much improved with the increase level of inverter. The total harmonic
distortion (THD) is highly reduced as the level of inverter is increased.
The input current drawn by the induction motor is less distorted as
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level of inverter increases. The output voltage total harmonic
distortion for three-level, four-level, five-level, six-level and seven-level
inverter is 42.48%, 24.99%, 17.05%, 11.57%, 6.71% and 4.67%
respectively. The results have been presented and analysed in this
chapter.
The second algorithm, an analytical space vector pulse width
modulation for multi-level inverter fed induction motor is based on or
two-level inverter is proposed and described in detail. An intrinsic
relationship between multi-level and two-level is developed and by
using a linear transformation, the switching time of vectors for two-
level inverter can be transformed for multi-level inverter. A novel
classification of voltage vectors is proposed to determine switching
sequence. This method can be extended for N-level inverter also. The
results show that the output voltage total harmonic distortion for
three-level, five-level, seven-level, nine-level and eleven-level inverters
is 16.92%, 4.35%, 2.45%, 2.26% and 2.13%. As the level of inverter
increases the THD and the torque ripples are effectively decreased and
the rotor speed is improved.
The third algorithm, space vector pulse width modulation for
multilevel inverter using decomposition method has been proposed
and described for a seven-level inverter. In this method, the space
vector diagram of the multilevel inverter is decomposed into several
space vector diagrams of two-level inverter. After decomposition, all the
remaining necessary procedures for multilevel inverter are done like
conventional two-level inverter. The switching times of voltage vectors
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are calculated at the same manner as two-level inverter. Thus the
proposed method reduces the algorithm complexity and the execution
time. The results are obtained for three-level, five-level and seven level
inverters. The obtained total harmonic distortion (THD) with the
proposed method for three-level, five-level and seven-level is 5.93%,
2.79% and 1.51% respectively. The phase voltage, torque, speed and
current responses are greatly improved.
Thus, the results of these three different space vector based
algorithms for multilevel inverter fed induction motor have been good
agreement with the published work.
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