Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 1 Power Estimation FlexSoc Seminar Series – 2004-03-15 Daniel Eckerbert [email protected]

Chalmers University of Technology

FlexSoC Seminar Series – 2004-03-15 Page 1

Power Estimation

FlexSoc Seminar Series – 2004-03-15

Daniel [email protected]



Outline

• Why power estimation?

• Power macromodeling

• Future directions for power estimation

Most pictures (non-Matlab-plots) are courtesy of Intel Corp.



Why Power Estimation? (Conference-Presentation Answer)

• Heat removal is expensive (fans, heat-sinks)

• Energy stored in battery is limited

• Power delivery is expensive (area, reliability, verification, packaging)



Why Power Estimation?(FlexSoC Answer)

• Compiler optimizations

• “Designing” range of chips for certain applications

• ??? You tell me!



Power Reduction Techniques

• Activity reduction• Supply voltage scaling• Leakage reduction (cut-off techniques, stacking

etc)

But, by how much does the power of a specific design needs to be reduced? And which power mechnism constitutes a problem?



Power Dissipation Basics



From Where Does thePower Increase Stem?



Increased Integration



Increased Integration

120 billion transistorsper wafer!!!

SRAM chips fabricatedon a 300mm wafer



Increased Density



Power Density



Heat Removal (die)



Heat Removal (package)



Power Macro Modeling



Architecture Level Power Macromodeling à la Wattch

• P=0.1*Psw(αmax)+Psw(α,state)



What Do We Want from aPower Estimation Methodology?

• Accurate

• Fast

• Provide information for power reduction



Levels of Power Estimation



Why Use Macro Models?

• Circuit simulations excessively time- and memory-consuming

• Designers need to run long traces to compare solutions (only possible using macro models)



Estimation Tool Run-Times

Run-time HSpice* PowerMill * Macro**

16b Han-Carlson

12d14h 8h49m(30x)

6m43s(2700x / 80x)

8b Multiplier 29d6h 17h37m(40x)

9m42s(4300x / 100x)

32b Multiplier N/A 14d10h 2h2m(N/A / 170x)

* Highly optimized code by team of software designers** Highly unoptimized C++ code by one overworked circuit designer



Precision

• Circuit simulations give full or close to full precision (depending on extraction)

• Macro modeling can give range of precision levels (with a maximum precision determined by methodology)

• Macro model precision is limited by the characterization



Power Estimation Flow

• Characterization– Requires lower level simulations– Has to support maximum precision– One-time only, can afford to be slow

• Estimation– Macro-model only– Can support multiple levels of precision– Frequently run, has to be fast



Characterization



Estimation



Switching Power(Circuit Level)



Switching Power(Early Power Macro Models)



Switching Power(VLSI Research Group Style)

Equation-based 0→1 tracking, even for intermediate nodes depending on accuracy

• Physical model based on nodal capacitances and voltage swings

• Enables semi-automatic characterization



Short-Circuit Power(Circuit Level)



Short-Circuit Power(Macro Model)



Interconnect Modeling



CRC



RLC



Subthreshold-Leakage Power



Subthreshold-Leakage Power(Circuit Level)



Subthreshold-Leakage Power

• Stacking effects

• Long settling times

• …?



Subthreshold-Leakage Power(Macro Model)

• Equation-based model considering on- and off-states of the transistors constituting the gate


• Possible extensions for stacking

• Possible extensions for multiple clock-cycle settling times



Gate-Leakage Power



Oxide Thickness

12 Å



Oxide Thickness



Gate-Leakage Power(Circuit Level)

• Enough equations and theory to use up the entire FlexSoC seminar series



Gate-Leakage Power(Macro Model)

• Equation-based model considering on- and off-states of the transistors constituting the gate


• Complications include leakage paths originating in one gate and ending up in another gate



Separating PowerDissipation Mechanisms



Leakage Power Increase



Active vs. Leakage Power



Separation of Mechanisms(Rise- and Fall-Times)



Separation of Mechanisms(Supply-Voltage Scaling)



Mismatch for Methodologies without a Leakage Component



Mismatch for Methodologies without Leakage or Dynamica Frequency and Supply Scaling



Added Complications



Complex Gates

• Most circuit-level models are only valid for a single transistor or an inverter

• Macromodels have to be able to account for large components, 32b multipliers etc

• Complexity increases super-linearly with the number of transistors in the component



Non-Conforming Components

There are classes of components which do not conform to the presented basic models:

• Clock generators

• Memories

• etc



Clock Generation (DLL)



Clock Generators (Delay Element)



Non-Linear Frequency Dependence for Certain Types of Components



Dynamic Precision

• Different architectures might impose different precision requirements for different components (static during estimation)

• Different operating modes might warrant different need for precision (changes during estimation)



Conclusions

• Power estimation is not simply about averaging the current through the supplies

• Circuit simulation is too slow

• A lot of research is needed to enable high-level power estimation for future designs: some in mechanism modeling but more importantly in the estimation framework



Power estimation is not as easy as it looks

Documents

Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 1 Power Estimation FlexSoc Seminar Series – 2004-03-15 Daniel Eckerbert [email protected]