Challenges of VLSI Patterning and Potential Applications of Atomic Layer EtchingChanro Park, Cathy Labelle, Genevieve Beique, Andre Labonte and Dae Han Choi

SETATECH ALE Workshop

Contents

• Key Elements in Leading Edge VLSI Devices

• Patterning Challenges in VLSI Devices– Common Challenges

– Unit Process (FEOL/MOL/BEOL)

• Candidate Applications of ALET– Gate Etch

– Contact Etch

– Dummy/Sacrificial Layer Removal

– MRAM Free Layer Etch

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Leading Edge VLSI devices

• Key Elements for 14NM / 10NM / 7NM logic technologies– 3D Channel (FINFETs)

– New Channel Materials: SiGe, III-V

– Replacement Gate

– Self Aligned Contact (SAC)

• Multiple Patterning– Sidewall Image Transfer (SIT)

• Mandrel Etch � Spacer Etch � Block mask for cutting

• Pitch Walking (PW)

– LELE, LELELE• Overlay control / Pitch Walking

• LER

• Loading effect

3

Common Etch Challenges for All Level

• CD uniformity

• Etch profile

• Micro loading

• Etch selectivity

• LER/LWR

• Tight defectivity control due to multiple patterning

• Double/triple patterning are mainstream patterning

solutions

4

FIN Etch Challenges• Fin formation by SIT or SIT2

– Fin: smallest feature– Fin pitch: smallest unit

• Pitch walking (a≠b)– FIN CD control by spacer thickness and RIE– PW depends on mandrel CD and spacer thickness– PW may affect intra-cell loading

• Gap fill friendly fin profile– Vertical top and tapered bottom

• Fin cut at tight Fin pitch– PW makes fin cut more challenging– Partially cut fins

• In line process control• Unpredictable device performance

• III-V/SiGe channel– Different channel for n/p FETs– Profile control, especially different channel

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Mandrel Etch �Spacer Etch

Block Planar Devices

Mandrel Pull-outFin Etch

a bFin cut

Fin residue

Gate Etch Challenges• Tight LER/LWR and CD variability control• Minimum pitch walking

– PW affects oxide opening between spacers– SAC contact etch can be very challenging with high PW

• Smaller gate CD poses tremendous challenges to replacement gate module• Gate profile control is critical

– Above the fins: tapered profile makes RMG process very challenging– Under the fins: Gate etch transits from trench to hole patterning– Foot/undercut affect device performance

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FIN

Spacer Etch Challenges

• High etch selectivity– Need high overetch to remove spacer material on Fin sidewall– Fin should not be damaged during spacer etch

• Minimal sidewall spacer loss– Incoming spacer thickness gets thinner as device shrinks– Spacer acts as an etch stop layer during SAC contact etch– Loss of spacer reduces SAC etch margin

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Across Gate Across Fin

SD Recess Etch Challenges• Etching of S/D channel to grow epitaxial layer

– Channel material recess : Si, SiGe, III-V

– Recess depth control

• Selective etching to spacer material and SiO2 ILD– Spacer on FIN sidewall is not completely removed

– Needs selective etching over spacer for confined epitaxial S/D growth,

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Contact Etch Challenges• Multiple patterning to open S/D contacts

– Gate pitch walking and OL affects contact placement w.r.t. gate– Misalignment to gate affect both shorting(gate-S/D) and open(S/D)

• Etch selectivity to SAC cap and spacer is critical– Selectivity is determined by selective polymer deposition on cap and spacer– Corner is the most vulnerable area to erosion– Selectivity is affected by contact overlap to cap/spacer– Oxide opening limits contact size

• Too small opening can cause etch step

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BEOL Etch Challenges

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• (LE)x and SADP• Very tight CDU requirement• Significant LER improvement post RIE regardless of poor LER post litho• Huge CD shrink required with minimum Iso / Dense bias difference• No undercut and bowing profile

• Via top and bottom CD control to improve via-chain TDDB• HM selectivity for SAV via etch for improved short margin• CD uniformity improvement for yield and reliability • No hard mask undercut for reliable metallization• Minimum dielectric damage • Wiggling due to resist stack or metal hard mask stress elimination before metallization

Hard Mask Patterning

Dielectric Etch

Patterning Approach Evolution thru Technology Node

• Technology shrinkage pushes patterning approaches in new directions– VFTL � TFHM: top CD control, SAV capability, easier to double/multi

pattern– LE � LLE � LELE � (LE)x: litho reached limit of existing tool capability,

EUV not ready at the time� need multi-patterning approaches• Evolved from double litho/single etch (LLE) to full litho-etch-litho-etch (LELE)

schemes and more– (LE)x vs. sidewall image transfer (SIT) may be chosen for different BEOL levels based on

design or process control needs (SIT better for alignment, (LE)x better for complex designs)

– EUV implementation now a visible reality � being targeted at 7nm & beyond nodes• Realizes some process simplification, but brings its own challenges

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Technology node 32nm 28nm 22/20nm 14nm 10nm

Minimum pitch (nm) 100 90 < 90 < 80 < 64

Lithography 193i 193i 193i 193i 193i EUV 193i

Trench patterning LE LE LLE/LELE LELE/(LE)x/SIT LELELE/SIT LE (LE)

x/SIT

2

Via patterning LE LE LE/LELE LELE/(LE)x

LELE/(LE)x

LE (LE)x

Patterning approach VFTL TFHM TFHM TFHM TFHM

Self-aligned via (SAV) Non-SAV Non-SAV SAV SAV SAV

7nm

< 50

TFHM

SAV

BEOL Patterning: a 2-tiered adventure• In a time (not so) long ago....BEOL patterning was relatively straight-forward �

print litho, etch film of interest

• Today’s world:– Assemble/print pattern

– Transfer into film of interest

• Both steps take equivalent process development effort

• EUV reduces the number of passes for step 1, but not necessarily the complexity (EUV resist � HM is the first challenge)

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TFHM Dielectric Etch

Via etch + strip Final Trench/Via Etch

(LE)x Via Pattern

Form at-pitch via pattern in HM2 above trench HM

HM2

(LE)x/SIT/SIT2 Trench Pattern

Form at-pitch trench pattern in HM

+

Multi-Patterning Approaches• Several approaches possible for trench pitch split multi-patterning

– Due to ILD material modification sensitivity, the at-pitch pattern has to be formed above the ILD

• Several approaches possible for via multi-patterning, but generally an (LE)x scheme used– To enable self-aligned vias, the complete via pattern must be formed

*above* the trench pattern in the HM and then translated down all at once

• Two major patterning schemes for trenches:

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Form at-pitch pattern in HM

(LE)x

Sidewall Image Transfer (SIT)

Atomic Layer Etching

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� ALET may be applicable to etch processes requiring– High etch selectivity

• Negligible gouging into underlayer

– Low etch damage• Alternative to wet process• No impact on device characteristics

– Etch thin layer• Slow etch rate of ALET impacts throughput

� Potential Application– Gate Etch– Contact Etch– Dummy/Sacrificial Layer Removal– MRAM Magnetic Stack Etch

Gate Etch• Gate First Metal Last device

– Dummy gate etch stopping on a metal gate– Dummy gate patterning with conventional etching– Metal gate is a sacrificial layer

• Selective etching– Selective metal gate etch to HK & Selective HK etch to IL– No footing/ undercutting

• No plasma induced damage to gate stack– Charging damage– Oxidation of exposed edge

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FIN

Dummy gate

Metal Gate / High-k dielectric

Hard Mask

Dummy/Sacrificial Layer Removal• Removal of dummy gate

– Two step Etch• Main etch stop on fin with conventional plasma followed by final touch-up with ALET• High etch selectivity to spacer• High etch selectivity to SiO2

– Fin top is exposed to plasma

– No physical/electrical damage to SiO2, which will be used as gate dielectric of I/O devices

• Removal of annealing cap layer– HK PDA/Spike annealing needs cap layer– A thin metallic diffusion barrier under the cap layer – Incomplete removal of cap : Vt control issue

• Wet removal of the cap layer is challenging in small features

– Two-step etch is not possible: A thin cap layer does not fill LC device– No diffusion of etch chemistry into HK dielectric

Dummy/sacrificial layer

Contact Etch• Minimum gouging into S/D Epi

– Wide contact area for low contact resistance

• Two-step contact etch– Main etch stops on thin Etch Stop Layer with SAC process

– Conventional ESL break through erodes too much cap/spacer � can cause gate-S/D shorting

– ALET for selective removal of ESL with limited cap/spacer erosion

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Across Fin Across Gate

ESL

FIN

Epi

MRAM Free Layer Etch• Top contact layer etch with RIE stopping on free layer

• Selective etching of free layer to barrier layer– Punch through of tunneling barrier

• Re-deposition of sputtered reference metal layer � A shorting path across tunneling barrier

– ALET to etch thin free layer(CoFeB)– ALET should stop on very thin (~1nm) MgO tunneling barrier

• No plasma damage to free, barrier and reference layer– Plasma damage can reduce MR ratio (ON/OFF signal ratio)– Corrosion magnetic layer– Further oxidation of MgO / oxidation of magnetic layer

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Summary

• Ever shrinking VLSI devices require very tight process control – Dimensional uniformity across feature size, pitch and macro

– 3D device structure & smaller device dimension add process complexity

– Unit process specific challenges

• ALET applications to logic and memory devices– ALET needs to improve throughput to be a main stream production tool

– Special applications to etch thin layers with a very high etch selectivity and low etch damage

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