Ch11_2

7/28/2019 Ch11_2

1/23

Backend - Chapter 11

Text Book:

Fundamentals, Practice and Modeling. . , . . ,and P. B. Griffin

SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin

2000 by Prentice HallUpper Saddle River NJ

7/28/2019 Ch11_2

2/23


Frontend vs. Backend

Backend

Frontend



2

7/28/2019 Ch11_2

3/23


Backend Technology

Backend technology: fabrication of interconnectsand the dielectrics that electrically isolate them.

Early structures were simple by today's standards.Oxide

Aluminum

N+Oxide

con

More metal interconnect levelsu u y

and speed.

Interconnects are separated intolocal interconnects (polysilicon,silicides, TiN) and intermediate-global interconnects (Cu or Al).

Backend processing is

. Larger fraction of total structureand processing.

Starting to dominate total speed



3(From ITRS)

of circuit.

7/28/2019 Ch11_2

4/23


Interconnection Considerations

Wire lengths Intra-cell routing

TI Presentations Slides:Impact of (Metal) Interconnect Scaling and ProcessVariation on Performance, Mayur Joshi, Nagaraj NS,Anthony Hill, Texas Instruments

n e -ce rou ng Local intra-block routing Global inter-block routing, clock, power

. . .

S gn cant Concerns Wire resistance

Wire capacitance Signal skew (interconnect variation) Wire delays vs. gate delays (wire beginning to dominate)

Inherent Considerations Planarization Vias vs. lines Local interconnect



Connection to gates

4

7/28/2019 Ch11_2

5/23


Chemical-Mechanical PolishingWafer carrier

WaferPolishing pad

Polishing table

Slurry(facing down)

The most common solut ion for planarization today is CMP, which

Close-up of wafer/pad interface:

Silicon

.

It is capable of forming very flatsurfaces as shown in the example.

Polishing pad(semi-rigid)

Oxideslurry

Deposit thick oxide

Plasma etchback CMP



5Locally planarized topography remains Globally planarized topography remains

7/28/2019 Ch11_2

6/23


Backend Structure SchematicWith PECVD oxide/PECVD nitride passivation bilayer

on top of final metal level

PECVD SiO 2

Metal 2

W PECVD SiO 2PECVD SiO 2

SOG or SOD

Metal 1

Field Oxide

W CVD SiO2

BPSGCVD SiO 2

+

Silicon

- .

Other variations include HDP oxide or the use of CMP.



6

7/28/2019 Ch11_2

7/23


Backend Structure SEM

Two backend structures. o Left: three metal levels and encapsulated BPSG for the first level

dielectric; SOG (encapsulated top and bottom with PECVD oxide) andCMP in the intermetal dielectrics. The mult ilayer metal layers and W

p ugs are a so c ear y seen.o Right: five metal levels, HDP oxide (with PECVD oxide on top) and CMPin the intermetal dielectr ics.



7

7/28/2019 Ch11_2

8/23


Measurement Methods

Resistance and Resistivity Metals and silicides

H s

=W H

L R

=

= W

L R s

Contact Res stance Cross-bridge Kelvin Probed Structure

Multiple contacts in series

W L R c

c

=

2211Rm Rm Rn R

cTotal++=



8

7/28/2019 Ch11_2

9/23


Electrical Measurements of ContactsLow resistance

SiliconS

ct

l

=

Representative of a

resistance computation

R cc

=

KELVIN BRIDGE

t

g vesoverestimation( R C ) of thecontact properties



9

7/28/2019 Ch11_2

10/23


Models and Simulation

Backend process simulation obviously relies heavily on the deposition andetching simulation tools discussed in Chapters 9 and 10.

Thin Film Deposition and Etching are key to processing. , an prev ous y ment one are a use

o Silicide Formation

o Chemical Mechanical Polishing

o Reflow

o Grain Growth

o Electromigration



10

7/28/2019 Ch11_2

11/23


Titanium Silicide Formationnewly

Ti

TiSi 2

Si + Ti TiSi 2 Ti

TiSi 2

Si + Ti TiSi 2

TiNN+ Ti TiN

a) b)

Si or Ndiffusion

through the

Silicon

Si

Silicon

Si

Silicide formation is often modelin usin the Deal-Grove linear-

material

parabolic model. Titanium Silicide growth based on a selective salicide formation.

1 nm of TI consumes 2.27 nm of Si producing 2.51 nm of TiSi 2

/

2

+=+ t A B

x

B

xss

++= 1

4/1

2 2 B At A

xs



11

7/28/2019 Ch11_2

12/23


Alternate Silicide FormationsCoSi 2Model

TiSi 2Model

Concern shorting of source-gate or gate-drain One solution: simultaneously grow TiN during the anneal

TiN is may also be used as a local interconnect if not removed TiN is also a diffusion barrier for most dopants



12

7/28/2019 Ch11_2

13/23


From Dr. Saraswat



13

7/28/2019 Ch11_2

14/23


Titanium Silicide Modeling Simulation of TiSi 2 formation using FLOOPS [11.32] on a 0.35 m wide

gate structure. Left: before formation anneal step. Right: after formationanneal step: 30 sec at 650

C in a nitrogen atmosphere

-0.4

-0.2

Titanium

Oxidespacer

TitaniumTitanium silicide

Titaniumnitride

Pinning point

-0.4

-0.2

0

0.2 i n m

i c r o n s

SiliconSilicondioxide i n

m i c r o n s

SiliconTitaniumsilicide Silicondioxide

0

0.2

-0.8 -0.4 0.0 0.4 0.8y in microns

0.4

x

-0.8 -0.4 0.0 0.4 0.8y in microns

0.4

Titanium Deposition After Anneal in NitrogenTiSi 2 forms over silicon and polysilicon, not over SiO 2.



14

7/28/2019 Ch11_2

15/23


Salicide: Table 11-5 p. 700



15

7/28/2019 Ch11_2

16/23


Chemical Mechanical Polishing mo e s ave a so een ncorpora e n process s mu a ors. Models for CMP attempt to determine the relative pressure at each point

and then calculate the relative removal rate at each point assuming that itis linearl ro ortional to the local ressure see text .

ATHENA simulation of

1

n s

a) b) c)chemical-mechanicalpolishing of SiO 2 over Al

lines:0

0 20microns

m i c r

0 20microns 0 20microns

.b. after 3 minutes of

polishing;c. after 6 minutes of

po s ng



16

7/28/2019 Ch11_2

17/23


Chemical Mechanical Polishing

0

.

m i c r o n s

SiO 2 W

0

.SiO

2W

0 10microns 0 10microns

ATHENA simulation of chemical-mechanical polishing of a tungsten viastructure:

o Left: before polishing;.

Due to the faster polishing of tungsten compared to silicon dioxide andthe semi-rigid pad, dishing of the tungsten plug can result.



17

7/28/2019 Ch11_2

18/23


Reflow

Reflow occurs to minimize the total energy of the system. In this case, thesurface energy of the structure is reduced by minimizing the curvature.

ur ace us on s one re ow mec an sm meta s at g .

Atoms will move to regions of lower chemical potential, , which is a functionof the curvature.

where is the per-area surface energy, is the atomic volume of the atom,

s

K

sForce

s

==

s s e curva ure, an s s e eng a ong e sur ace.

The curvature, K, is equal to the inverse of the radius of curvature, R, at thatpoint:

The force acting upon an atom is in the direction away from a point of higher

RK =



18

.results.

7/28/2019 Ch11_2

19/23


Reflow (2)R 1 Force

1

2R 2

The surface flux of atoms, F s then equals:

2

2 K DF

ss

s

=

where is the number of atoms per unit area, andDs is the surface diffusivity of the atoms.

initial profile15 min., 800K30 min.60 min.

2.0

1.5

1.0

0.5 t ( m i c r o n s )

(a) initial profile3 min., 800K9 min.18 min.

2.0

1.5

1.0

0.5 t ( m i c r o n s )

(b) Simulations of R. Brain, for reflow

of Cu at 800K for different t renchsizes:

0.0

-0.5

-1.03 4 5 6 7

Width (microns)

H e i g 0.0

-0.5

-1.03 4 5 6 7

Width (microns)

H e i g

o a. 1 x 1 m;o b. 0.5 x 1 m;o c. 0.33 x 1 m; and

initial profile2 min., 800K4 min.8 min.

2.0

1.5

1.0

0.5 h t ( m i c r o n s )

(c) initial profile3 min., 800K12 min.18 min.24 min.

3.0

2.0

1.0 t ( m i c r o n s )

(d)

. .spaced 0.5 m apart .

(parameters given in Table 11.8, p.751, in text.)



19

.

-0.5

-1.03 4 5 6 7

Width (microns)

H e i g 0.0

-1.0

2 4 6 8Width (microns)

H e i g Note filling of trenches and

smoothing of topography.

7/28/2019 Ch11_2

20/23


Grain Growth

All materials used for interconnectionsare polycrystalline. That is, they aremade u of re ions of sin le cr stal material where atoms are lined upperfectly that contact irregularly atcrystal grain boundaries.

Grain boundaries may havesignificantly different properties than

the grains. (traps, density, etc.),grows.

Grain growth is similar to reflow.

boundaries, with growth occurringwhere another grain is losing material.



20

7/28/2019 Ch11_2

21/23


Grain Growth Simulations

Normal grain growth with time. Based Grain growth within a strip in time.

on wor y ros an co eagues re erencein the text.

In stead state avera e rain size

The limit to grain growth is related to thestructure. For polycrystalline films growth

roceeds until the avera e rain diameter is



21

determined by sqrt(t). approximately 2 to 3 times the film

thickness.

7/28/2019 Ch11_2

22/23


The Future of Backend Technology 2

1+

1

L = . = . I ox o Hx ox + WL S emem er:

Year of Production 1998 2000 2002 2004 2007 2010 2013 2016 2018

MPU Printed Gate Leng th 100 nm 70 nm 53 nm 35 nm 25 nm 18 nm 13 nm 10 nmMin Meta l 1 Pitch (nm) 214 152 108 76 54 42

-

Me tal 1 Aspect Ratio (Cu) 1.7 1.7 1.8 1.9 2.0 2.0

Contact As pec t Ratio (DRAM) 15 16 >20 >20 >20 >20

renc s pec a o . . . . .

Me tal Res istivi ty (ohm-cm) 3.3, 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2

Interlevel Dielectric Constant 3.9 3.7 3.7

7/28/2019 Ch11_2

23/23


Summary of Key Ideas

Backend processing (interconnects and dielectrics) have taken on increasedimportance in recent years.

Interconnect dela s now contribute a si nificant com onent to overall circuit performance in many applications.

Early backend structures utilized simple aluminum to silicon contacts.

e a y ssues, e nee or many eve s o n erconnec an p anar za onissues have led to much more complex structures today involving multilayermetals and dielectrics.

s e mos common panarza on ec nque o ay.

Copper and low-K dielectrics are now found in some advanced chips and theiruse will likely be common in the future.

Beyond these materials changes, interconnect options in the future includearchitectural (design) approaches to minimizing wire lengths, opticalinterconnects, electrical repeaters and RF broadcasting. All of these areas will



see s gn can researc n e nex ew years.

23

Documents

Ch11_2