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Chapter 11

CONCLUSIONS

In this book, design and integration issues of broadband VCO and PLLfrequency synthesizer in CMOS technology are investigated. A fully integratedradio solution requires concurrent design ofthe transceiver and synthesizer withparticular attention paid to frequency planning in order to ease implementation.The full integration of a broadband VCO requires attention at the transceiverarchitecture and frequency planning, synthesizer architecture, and technologyaspects. Summary. of conclusions and contributions exploring the above issuesare listed as follows:

An analytical model is developed to investigate the noise properties ofclosed-loop PLL. The closed-loop PLL noise is an important factor of the total system performance in modem digital communications which use phase

modulation, such as QPSK and QAM. The PLL noise model includes noisecontributions from the blocks forming a PLL as well as the VCO. A SPICEimplementation of the model is also compared with measured results. Themodels allow optimization of closed-loop PLL noise.

Broadband VCO design issues are explored. As an individual block, VCOspecifications include phase noise, tuning range and power consumption.However, full integration of a VCO in a transceiver also demands manu

facturability (robust design against process variation, temperature and supplylbias variations) and tolerance to integrated environment disturbances(substrate coupled noise, cross talk between signal lines, and supply linebounces). Active circuit design for negative resistance generation is explored for broadband operation. The resonator design is also presented.

An application of broadband PLL frequency synthesizers is designed and implemented for a muW-band/standard (IEEE 802.11a1b/g)WLAN frequency

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synthesizer in O.18j1m CMOS. Phase noise trade-offs for PLL noise specifications are explored in this application. A loop filter architecture suitedfor integrated environments is also developed. VCO interface betweenprescaler and mixers require particular attention for isolation considerations. A quadrature signal generation architecture is also developed. Thequadrature signal is generated by driving PPF with the VCO directly. Dualmodulus prescaler design and integration issues are investigated.

Design and development of 4GHz VCO in CMOS technology for use inWLAN frequency synthesizer is presented. PMOS and complementaryCMOS active circuit topologies are evaluated for integration considerations.PMOS active circuit topology exhibits better performance with accumulation mode varactor.

An auto calibration circuit for VCO tuning band selection is developed andimplemented. The auto calibration circuit eases the tuning range issue forbroadband operation.

A fully integrated dual-mode frequency synthesizer for GSM and WCDMAstandards is developed as another application. A dual-band VCO is designedto support the required frequency channels. This example explores hardwaresharing in PLL components by using integer-N/frac-tional-N architecturesfor dual-band/standard operation.

RF CMOS characterization issues are investigated. Microwave wafer measurement and pad de-embedding techniques are developed. CMOS technologies are evaluated for RP design.

Other issues which require further study in the design and implementationof fully integrated RP PLL frequency synthesizer in sub-micron CMOS technologies include:

Amplitude control architecture and circuit techniques for broadband VCOsare needed. VCO output amplitude varies over the tuning range due to

change of the resonator Q. Also, inductor metal sheet resistance varies dueto temperature and process variations. This results in variation of the Q forthe resonator since the loaded resonator Q is determined primarily by theinductor Q.

Flicker noise of the MOS devices under large signal condition require furtherresearch and understanding for better VCO noise prediction.

Fractional-N architectures for multi-standard operations should be investigated.

Further investigation of RP CMOS modeling issues at 10GHz and beyondis needed.