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4-1 Chapter 4 - The Instruction Set Architecture

Computer Architecture and Organizationby M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

Computer Architecture and

OrganizationMiles Murdocca and Vincent Heuring

Chapter 4 The

Instruction Set

Architecture

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Chapter Contents

4.1 Hardware Components of the Instruction Set Architecture

4.2 ARC, A RISC Computer

4.3 Pseudo-Operations

4.4 Synthetic Instructions

4.5 Examples of Assembly Language Programs

4.6 Accessing Data in MemoryAddressing Modes

4.7 Subroutine Linkage and Stacks

4.8 Input and Output in Assembly Language

4.9 Case Study: The Java Virtual Machine ISA

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The Instruction Set Architecture

The Instruction Set Architecture(ISA) view of a machinecorresponds to the machine and assembly language levels.

A compilertranslates a high level language, which is architecture

independent, into assembly language, which is architecture

dependent.

An assemblertranslates assembly language programs into

executable binary codes.

For fully compiled languages like C and Fortran, the binary codes

are executed directly by the target machine. Java stops thetranslation at the byte code level. The Java virtual machine, which

is at the assembly language level, interprets the byte codes

(hardware implementations of the JVM also exist, in which Java

byte codes are executed directly.)

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The System Bus Model of a ComputerSystem, Revisited

A compiled program is copied from a hard disk to the memory. The

CPU reads instructions and data from the memory, executes the

instructions, and stores the results back into the memory.

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Common Data Type Sizes

A byte is composed of 8 bits. Two nibbles make up a byte.

Halfwords, words, doublewords, and quadwords are composed of bytes

as shown below:

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Big-Endian and Little-Endian Formats In a byte-addressable machine, the smallest datum that can be

referenced in memory is the byte. Multi-byte words are stored as asequence of bytes, in which the address of the multi-byte word is the

same as the byte of the word that has the lowest address.

When multi-byte words are used, two choices for the order in which

the bytes are stored in memory are: most significant byte at lowestaddress, referred to as big-endian, or least significant byte stored at

lowest address, referred to as little-endian.

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Memory Map for the ARC

Memory

locations are

arranged linearly

in consecutive

order. Each

numberedlocation

corresponds to

an ARC word.

The unique

number thatidentifies each

word is referred

to as its

address.

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Example of ARC Memory Layout The table illustrates both the distinction between an address and the

data that is stored there, and the fact that ARC/SPARC is a big-endianmachine. The table shows four bytes stored at consecutive addresses

00001000 to 00001003.

Thus the byte address 0x00001003 contains the byte 0xDD. Since this

is a big-endian machine (the big end is stored at the lowest address)

the word stored at address 0x00001000 is 0xAABBCCDD.

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Abstract View of a CPU

The CPU consists of a data section containing registers and an ALU,

and a control section, which interprets instructions and effects registertransfers. The data section is also known as the datapath.

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The Fetch-Execute Cycle

The steps that the control unit carries out in executing a program are:

(1) Fetch the next instruction to be executed from memory.

(2) Decode the opcode.

(3) Read operand(s) from main memory, if any.

(4) Execute the instruction and store results, if any.

(5) Go to step 1.

This is known as the fetch-execute cycle.

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An Example Datapath

The ARC datapath is made up of a collection of registers known as the

register fileand the arithmetic and logic unit(ALU).

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ARC User-Visible Registers

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ARC Assembly Language Format

The ARC assembly language format is the same as the SPARCassembly language format.

This example shows the assembly language format for ARC (and

SPARC) arithmetic and logic instructions.

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ARC Load / Store Format

This example shows the assembly language format for ARC load andstore instructions.

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Simple Example: Add Two Numbers

The figure shows a simple program fragment using our ld, st, and add

instructions. This fragment is equivalent to the C statement:

z = x + y;

Since ARC is a load-store machine, the code must first fetch the x and

y operands from memory using ld instructions, and then perform the

addition, and then store the result back into z using an st instruction.

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ARC Transfer of Control Sequence

This example shows the assembly language format for ARC branchinstructions.

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ARC Fragment that Computes theAbsolute Value

As an example of using the ARC instruction types we have seen so

far, consider the absolute value function, abs:

abs(x) := if (x < 0) then x = -x;

An ARC fragment to implement this is shown below:

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A Portion of the ARC ISA The ARC ISA is a subset of the SPARC ISA. A portion of the ARC ISA

is shown here.

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ARC Instruction and PSR Formats

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ARC DataFormats

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ARC Pseudo-Ops

Pseudo-ops are instructions to the assembler. They are not part of the

ISA, but instruct the assembler to do an operation at assembly time.

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Synthetic Instructions Many assemblers will accept synthetic instructions that are converted to

actual machine-language instructions during assembly. The figurebelow shows some commonly used synthetic instructions.

Synthetic instructions are single instructions that replace single

instructions, which are different from macros which are discussed later.

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ARC Example Program

An ARC assembly language program adds two integers:

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A MoreComplexExampleProgram

An ARC program

sums five integers.

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One, Two, Three-Address Machines Consider how the C expression A = B*C + D might be evaluated by each

of the one, two, and three-address instruction types. Assumptions: Addresses and data words are two bytes in size. Opcodes

are 1 byte in size. Operands are moved to and from memory one word

(two bytes) at a time.

Three-Address Instructions: In a three-address instruction, theexpression A = B*C + D might be coded as:

mult B, C, A

add D, A, A

which means multiply B by C and store the result at A. (The mult and

add operations are generic; they are not ARC instructions.) Then, add D

to A and store the result at address A. The program size is 72 = 14

bytes. Memory traffic is 14 + 2(23) = 26 bytes.

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One, Two, Three-Address Machines

Two Address Instructions: In a two-address instruction, one of the

operands is overwritten by the result. Here, the code for the expressionA = B*C + D is:

load B, A

mult C, A

add D, A

The program size is now 3(1+22) or 15 bytes. Memory traffic is 15 +

22 + 223 or 31 bytes.

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One, Two, Three-Address Machines One Address (Accumulator) Instructions: A one-address instruction

employs a single arithmetic register in the CPU, known as theaccumulator. The code for the expression A = B*C + D is now:

load B

mult C

add D

store A

The load instruction loads B into the accumulator, mult multiplies C by the

accumulator and stores the result in the accumulator, and add does thecorresponding addition. The store instruction stores the accumulator in

A. The program size is now 34 or 12 bytes, and memory traffic is 12 +

42 or 20 bytes.

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Addressing Modes

Four ways of computing the address of a value in memory: (1) a constant

value known at assembly time, (2) the contents of a register, (3) the sum

of two registers, (4) the sum of a register and a constant. The table gives

names to these and other addressing modes.

C S

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Subroutine Linkage Registers

Subroutine linkage with registers passes parameters in registers.

Ch 4 Th I i S A hi

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Subroutine Linkage Data Link Area Subroutine linkage with a data link area passes parameters in a

separate area in memory. The address of the memory area is passedin a register (%r5 here).

4 31 Ch t 4 Th I t ti S t A hit t

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Subroutine Linkage Stack Subroutine linkage with a stack passes parameters on a stack.

4 32 Ch t 4 Th I t ti S t A hit t

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StackLinkageExample

A C program

illustrates nested

function calls.

4 33 Chapter 4 The Instruction Set Architecture

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Stack

LinkageExample(cont)

(a-f) Stack

behavior during

execution of theprogram shown in

previous slide.


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Stack

LinkageExample(cont)

(g-k) Stack behavior

during execution of

the C programshown previously.


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Input and

Output forthe ISA

Memory map forthe ARC, showing

memory mapped

I/O.

4 36 Chapter 4 - The Instruction Set Architecture

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Touchscreen I/O Device

A user selecting an object on a touchscreen:

4 37 Chapter 4 - The Instruction Set Architecture

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Flowchart for I/ODevice

Flowchart illustrating the control

structure of a program that tracks

a touchscreen.


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Java Virtual Machine Architecture


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4-39 Chapter 4 The Instruction Set Architecture


JavaPro-gramand

Com-piledClass

File


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A Java Class File


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A Java Class File (Cont)


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4 42 C apte e st uct o Set c tectu e

Byte Code for Java Program Disassembled byte code for previous Java program.

Location Code Mnemonic Meaning0x00e3 0x10 bipush Push next byte onto stack

0x00e4 0x0f 15 Argument to bipush

0x00e5 0x3c istore_1 Pop stack to local variable 1

0x00e6 0x10 bipush Push next byte onto stack

0x00e7 0x09 9 Argument to bipush

0x00e8 0x3d istore_2 Pop stack to local variable 2

0x00e9 0x03 iconst_0 Push 0 onto stack

0x00ea 0x3e istore_3 Pop stack to local variable 3

0x00eb 0x1b iload_1 Push local variable 1 onto stack0x00ec 0x1c iload_2 Push local variable 2 onto stack

0x00ed 0x60 iadd Add top two stack elements

0x00ee 0x3e istore_3 Pop stack to local variable 3

0x00ef 0xb1 return Return

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