Ch02

CMOS Technology- Chapter 2

Text Book:Silicon VLSI Technology

Fundamentals, Practice and Modelingg

Authors: J. D. Plummer, M. D. Deal, and P. B. Griffina d G

SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin

© 2000 by Prentice HallUpper Saddle River NJ


CMOS TECHNOLOGY• We will describe a modern CMOS process flow.

• Typical CMOS technologies in manufacturing today add additional steps to implement multiple device VTH, TFT devices for loads in SRAMs, capacitors for DRAMs etc.

• Process described here requires 16 masks and > 100 process steps.

• There are many possible variations on the process flow described here, some of which are described in Chapter 2 pin the text. e.g. see the STI section in the text.



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CMOS Digital Gates• In the simplest CMOS technologies, we need to

realize simply NMOS and PMOS transistors for circuits like those illustrated below.

+ V+ V

PMOS

IN1

IN2

INPUT

OUTPUTOUTPUT

NMOS

GNDGND



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GND

Inverter 2-input NOR


2-Level Metal CMOS

G

D

S S

D

GSub Sub

S G D S G D

S S

PMOS and NMOS wafer cross section after fabrication

PNP+ P+ N+ N+

fabrication

P Well - NMOS SubstrateN Well - PMOS Substrate



4P

PMOS NMOS


Processing Phases• Choosing a Substrate• Active Regiong• N and P Well• Gate• Tip or Extension• Source and Drain

C t t d L l I t t• Contact and Local Interconnect• Multilevel Metalization



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Choosing a Substrate

SiO2

Si3N4

Photoresist

40 nm

1 µm80 nm

Choose the substrate (type, orientation, resistivity, wafer size)

240 nm

Si, (100), P Type, 5-50 žcm

• Initial processing:• Wafer cleaning• thermal oxidation, H2O2

(≈ 40 nm, 15 min. @ 900ºC)• nitride LPCVD deposition

(≈ 80 nm)• Substrate selection: • moderately high resistivity

• 1st Mask Photoresist• spinning and baking

(25-50 ohm-cm)• (100) orientation• P- type.



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(≈ 0.5 - 1.0 µm)


Active Area Definition

Ph t lith h• Photolithography• Mask #1 pattern alignment

and UV exposure• Rinse away non-pattern PRy p

• Dry etch the Nitride layer• Plasma etch with Fluorine

P

PlasmaNForCF 44

• Strip Photoresist



7


Field Oxide Growth

W t O id (thi k SiO )• Wet Oxide (thick SiO2)• H2O (≈ 500 nm, 45 min. @

1000ºC)• LOCOS: Local Oxidation of Bird’s beak surface feature

Silicon

• Strip Nitride layer• Phosophoric acid orP • Phosophoric acid or

plasma etch

Instead of Si3N4 useInstead of Si3N4 useSiO2/PolySi/Si3N4=Poly Buffered LOCOS Results in less bird’s beak



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P-well Fabrication

• Photolithography• Mask #2 pattern alignment

Boron

• Mask #2 pattern alignment and UV exposure

• Rinse away non-pattern PR

P Implant• Ion Implantation

• B+ ion bombardment• Penetrate thin SiO2 and field

SiO

P

SiO2• 150-200 KeV for 1013 cm-2

• Implantation Energy and total dose adjusted for

PMOS NMOS

depth and concentration




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N-well Fabrication


Phosphorus



P ImplantN Implant

Phosphorus

• Ion Implantation• P+ ion bombardment• Penetrate thin SiO2 and field

SiOSiO2• 300-400 KeV for 1013 cm-2

• Implantation Energy and total dose adjusted for PMOS NMOS

P depth and concentration




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Thermal Anneal and Diffusion

• Thermal Anneal• Repair crystal lattice structure

d d t i l t tidamage due to implantation

• N and P Drive-in• Thermal diffusion of dopant to

P WellN Welle a d us o o dopa t to

shallower than desired depth• Drive-in is a cumulative

process!2-3 µm deep

PMOS NMOSP • Dry Furnace (N2 ambient)

• Anneal30 min @ 800˚C or

PMOS NMOS

@RTA 10 sec @ 1000˚C

• Drive-in4-6 hours @ 1000 ˚C - 1100 ˚C



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Threshold Adjustment, P-type NMOS


Boron



P WellN Well

P

• Ion Implantation• B+ ion bombardment• 50-75KeV for 1-5 x 1012 cm-2

• Implantation Energy and

P

P WellN Well • Implantation Energy and total dose adjusted for depth and concentrationPMOS NMOS




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Threshold Adjustment, N-type PMOS


Arsenic



P WellN Well

PN

• Ion Implantation• As+ ion bombardment• 75-100 KeV for 1-5 x 1012 cm-2

• Implantation Energy and

P

• Implantation Energy and total dose adjusted for depth and concentration

PMOS NMOSP




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Gate Oxide Growth

• Remove existing gate region

PN

• Remove existing gate region oxide• HF etch

P WellN Well • Furnace Steps• Thermal Anneal

• Dry Furnace (N2 ambient)• 30 min @ 800˚CPMOS NMOS

P

30 min @ 800 C• Oxide growth 3-5 nm

• O2 ambient• 0.5-1 hour @ 800˚C

PMOS NMOS



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Polysilicon Gate Deposition

• LPCVD Deposition of Si

PN

• Silane

• Amorphous or polycrystallineP WellN Well

Amorphous or polycrystalline silicon layer results

• 0.3-0.5 um

I I l t tiP

• Ion Implantation • P+ or As+ (N+) implant dopes

the poly (typically 5 x 1015 cm-2)

PMOS NMOS

( yp y )



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Gate Patterning

Ph t lith h

PN


and UV exposure• Rinse away non-pattern PR

P WellN Well

PNy p

• Plasma Etch• Anisotropic etch

• Vertical etch rate high

P

• Vertical etch rate high• Lateral etch rate low

• Clorine or Bromine based for SiO2 selectivity

PMOS NMOS



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Extension (LDD) Formation NMOS

PN

Phosphorus


and UV exposureP WellN Well

N- Implant and UV exposure• Rinse away non-pattern PR

• Ion ImplantationP+ i b b d t

P

LDD:

• P+ ion bombardment• 50 KeV for 5 x 1013 cm-2


PMOS NMOS

LDD:• Lightly Doped Drain• Reduce short channel effects due to gate voltage

magnitudes and electric fields

p



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• Source and Drain must be layered as NMOS:N+N-P or PMOS: P+P-N


Extension (LDD) Formation PMOS

Boron • Photolithography• Mask #8 pattern alignment

and UV exposure

P WellN Well

PN

N - ImplantP- Implant


• Ion ImplantationB+ i b b d t

P

• B+ ion bombardment• 50 KeV for 5 x 1013 cm-2


PMOS NMOS

p



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SiO2 Spacer Deposition

• CVD or LPCVD Deposition of

PN

SiO2• Silane and Oxygen

• Or

P WellN Well

N- ImplantP- ImplantOr

• 0.5 um

P id i b t t

P

• Provides spacing between gate and source-drain.

• Reduce field at gate edgePMOS NMOS



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Anisotropic Spacer Etch

Ph t lith hPN

N- ImplantP- Implant

• Photolithography• Mask #6 oversized pattern

alignment and UV exposure• Rinse away non-pattern PR

P WellN Welly p

• Plasma Etch• Anisotropic etch

• Vertical etch rate highP

• Vertical etch rate high• Lateral etch rate low

• Flourine based

PMOS NMOS




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NMOS Source and Drain Implant

• Screen Oxide Growth

Arsenic

• Screen Oxide Growth• Thin SiO2 layer ~10 nm to

scatter the implanted ions• Reduce channeling

PN

N+ Implant


and UV exposureP WellN Well


• Ion ImplantationA i b b d tPMOS NMOS

P • As+ ion bombardment• 75 KeV for 2-4 x 1015cm-2


PMOS NMOS



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p


PMOS Source and Drain Implant

Boron



P WellN Well

PN

N+ ImplantP+ Implant


• Ion Implantation• B+ ion bombardment

1 2

P

• 5-10 KeV for 1-3 x 1015cm-2

• Strip PhotoresistPMOS NMOS



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Thermal Annealing

• Thermal Anneal• Repair crystal lattice structure

d d t i l t ti

P W llN W ll

PNP+ P+ N+ N+damage due to implantation

• N+ and P+ Drive-in• Thermal diffusion of dopant to P WellN Well e a d us o o dopa t to

shallower than desired depth• Drive-in is a cumulative

process!PMOS NMOS

P • Dry Furnace (N2 ambient)• Anneal

30 min @ 900˚C or

PMOS NMOS

@RTA 60 sec @ 1000 ˚C - 1050 ˚CTransient Enhanced Diffusion (TED)

• Higher than normal diffusivity due to crystal damage



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Contact Openings

P WellN Well

PNP+ P+ N+ N+

• HF etch to remove thin SiO2• Remove screen oxide from

drain, source and ploy gate regions

• Dip for a few secondsPMOS NMOSP

LDD and Sidewall structure• NMOS: Lateral N+ N- P N- N+• PMOS: Lateral P+ P- N P- P+



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Contacts and Interconnects• Titanium sputtering local contacts• Conformal Coat with SiO22

• Planarization• Tungsten Plug vias• Aluminum Metal Deposition• Repeat

C t– Coat– Planarize– Plug– Metal deposition



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Titanium Deposition

PNP+ P+ N+ N+ • Ti is deposited by sputtering

P WellN Well

sputtering (typically 100 nm).

• Ti target hit with Ar+ ions in a

h bP

vacuum chamber

Th Ti i d i

PMOS NMOS

P W llN W ll

PNP+ P+ N+ N+

• The Ti is reacted in an N2 ambient,

• Forms TiSi2 and TiN(typically 1 min @ 600 -P WellN Well (typically 1 min @ 600 700 ˚C).

• TiSi2 has excellent contact characteristicsTiN d t b tPMOS NMOS



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P• TiN does not, but can

be used for local wiringPMOS NMOS


Local TiN Interconnect

PNP+ P+ N+ N+



P WellN Well


• TiN etch• NH4OH:H202:H20 (1:1:5)

P


• Thermal Treat in Ar

PMOS NMOSThermal Treat in Ar• 1 min @ 800 ˚C



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Conformal Coat and Planarize

PNP+ P+ N+ N+

• Conformal layer of SiO2 is deposited by CVD or LPCVD

P WellN Well

CVD or LPCVD (typically 1 µm)• PSG or BPSG• Surface passivation

Glass reflo for

P

• Glass reflow for partial planarizationPMOS NMOS

PNP+ P+ N+ N+• Chemical Mechanical

Polishing (CMP)• Planarize the wafer

P WellN Well surface• Polish with high pH

silica slurry



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PPMOS NMOS


Vias to 1st Metal


and UV exposure

P WellN Well

PNP+ P+ N+ N+


• SiO2 plasma etchA i t i t h

P

• Anisotropic etch

• Strip PhotoresistPMOS NMOSP



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Via Deposition – Tungsten PlugsTiNW

PNP+ P+ N+ N+

• TiN or Ti/TiN barrier layer • Sputtering or CVD

(few tens of nm)P WellN Well

(few tens of nm)

• CVD Tungsten (W)

PPMOS NMOS

• Chemical Mechanical Polishing (CMP)

• Planarize the wafer

PNP+ P+ N+ N+

Planarize the wafer surface

• Polish with high pH silica slurry

P WellN Well

PMOS NMOSSILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin


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PPMOS NMOS


Damascene Process• Etch Contact Holes or Line Trenches• Fill etched regionsg• Planarize

– CMP processAl t i l th t “ fl d h l t h– Also removes material that “overflowed holes or trenches

• Also used in reference to copper line metal layer deposition



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Metal #1 Deposition

• Photolithographyg p y• Mask #13 pattern alignment


P WellN Well

PNP+ P+ N+ N+ • Sputtered Aluminum • Al with small amounts of

Si and Cu

P

• Cu reduces electromigration

• Anisotropic plasma etchPMOS NMOS




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Multiple Metal Layers

• Deposits Oxide Layer• CMP

Ph t lith h M k #14• Photolithography Mask #14• Etch Vias• Deposit via material• CMP

P WellN Well

PNP+ P+ N+ N+

C• Photolithography Mask #15• Deposit Next Metal Layer

Final passivation layer ofP WellN Well • Final passivation layer of Si3N4 is deposited by PECVD and patterned with Mask #16.PMOS NMOS

P

• Final anneal and alloy in forming gas (10% H2 in N2)

• 30 min @ 400 450 ˚C

PMOS NMOS



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• 30 min @ 400-450 C


Intel µprocessor chip 52MB SRAM chips on a 12” wafer

• Photos of state-of-the-art CMOS chips (from Intel website).• 90 nm technology.




Summary of Key ideas

• This chapter serves as an introduction to CMOS technology.

• It provides a perspective on how individual technologies like oxidation andIt provides a perspective on how individual technologies like oxidation and ion implantation are actually used.

• There are many variations on CMOS process flows used in industry.

• The process described here is intended to be representative, although it is simplified compared to many current process flows.

• Some process options are described in Chapter 2 in the text.

• Perhaps the most important point is that while individual process steps like oxidation and ion implantation are usually studied as isolated technologiesoxidation and ion implantation are usually studied as isolated technologies, their actual use is complicated by the fact that IC manufacturing consists of many sequential steps, each of which must integrate together to make the whole process flow work in manufacturing.



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Ch02