Central Processing Unit - Prof H.M.Patel - Homehmpatel123.weebly.com/uploads/2/3/7/3/23736061/che-5__coa.pdfCentral Processing Unit. Created by : - Sanjay Patel 2 Outline Introduction

SUBJECT:- COA

TOPICS:-CPU

Created by : - Sanjay Patel

Central Processing Unit

Created by : - Sanjay Patel2

Outline Introduction

General register Organization

Stack Organization

Instruction Format

Addressing Modes

Data transfer and manipulation

Program Control

RISC and CISC


Introduction Referred “brain” of the system

Main portion

Contain electronic circuit

ALU + CU = CPU

Arithmetic logic

unit

Control unit CPU


CPU Architecture


General Register Organization

Register:- which stores information in bit of sequence

like 00,01,0011,00110. It is made by flip-flop and basic

element of processor.

How to add simple two number in register

MOV R1,#50H -- 50H value is store in R1

MOV R2,#60H -- 60H value is store in R2

ADD R1 + R2 -- perform add operation

STA R3 -- store the result


Bus Organization

Bus:- Bus is a path(of a group of wires) over which

information is transferred, from any of several

sources to any of several destinations

There are three type of bus.

Address Bus

Data Bus

Control Bus


Example

To perform the operation R3 R1+R2

1. SELA :- To place the content of R1 into bus A

2. SELB :- To place the content of R2 into bus B

3. SELOPR :- To Perform addition operation A+B

4. SELREG :- To place the result in R3

Format of control word

12 10 9 7 6 4 3 0

SELA SELB SELOPR SELREG


Bus Organization


Stack Organization

Stack:- Data operated on by a program can be stored in

the CPU register and in the computer memory. It can be

organized properly for easy access like array data

structure.

Most of the computers supports an important data

structure known as STACK.

LIFO

FIFO

Stack area:- The part of register array or memory used

for stack is called stack area.

Stack pointer:- The register that holds the address for

the stack is called stack pointer.


Register Stack


Example


Memory Stack

Program

Memory

Data ( Operand )

Memory

Stack Memory

PC

AR

SP

DR


Notation

A + B :- Infix Notation

+ A B :- Prefix or polish notation

A B + :- postfix or reverse polish notation


Example


Example

Use reverse polish notation

34 + 26 + 10 * 8 + * (Answer= 616)

Use reverse polish notation

x y – 3 * v u * 2 * w + +

Where, x=5, y=2, v=3, u=4 and w=6. (Answer=39)


Reverse polish notation

Convert ( A * B + C * D + E * F ) into reverse polish

notation .

A B * C D * E F * ++ Push A A

B * C D * E F * ++ Push B B

* C D * E F * ++ MUL A * B

C D * E F * ++ Push C C

D * E F * ++ Push D D

* E F * ++ MUL C * D

E F * ++ Push E E

F * ++ Push F F

* ++ MUL E * F

++ ADD +

+ ADD +



Evaluate ( 8 + 2 * 5) / ( 1 + 3 * 2 - 4) into RPN.

8 2 5 * + 1 3 2 * + 4 - / Push 8 8

2 5 * + 1 3 2 * + 4 - / Push 2 8,2

5 * + 1 3 2 * + 4 - / Push 5 8,2,5

* + 1 3 2 * + 4 - / MUL 8,10

+ 1 3 2 * + 4 - / ADD 18

1 3 2 * + 4 - / Push 1 18,1

3 2 * + 4 - / Push 3 18,1,3

2 * + 4 - / Push 2 18,1,3,2

* + 4 - / MUL 18,1,6

+ 4 - / ADD 18,7

4 - / Push 4 18,7,4

- / SUB 18,3

/ DIV 6



1. Evaluate A * B + A * ( B * D + C * E) into RPN.

2. Evaluate A + B *( C * D + E * (F + G) into RPN.


ANSWER

1. A B * A B D * C E * + * +

2. A B F G + E * C D * + B * + .


Instruction Format Each instruction of the CPU contain specific

information fields, which are required to execute

it. These information fields of instruction are

called elements of instruction.

Operation

code

Source/destination

operand

Source

operand

address

Destination

operand

address

Next

instruction

address

Three address instruction

Two address instruction

One address instruction

Zero address instruction


Three address instruction


Two address instruction


One address instruction


Zero Address instruction

In these instruction, the location of all operand

are defined implicitly, such as instruction are

found in machine in a structure called a

Pushdown stack.


Example

Write a program to evaluate the arithmetic

statement Y= (A+B) * (C+D) using three address,

two address, one address and zero address.


Cont’d..


Addressing mode

Register mode

Absolute mode or Direct addressing mode

Indirect addressing mode

Immediate mode

Index mode

Relative mode

Auto increment mode

Auto decrement mode


Register mode

Register mode :- The operand is the content of

processor register.

Example :- MOV R1,R2

This instruction copies the content of register

R2 to register R1


Absolute mode OR Direct mode

Absolute mode OR Direct mode:- The address

of the location of the operand is given explicitly

as a part of the instruction.

Example :- MOVE A,2000

This instruction copies the content of memory

location 2000 into A register.


Indirect mode

Absolute mode OR Direct mode:- The effective

address of the operand is the content of register

or main memory location.

Example :- MOVE A,(R0)

This instruction copies the content of memory

addressed by the content of register R0 into

register A.


Direct and indirect Addressing mode

0 ADD 45722

Operand457

1 ADD 30035

1350300

Operand1350

+

AC

+

AC

Direct addressing Indirect addressing


Immediate mode

Immediate mode:- The operand is given

explicitly in the instruction.

Example:- MOV A,#20

The above instruction copies operand 20 in the

register A. The # indicate the value is an

immediate operand.


Index mode

Index mode:- The effective address of the

operand is generated by adding a constant value

called offset to the content of register

EA= offset + R1

Auto increment mode

Auto decrement mode


RISC

RISC is stand for reduced instruction set computer.


CISC

CISC is stand for complex instruction set computer.


RISC vs CISC

RISC CISC

Few instruction Many instruction

Fixed format instruction Variable format instruction

Clock rate is 50-150 MHz in 1993 Clock rate is 33-50 MHz in 1992

Simple instruction, taking one cycle Complex instruction, multiple cycle

Very few instruction refer memory Most of instruction refer memory

Instruction executed by hardware Instruction executed by micro program

Few addressing modes Many addressing modes

Multiple register set Single register set

Highly pipelined Less pipelined or not pipelined

Complexity is in the computer Complexity is in the micro program


RISC properties ( overlapping register window)


RISC properties ( overlapping register window)

To implement register to register operation

Register sets are organized into overlapped

window and act as small, fast buffer for holding a

subset of all variable.

The window divided into three fixed size areas.

Parameter register:- hold parameter passed

down from the procedure that called the current

procedure and result to be passed back up.

Local register:- are used for local variables, as

assigned by the compiler

Temporary register:- are used to exchange

parameter and result with the procedure called by

current procedure.


RISC Addressing mode

Register addressing:-

R3 M[R1+R2]

Immediate operand addressing:-

ADD R1, #100

Relative to PC addressing:-

JMP COND,R1(R2)


RISC and CISC Application

Network interface cards

Mobile frameworks

Transport logistics

Mobile web services

Security controller

Data collector

Touched based human machine interface

Mobile information system

Location planning

Warehouse logistics


Status Register (PSW)


Status register (PSW)

C-bit : Carry bit – It is set when the output carry

is 1 otherwise it is 0.

S-bit: Sign bit – It is set when MSB (Most

significant bit) of the result is 1 otherwise it is

zero.

Z-bit: Zero bit – It is set when the result is zero,

otherwise it is zero.

V- bit: overflow bit – if the result is too large

The collection of all status bits conditions in the

CPU is called a program status word(PSW)


Program interrupt

External interrupt

Internal interrupt

Program interrupt



Data transfer instruction

Data manipulation instruction

Program control instruction


Data transfer Instruction



Data manipulation instruction perform following

types of operation

Arithmetic operation

Logical operation

Shift and rotate operation


Arithmetic Operation


Logical Operation


Shift and Rotate Operation


Program control instruction

Thank You !

Created by :-

S A N J A Y P A T E L

Assistant Professor (I.T.)

Shankersinh Vaghela Bapu

Institute of Technology, Gandhinagar

Documents

Central Processing Unit - Prof H.M.Patel - Homehmpatel123.weebly.com/uploads/2/3/7/3/23736061/che-5__coa.pdfCentral Processing Unit. Created by : - Sanjay Patel 2 Outline Introduction